drm/amdgpu/powerplay: add smu smc_table_manager callback for vega20
For consistency with other asics. Reviewed-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher
parent
68e841abf8
commit
a476e925ba
@ -743,8 +743,8 @@ static int vega20_init_smc_table(struct pp_hwmgr *hwmgr)
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memcpy(pp_table, pptable_information->smc_pptable, sizeof(PPTable_t));
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result = vega20_copy_table_to_smc(hwmgr,
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(uint8_t *)pp_table, TABLE_PPTABLE);
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result = smum_smc_table_manager(hwmgr,
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(uint8_t *)pp_table, TABLE_PPTABLE, false);
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PP_ASSERT_WITH_CODE(!result,
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"[InitSMCTable] Failed to upload PPtable!",
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return result);
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@ -1067,7 +1067,7 @@ static int vega20_od8_initialize_default_settings(
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vega20_od8_set_feature_id(hwmgr);
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/* Set default values */
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ret = vega20_copy_table_from_smc(hwmgr, (uint8_t *)od_table, TABLE_OVERDRIVE);
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ret = smum_smc_table_manager(hwmgr, (uint8_t *)od_table, TABLE_OVERDRIVE, true);
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PP_ASSERT_WITH_CODE(!ret,
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"Failed to export over drive table!",
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return ret);
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@ -1195,7 +1195,7 @@ static int vega20_od8_initialize_default_settings(
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}
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}
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ret = vega20_copy_table_to_smc(hwmgr, (uint8_t *)od_table, TABLE_OVERDRIVE);
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ret = smum_smc_table_manager(hwmgr, (uint8_t *)od_table, TABLE_OVERDRIVE, false);
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PP_ASSERT_WITH_CODE(!ret,
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"Failed to import over drive table!",
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return ret);
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@ -1214,7 +1214,7 @@ static int vega20_od8_set_settings(
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struct vega20_od8_single_setting *od8_settings =
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data->od8_settings.od8_settings_array;
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ret = vega20_copy_table_from_smc(hwmgr, (uint8_t *)(&od_table), TABLE_OVERDRIVE);
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ret = smum_smc_table_manager(hwmgr, (uint8_t *)(&od_table), TABLE_OVERDRIVE, true);
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PP_ASSERT_WITH_CODE(!ret,
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"Failed to export over drive table!",
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return ret);
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@ -1271,7 +1271,7 @@ static int vega20_od8_set_settings(
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break;
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}
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ret = vega20_copy_table_to_smc(hwmgr, (uint8_t *)(&od_table), TABLE_OVERDRIVE);
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ret = smum_smc_table_manager(hwmgr, (uint8_t *)(&od_table), TABLE_OVERDRIVE, false);
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PP_ASSERT_WITH_CODE(!ret,
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"Failed to import over drive table!",
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return ret);
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@ -1841,7 +1841,7 @@ static int vega20_get_gpu_power(struct pp_hwmgr *hwmgr,
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int ret = 0;
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SmuMetrics_t metrics_table;
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ret = vega20_copy_table_from_smc(hwmgr, (uint8_t *)&metrics_table, TABLE_SMU_METRICS);
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ret = smum_smc_table_manager(hwmgr, (uint8_t *)&metrics_table, TABLE_SMU_METRICS, true);
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PP_ASSERT_WITH_CODE(!ret,
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"Failed to export SMU METRICS table!",
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return ret);
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@ -1893,7 +1893,7 @@ static int vega20_get_current_activity_percent(struct pp_hwmgr *hwmgr,
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int ret = 0;
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SmuMetrics_t metrics_table;
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ret = vega20_copy_table_from_smc(hwmgr, (uint8_t *)&metrics_table, TABLE_SMU_METRICS);
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ret = smum_smc_table_manager(hwmgr, (uint8_t *)&metrics_table, TABLE_SMU_METRICS, true);
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PP_ASSERT_WITH_CODE(!ret,
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"Failed to export SMU METRICS table!",
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return ret);
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@ -2612,18 +2612,18 @@ static int vega20_odn_edit_dpm_table(struct pp_hwmgr *hwmgr,
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data->gfxclk_overdrive = false;
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data->memclk_overdrive = false;
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ret = vega20_copy_table_from_smc(hwmgr,
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(uint8_t *)od_table,
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TABLE_OVERDRIVE);
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ret = smum_smc_table_manager(hwmgr,
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(uint8_t *)od_table,
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TABLE_OVERDRIVE, true);
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PP_ASSERT_WITH_CODE(!ret,
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"Failed to export overdrive table!",
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return ret);
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break;
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case PP_OD_COMMIT_DPM_TABLE:
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ret = vega20_copy_table_to_smc(hwmgr,
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(uint8_t *)od_table,
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TABLE_OVERDRIVE);
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ret = smum_smc_table_manager(hwmgr,
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(uint8_t *)od_table,
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TABLE_OVERDRIVE, false);
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PP_ASSERT_WITH_CODE(!ret,
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"Failed to import overdrive table!",
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return ret);
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@ -2847,8 +2847,8 @@ static int vega20_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
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if ((data->water_marks_bitmap & WaterMarksExist) &&
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!(data->water_marks_bitmap & WaterMarksLoaded)) {
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result = vega20_copy_table_to_smc(hwmgr,
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(uint8_t *)wm_table, TABLE_WATERMARKS);
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result = smum_smc_table_manager(hwmgr,
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(uint8_t *)wm_table, TABLE_WATERMARKS, false);
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PP_ASSERT_WITH_CODE(!result,
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"Failed to update WMTABLE!",
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return result);
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@ -160,8 +160,8 @@ static uint32_t vega20_get_argument(struct pp_hwmgr *hwmgr)
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* @param hwmgr the address of the HW manager
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* @param table_id the driver's table ID to copy from
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*/
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int vega20_copy_table_from_smc(struct pp_hwmgr *hwmgr,
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uint8_t *table, int16_t table_id)
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static int vega20_copy_table_from_smc(struct pp_hwmgr *hwmgr,
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uint8_t *table, int16_t table_id)
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{
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struct vega20_smumgr *priv =
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(struct vega20_smumgr *)(hwmgr->smu_backend);
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@ -200,8 +200,8 @@ int vega20_copy_table_from_smc(struct pp_hwmgr *hwmgr,
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* @param hwmgr the address of the HW manager
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* @param table_id the table to copy from
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*/
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int vega20_copy_table_to_smc(struct pp_hwmgr *hwmgr,
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uint8_t *table, int16_t table_id)
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static int vega20_copy_table_to_smc(struct pp_hwmgr *hwmgr,
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uint8_t *table, int16_t table_id)
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{
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struct vega20_smumgr *priv =
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(struct vega20_smumgr *)(hwmgr->smu_backend);
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@ -560,6 +560,19 @@ static bool vega20_is_dpm_running(struct pp_hwmgr *hwmgr)
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return false;
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}
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static int vega20_smc_table_manager(struct pp_hwmgr *hwmgr, uint8_t *table,
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uint16_t table_id, bool rw)
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{
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int ret;
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if (rw)
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ret = vega20_copy_table_from_smc(hwmgr, table, table_id);
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else
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ret = vega20_copy_table_to_smc(hwmgr, table, table_id);
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return ret;
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}
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const struct pp_smumgr_func vega20_smu_funcs = {
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.smu_init = &vega20_smu_init,
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.smu_fini = &vega20_smu_fini,
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@ -571,4 +584,5 @@ const struct pp_smumgr_func vega20_smu_funcs = {
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.upload_pptable_settings = NULL,
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.is_dpm_running = vega20_is_dpm_running,
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.get_argument = vega20_get_argument,
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.smc_table_manager = vega20_smc_table_manager,
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};
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@ -47,10 +47,6 @@ struct vega20_smumgr {
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#define SMU_FEATURES_HIGH_MASK 0xFFFFFFFF00000000
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#define SMU_FEATURES_HIGH_SHIFT 32
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int vega20_copy_table_from_smc(struct pp_hwmgr *hwmgr,
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uint8_t *table, int16_t table_id);
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int vega20_copy_table_to_smc(struct pp_hwmgr *hwmgr,
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uint8_t *table, int16_t table_id);
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int vega20_enable_smc_features(struct pp_hwmgr *hwmgr,
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bool enable, uint64_t feature_mask);
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int vega20_get_enabled_smc_features(struct pp_hwmgr *hwmgr,
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