drm/amd/display: Add TMDS DC balancer control
Add TMDS balancer control to the list of available encoder registers for DCN 30. Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -55,7 +55,8 @@
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SRI(DP_DPHY_HBR2_PATTERN_CONTROL, DP, id)
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#define LINK_ENCODER_MASK_SH_LIST_DCN30(mask_sh) \
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LINK_ENCODER_MASK_SH_LIST_DCN20(mask_sh)
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LINK_ENCODER_MASK_SH_LIST_DCN20(mask_sh),\
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LE_SF(DIG0_TMDS_DCBALANCER_CONTROL, TMDS_SYNC_DCBAL_EN, mask_sh)
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#define DPCS_DCN3_MASK_SH_LIST(mask_sh)\
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DPCS_DCN2_MASK_SH_LIST(mask_sh),\
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