qlge: Add serdes reg blocks dump to firmware dump.
Signed-off-by: Ron Mercer <ron.mercer@qlogic.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Ron Mercer
David S. Miller
parent
24bb55b480
commit
a48c86fdb1
@ -19,6 +19,318 @@ static u32 ql_read_other_func_reg(struct ql_adapter *qdev,
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return reg_val;
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}
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/* Write a NIC register from the alternate function. */
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static int ql_write_other_func_reg(struct ql_adapter *qdev,
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u32 reg, u32 reg_val)
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{
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u32 register_to_read;
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int status = 0;
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register_to_read = MPI_NIC_REG_BLOCK
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| MPI_NIC_READ
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| (qdev->alt_func << MPI_NIC_FUNCTION_SHIFT)
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| reg;
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status = ql_write_mpi_reg(qdev, register_to_read, reg_val);
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return status;
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}
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static int ql_wait_other_func_reg_rdy(struct ql_adapter *qdev, u32 reg,
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u32 bit, u32 err_bit)
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{
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u32 temp;
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int count = 10;
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while (count) {
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temp = ql_read_other_func_reg(qdev, reg);
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/* check for errors */
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if (temp & err_bit)
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return -1;
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else if (temp & bit)
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return 0;
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mdelay(10);
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count--;
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}
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return -1;
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}
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static int ql_read_other_func_serdes_reg(struct ql_adapter *qdev, u32 reg,
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u32 *data)
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{
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int status;
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/* wait for reg to come ready */
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status = ql_wait_other_func_reg_rdy(qdev, XG_SERDES_ADDR / 4,
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XG_SERDES_ADDR_RDY, 0);
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if (status)
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goto exit;
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/* set up for reg read */
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ql_write_other_func_reg(qdev, XG_SERDES_ADDR/4, reg | PROC_ADDR_R);
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/* wait for reg to come ready */
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status = ql_wait_other_func_reg_rdy(qdev, XG_SERDES_ADDR / 4,
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XG_SERDES_ADDR_RDY, 0);
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if (status)
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goto exit;
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/* get the data */
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*data = ql_read_other_func_reg(qdev, (XG_SERDES_DATA / 4));
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exit:
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return status;
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}
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/* Read out the SERDES registers */
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static int ql_read_serdes_reg(struct ql_adapter *qdev, u32 reg, u32 * data)
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{
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int status;
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/* wait for reg to come ready */
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status = ql_wait_reg_rdy(qdev, XG_SERDES_ADDR, XG_SERDES_ADDR_RDY, 0);
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if (status)
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goto exit;
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/* set up for reg read */
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ql_write32(qdev, XG_SERDES_ADDR, reg | PROC_ADDR_R);
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/* wait for reg to come ready */
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status = ql_wait_reg_rdy(qdev, XG_SERDES_ADDR, XG_SERDES_ADDR_RDY, 0);
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if (status)
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goto exit;
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/* get the data */
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*data = ql_read32(qdev, XG_SERDES_DATA);
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exit:
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return status;
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}
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static void ql_get_both_serdes(struct ql_adapter *qdev, u32 addr,
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u32 *direct_ptr, u32 *indirect_ptr,
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unsigned int direct_valid, unsigned int indirect_valid)
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{
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unsigned int status;
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status = 1;
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if (direct_valid)
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status = ql_read_serdes_reg(qdev, addr, direct_ptr);
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/* Dead fill any failures or invalids. */
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if (status)
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*direct_ptr = 0xDEADBEEF;
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status = 1;
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if (indirect_valid)
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status = ql_read_other_func_serdes_reg(
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qdev, addr, indirect_ptr);
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/* Dead fill any failures or invalids. */
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if (status)
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*indirect_ptr = 0xDEADBEEF;
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}
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static int ql_get_serdes_regs(struct ql_adapter *qdev,
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struct ql_mpi_coredump *mpi_coredump)
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{
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int status;
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unsigned int xfi_direct_valid, xfi_indirect_valid, xaui_direct_valid;
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unsigned int xaui_indirect_valid, i;
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u32 *direct_ptr, temp;
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u32 *indirect_ptr;
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xfi_direct_valid = xfi_indirect_valid = 0;
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xaui_direct_valid = xaui_indirect_valid = 1;
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/* The XAUI needs to be read out per port */
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if (qdev->func & 1) {
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/* We are NIC 2 */
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status = ql_read_other_func_serdes_reg(qdev,
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XG_SERDES_XAUI_HSS_PCS_START, &temp);
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if (status)
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temp = XG_SERDES_ADDR_XAUI_PWR_DOWN;
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if ((temp & XG_SERDES_ADDR_XAUI_PWR_DOWN) ==
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XG_SERDES_ADDR_XAUI_PWR_DOWN)
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xaui_indirect_valid = 0;
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status = ql_read_serdes_reg(qdev,
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XG_SERDES_XAUI_HSS_PCS_START, &temp);
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if (status)
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temp = XG_SERDES_ADDR_XAUI_PWR_DOWN;
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if ((temp & XG_SERDES_ADDR_XAUI_PWR_DOWN) ==
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XG_SERDES_ADDR_XAUI_PWR_DOWN)
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xaui_direct_valid = 0;
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} else {
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/* We are NIC 1 */
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status = ql_read_other_func_serdes_reg(qdev,
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XG_SERDES_XAUI_HSS_PCS_START, &temp);
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if (status)
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temp = XG_SERDES_ADDR_XAUI_PWR_DOWN;
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if ((temp & XG_SERDES_ADDR_XAUI_PWR_DOWN) ==
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XG_SERDES_ADDR_XAUI_PWR_DOWN)
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xaui_indirect_valid = 0;
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status = ql_read_serdes_reg(qdev,
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XG_SERDES_XAUI_HSS_PCS_START, &temp);
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if (status)
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temp = XG_SERDES_ADDR_XAUI_PWR_DOWN;
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if ((temp & XG_SERDES_ADDR_XAUI_PWR_DOWN) ==
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XG_SERDES_ADDR_XAUI_PWR_DOWN)
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xaui_direct_valid = 0;
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}
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/*
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* XFI register is shared so only need to read one
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* functions and then check the bits.
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*/
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status = ql_read_serdes_reg(qdev, XG_SERDES_ADDR_STS, &temp);
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if (status)
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temp = 0;
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if ((temp & XG_SERDES_ADDR_XFI1_PWR_UP) ==
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XG_SERDES_ADDR_XFI1_PWR_UP) {
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/* now see if i'm NIC 1 or NIC 2 */
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if (qdev->func & 1)
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/* I'm NIC 2, so the indirect (NIC1) xfi is up. */
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xfi_indirect_valid = 1;
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else
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xfi_direct_valid = 1;
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}
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if ((temp & XG_SERDES_ADDR_XFI2_PWR_UP) ==
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XG_SERDES_ADDR_XFI2_PWR_UP) {
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/* now see if i'm NIC 1 or NIC 2 */
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if (qdev->func & 1)
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/* I'm NIC 2, so the indirect (NIC1) xfi is up. */
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xfi_direct_valid = 1;
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else
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xfi_indirect_valid = 1;
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}
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/* Get XAUI_AN register block. */
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if (qdev->func & 1) {
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/* Function 2 is direct */
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direct_ptr = mpi_coredump->serdes2_xaui_an;
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indirect_ptr = mpi_coredump->serdes_xaui_an;
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} else {
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/* Function 1 is direct */
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direct_ptr = mpi_coredump->serdes_xaui_an;
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indirect_ptr = mpi_coredump->serdes2_xaui_an;
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}
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for (i = 0; i <= 0x000000034; i += 4, direct_ptr++, indirect_ptr++)
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ql_get_both_serdes(qdev, i, direct_ptr, indirect_ptr,
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xaui_direct_valid, xaui_indirect_valid);
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/* Get XAUI_HSS_PCS register block. */
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if (qdev->func & 1) {
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direct_ptr =
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mpi_coredump->serdes2_xaui_hss_pcs;
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indirect_ptr =
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mpi_coredump->serdes_xaui_hss_pcs;
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} else {
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direct_ptr =
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mpi_coredump->serdes_xaui_hss_pcs;
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indirect_ptr =
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mpi_coredump->serdes2_xaui_hss_pcs;
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}
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for (i = 0x800; i <= 0x880; i += 4, direct_ptr++, indirect_ptr++)
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ql_get_both_serdes(qdev, i, direct_ptr, indirect_ptr,
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xaui_direct_valid, xaui_indirect_valid);
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/* Get XAUI_XFI_AN register block. */
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if (qdev->func & 1) {
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direct_ptr = mpi_coredump->serdes2_xfi_an;
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indirect_ptr = mpi_coredump->serdes_xfi_an;
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} else {
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direct_ptr = mpi_coredump->serdes_xfi_an;
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indirect_ptr = mpi_coredump->serdes2_xfi_an;
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}
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for (i = 0x1000; i <= 0x1034; i += 4, direct_ptr++, indirect_ptr++)
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ql_get_both_serdes(qdev, i, direct_ptr, indirect_ptr,
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xfi_direct_valid, xfi_indirect_valid);
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/* Get XAUI_XFI_TRAIN register block. */
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if (qdev->func & 1) {
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direct_ptr = mpi_coredump->serdes2_xfi_train;
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indirect_ptr =
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mpi_coredump->serdes_xfi_train;
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} else {
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direct_ptr = mpi_coredump->serdes_xfi_train;
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indirect_ptr =
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mpi_coredump->serdes2_xfi_train;
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}
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for (i = 0x1050; i <= 0x107c; i += 4, direct_ptr++, indirect_ptr++)
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ql_get_both_serdes(qdev, i, direct_ptr, indirect_ptr,
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xfi_direct_valid, xfi_indirect_valid);
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/* Get XAUI_XFI_HSS_PCS register block. */
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if (qdev->func & 1) {
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direct_ptr =
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mpi_coredump->serdes2_xfi_hss_pcs;
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indirect_ptr =
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mpi_coredump->serdes_xfi_hss_pcs;
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} else {
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direct_ptr =
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mpi_coredump->serdes_xfi_hss_pcs;
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indirect_ptr =
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mpi_coredump->serdes2_xfi_hss_pcs;
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}
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for (i = 0x1800; i <= 0x1838; i += 4, direct_ptr++, indirect_ptr++)
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ql_get_both_serdes(qdev, i, direct_ptr, indirect_ptr,
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xfi_direct_valid, xfi_indirect_valid);
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/* Get XAUI_XFI_HSS_TX register block. */
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if (qdev->func & 1) {
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direct_ptr =
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mpi_coredump->serdes2_xfi_hss_tx;
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indirect_ptr =
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mpi_coredump->serdes_xfi_hss_tx;
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} else {
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direct_ptr = mpi_coredump->serdes_xfi_hss_tx;
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indirect_ptr =
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mpi_coredump->serdes2_xfi_hss_tx;
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}
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for (i = 0x1c00; i <= 0x1c1f; i++, direct_ptr++, indirect_ptr++)
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ql_get_both_serdes(qdev, i, direct_ptr, indirect_ptr,
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xfi_direct_valid, xfi_indirect_valid);
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/* Get XAUI_XFI_HSS_RX register block. */
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if (qdev->func & 1) {
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direct_ptr =
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mpi_coredump->serdes2_xfi_hss_rx;
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indirect_ptr =
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mpi_coredump->serdes_xfi_hss_rx;
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} else {
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direct_ptr = mpi_coredump->serdes_xfi_hss_rx;
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indirect_ptr =
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mpi_coredump->serdes2_xfi_hss_rx;
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}
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for (i = 0x1c40; i <= 0x1c5f; i++, direct_ptr++, indirect_ptr++)
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ql_get_both_serdes(qdev, i, direct_ptr, indirect_ptr,
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xfi_direct_valid, xfi_indirect_valid);
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/* Get XAUI_XFI_HSS_PLL register block. */
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if (qdev->func & 1) {
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direct_ptr =
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mpi_coredump->serdes2_xfi_hss_pll;
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indirect_ptr =
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mpi_coredump->serdes_xfi_hss_pll;
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} else {
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direct_ptr =
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mpi_coredump->serdes_xfi_hss_pll;
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indirect_ptr =
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mpi_coredump->serdes2_xfi_hss_pll;
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}
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for (i = 0x1e00; i <= 0x1e1f; i++, direct_ptr++, indirect_ptr++)
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ql_get_both_serdes(qdev, i, direct_ptr, indirect_ptr,
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xfi_direct_valid, xfi_indirect_valid);
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return 0;
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}
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static int ql_get_ets_regs(struct ql_adapter *qdev, u32 * buf)
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{
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int status = 0;
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@ -413,6 +725,111 @@ int ql_core_dump(struct ql_adapter *qdev, struct ql_mpi_coredump *mpi_coredump)
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ql_read_other_func_reg(qdev, (i * sizeof(u32)) / 4);
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}
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/* Rev C. Step 20a */
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ql_build_coredump_seg_header(&mpi_coredump->xaui_an_hdr,
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XAUI_AN_SEG_NUM,
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sizeof(struct mpi_coredump_segment_header) +
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sizeof(mpi_coredump->serdes_xaui_an),
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"XAUI AN Registers");
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/* Rev C. Step 20b */
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ql_build_coredump_seg_header(&mpi_coredump->xaui_hss_pcs_hdr,
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XAUI_HSS_PCS_SEG_NUM,
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sizeof(struct mpi_coredump_segment_header) +
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sizeof(mpi_coredump->serdes_xaui_hss_pcs),
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"XAUI HSS PCS Registers");
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ql_build_coredump_seg_header(&mpi_coredump->xfi_an_hdr, XFI_AN_SEG_NUM,
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sizeof(struct mpi_coredump_segment_header) +
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sizeof(mpi_coredump->serdes_xfi_an),
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"XFI AN Registers");
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ql_build_coredump_seg_header(&mpi_coredump->xfi_train_hdr,
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XFI_TRAIN_SEG_NUM,
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sizeof(struct mpi_coredump_segment_header) +
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sizeof(mpi_coredump->serdes_xfi_train),
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"XFI TRAIN Registers");
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ql_build_coredump_seg_header(&mpi_coredump->xfi_hss_pcs_hdr,
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XFI_HSS_PCS_SEG_NUM,
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sizeof(struct mpi_coredump_segment_header) +
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sizeof(mpi_coredump->serdes_xfi_hss_pcs),
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"XFI HSS PCS Registers");
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ql_build_coredump_seg_header(&mpi_coredump->xfi_hss_tx_hdr,
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XFI_HSS_TX_SEG_NUM,
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sizeof(struct mpi_coredump_segment_header) +
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sizeof(mpi_coredump->serdes_xfi_hss_tx),
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"XFI HSS TX Registers");
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ql_build_coredump_seg_header(&mpi_coredump->xfi_hss_rx_hdr,
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XFI_HSS_RX_SEG_NUM,
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sizeof(struct mpi_coredump_segment_header) +
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sizeof(mpi_coredump->serdes_xfi_hss_rx),
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"XFI HSS RX Registers");
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ql_build_coredump_seg_header(&mpi_coredump->xfi_hss_pll_hdr,
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XFI_HSS_PLL_SEG_NUM,
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sizeof(struct mpi_coredump_segment_header) +
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sizeof(mpi_coredump->serdes_xfi_hss_pll),
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"XFI HSS PLL Registers");
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ql_build_coredump_seg_header(&mpi_coredump->xaui2_an_hdr,
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XAUI2_AN_SEG_NUM,
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sizeof(struct mpi_coredump_segment_header) +
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sizeof(mpi_coredump->serdes2_xaui_an),
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"XAUI2 AN Registers");
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ql_build_coredump_seg_header(&mpi_coredump->xaui2_hss_pcs_hdr,
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XAUI2_HSS_PCS_SEG_NUM,
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sizeof(struct mpi_coredump_segment_header) +
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sizeof(mpi_coredump->serdes2_xaui_hss_pcs),
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"XAUI2 HSS PCS Registers");
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ql_build_coredump_seg_header(&mpi_coredump->xfi2_an_hdr,
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XFI2_AN_SEG_NUM,
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sizeof(struct mpi_coredump_segment_header) +
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sizeof(mpi_coredump->serdes2_xfi_an),
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"XFI2 AN Registers");
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ql_build_coredump_seg_header(&mpi_coredump->xfi2_train_hdr,
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XFI2_TRAIN_SEG_NUM,
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sizeof(struct mpi_coredump_segment_header) +
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sizeof(mpi_coredump->serdes2_xfi_train),
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"XFI2 TRAIN Registers");
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ql_build_coredump_seg_header(&mpi_coredump->xfi2_hss_pcs_hdr,
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XFI2_HSS_PCS_SEG_NUM,
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sizeof(struct mpi_coredump_segment_header) +
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sizeof(mpi_coredump->serdes2_xfi_hss_pcs),
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"XFI2 HSS PCS Registers");
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ql_build_coredump_seg_header(&mpi_coredump->xfi2_hss_tx_hdr,
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XFI2_HSS_TX_SEG_NUM,
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sizeof(struct mpi_coredump_segment_header) +
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sizeof(mpi_coredump->serdes2_xfi_hss_tx),
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"XFI2 HSS TX Registers");
|
||||
|
||||
ql_build_coredump_seg_header(&mpi_coredump->xfi2_hss_rx_hdr,
|
||||
XFI2_HSS_RX_SEG_NUM,
|
||||
sizeof(struct mpi_coredump_segment_header) +
|
||||
sizeof(mpi_coredump->serdes2_xfi_hss_rx),
|
||||
"XFI2 HSS RX Registers");
|
||||
|
||||
ql_build_coredump_seg_header(&mpi_coredump->xfi2_hss_pll_hdr,
|
||||
XFI2_HSS_PLL_SEG_NUM,
|
||||
sizeof(struct mpi_coredump_segment_header) +
|
||||
sizeof(mpi_coredump->serdes2_xfi_hss_pll),
|
||||
"XFI2 HSS PLL Registers");
|
||||
|
||||
status = ql_get_serdes_regs(qdev, mpi_coredump);
|
||||
if (status) {
|
||||
QPRINTK(qdev, DRV, ERR,
|
||||
"Failed Dump of Serdes Registers. Status = 0x%.08x\n",
|
||||
status);
|
||||
goto err;
|
||||
}
|
||||
|
||||
ql_build_coredump_seg_header(&mpi_coredump->core_regs_seg_hdr,
|
||||
CORE_SEG_NUM,
|
||||
sizeof(mpi_coredump->core_regs_seg_hdr) +
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user