ARM: OMAP2/3: Remove OMAP2_32KSYNCT_BASE
Use processor specific defines instead. As an extra bonus, this patch fixes the problem of CONFIG_DEBUG_SPINLOCK calling sched_clock before we have things initialized: http://patchwork.kernel.org/patch/15810/ Signed-off-by: Tony Lindgren <tony@atomide.com>
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@ -128,7 +128,7 @@ omap242x_sdi_prcm_voltctrl:
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prcm_mask_val:
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.word 0xFFFF3FFC
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omap242x_sdi_timer_32ksynct_cr:
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.word IO_ADDRESS(OMAP2_32KSYNCT_BASE + 0x010)
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.word IO_ADDRESS(OMAP2420_32KSYNCT_BASE + 0x010)
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ENTRY(omap242x_sram_ddr_init_sz)
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.word . - omap242x_sram_ddr_init
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@ -224,7 +224,7 @@ omap242x_srs_prcm_voltctrl:
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ddr_prcm_mask_val:
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.word 0xFFFF3FFC
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omap242x_srs_timer_32ksynct:
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.word IO_ADDRESS(OMAP2_32KSYNCT_BASE + 0x010)
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.word IO_ADDRESS(OMAP2420_32KSYNCT_BASE + 0x010)
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ENTRY(omap242x_sram_reprogram_sdrc_sz)
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.word . - omap242x_sram_reprogram_sdrc
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@ -128,7 +128,7 @@ omap243x_sdi_prcm_voltctrl:
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prcm_mask_val:
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.word 0xFFFF3FFC
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omap243x_sdi_timer_32ksynct_cr:
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.word IO_ADDRESS(OMAP2_32KSYNCT_BASE + 0x010)
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.word IO_ADDRESS(OMAP2430_32KSYNCT_BASE + 0x010)
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ENTRY(omap243x_sram_ddr_init_sz)
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.word . - omap243x_sram_ddr_init
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@ -224,7 +224,7 @@ omap243x_srs_prcm_voltctrl:
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ddr_prcm_mask_val:
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.word 0xFFFF3FFC
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omap243x_srs_timer_32ksynct:
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.word IO_ADDRESS(OMAP2_32KSYNCT_BASE + 0x010)
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.word IO_ADDRESS(OMAP2430_32KSYNCT_BASE + 0x010)
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ENTRY(omap243x_sram_reprogram_sdrc_sz)
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.word . - omap243x_sram_reprogram_sdrc
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@ -175,25 +175,61 @@ console_initcall(omap_add_serial_console);
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* but systems won't necessarily want to spend resources that way.
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*/
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#if defined(CONFIG_ARCH_OMAP16XX)
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#define TIMER_32K_SYNCHRONIZED 0xfffbc410
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#elif defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
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#define TIMER_32K_SYNCHRONIZED (OMAP2_32KSYNCT_BASE + 0x10)
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#endif
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#define OMAP16XX_TIMER_32K_SYNCHRONIZED 0xfffbc410
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#ifdef TIMER_32K_SYNCHRONIZED
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#if !(defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP15XX))
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#include <linux/clocksource.h>
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static cycle_t omap_32k_read(struct clocksource *cs)
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#ifdef CONFIG_ARCH_OMAP16XX
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static cycle_t omap16xx_32k_read(struct clocksource *cs)
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{
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return omap_readl(TIMER_32K_SYNCHRONIZED);
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return omap_readl(OMAP16XX_TIMER_32K_SYNCHRONIZED);
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}
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#else
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#define omap16xx_32k_read NULL
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#endif
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#ifdef CONFIG_ARCH_OMAP2420
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static cycle_t omap2420_32k_read(struct clocksource *cs)
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{
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return omap_readl(OMAP2420_32KSYNCT_BASE + 0x10);
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}
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#else
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#define omap2420_32k_read NULL
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#endif
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#ifdef CONFIG_ARCH_OMAP2430
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static cycle_t omap2430_32k_read(struct clocksource *cs)
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{
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return omap_readl(OMAP2430_32KSYNCT_BASE + 0x10);
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}
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#else
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#define omap2430_32k_read NULL
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#endif
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#ifdef CONFIG_ARCH_OMAP34XX
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static cycle_t omap34xx_32k_read(struct clocksource *cs)
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{
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return omap_readl(OMAP3430_32KSYNCT_BASE + 0x10);
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}
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#else
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#define omap34xx_32k_read NULL
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#endif
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/*
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* Kernel assumes that sched_clock can be called early but may not have
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* things ready yet.
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*/
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static cycle_t omap_32k_read_dummy(struct clocksource *cs)
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{
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return 0;
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}
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static struct clocksource clocksource_32k = {
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.name = "32k_counter",
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.rating = 250,
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.read = omap_32k_read,
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.read = omap_32k_read_dummy,
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.mask = CLOCKSOURCE_MASK(32),
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.shift = 10,
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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@ -207,7 +243,7 @@ unsigned long long sched_clock(void)
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{
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unsigned long long ret;
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ret = (unsigned long long)omap_32k_read(&clocksource_32k);
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ret = (unsigned long long)clocksource_32k.read(&clocksource_32k);
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ret = (ret * clocksource_32k.mult_orig) >> clocksource_32k.shift;
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return ret;
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}
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@ -220,6 +256,17 @@ static int __init omap_init_clocksource_32k(void)
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if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
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struct clk *sync_32k_ick;
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if (cpu_is_omap16xx())
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clocksource_32k.read = omap16xx_32k_read;
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else if (cpu_is_omap2420())
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clocksource_32k.read = omap2420_32k_read;
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else if (cpu_is_omap2430())
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clocksource_32k.read = omap2430_32k_read;
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else if (cpu_is_omap34xx())
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clocksource_32k.read = omap34xx_32k_read;
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else
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return -ENODEV;
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sync_32k_ick = clk_get(NULL, "omap_32ksync_ick");
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if (sync_32k_ick)
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clk_enable(sync_32k_ick);
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@ -234,7 +281,7 @@ static int __init omap_init_clocksource_32k(void)
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}
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arch_initcall(omap_init_clocksource_32k);
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#endif /* TIMER_32K_SYNCHRONIZED */
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#endif /* !(defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP15XX)) */
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/* Global address base setup code */
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@ -87,7 +87,6 @@
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#if defined(CONFIG_ARCH_OMAP2420)
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#define OMAP2_32KSYNCT_BASE OMAP2420_32KSYNCT_BASE
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#define OMAP2_PRCM_BASE OMAP2420_PRCM_BASE
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#define OMAP2_CM_BASE OMAP2420_CM_BASE
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#define OMAP2_PRM_BASE OMAP2420_PRM_BASE
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@ -95,7 +94,6 @@
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#elif defined(CONFIG_ARCH_OMAP2430)
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#define OMAP2_32KSYNCT_BASE OMAP2430_32KSYNCT_BASE
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#define OMAP2_PRCM_BASE OMAP2430_PRCM_BASE
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#define OMAP2_CM_BASE OMAP2430_CM_BASE
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#define OMAP2_PRM_BASE OMAP2430_PRM_BASE
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@ -85,7 +85,6 @@
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#if defined(CONFIG_ARCH_OMAP3430)
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#define OMAP2_32KSYNCT_BASE OMAP3430_32KSYNCT_BASE
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#define OMAP2_CM_BASE OMAP3430_CM_BASE
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#define OMAP2_PRM_BASE OMAP3430_PRM_BASE
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#define OMAP2_VA_IC_BASE IO_ADDRESS(OMAP34XX_IC_BASE)
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