Merge branch '3.8/dsi-pll-work'
Merge omapdss patches to enable using DSI PLL for DPI output.
This commit is contained in:
Tomi Valkeinen
commit
a4ae0ba80b
@ -510,6 +510,9 @@ static int __init omap_dss_bus_register(void)
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/* INIT */
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static int (*dss_output_drv_reg_funcs[])(void) __initdata = {
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#ifdef CONFIG_OMAP2_DSS_DSI
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dsi_init_platform_driver,
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#endif
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#ifdef CONFIG_OMAP2_DSS_DPI
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dpi_init_platform_driver,
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#endif
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@ -522,15 +525,15 @@ static int (*dss_output_drv_reg_funcs[])(void) __initdata = {
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#ifdef CONFIG_OMAP2_DSS_VENC
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venc_init_platform_driver,
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#endif
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#ifdef CONFIG_OMAP2_DSS_DSI
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dsi_init_platform_driver,
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#endif
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#ifdef CONFIG_OMAP4_DSS_HDMI
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hdmi_init_platform_driver,
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#endif
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};
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static void (*dss_output_drv_unreg_funcs[])(void) __exitdata = {
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#ifdef CONFIG_OMAP2_DSS_DSI
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dsi_uninit_platform_driver,
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#endif
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#ifdef CONFIG_OMAP2_DSS_DPI
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dpi_uninit_platform_driver,
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#endif
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@ -543,9 +546,6 @@ static void (*dss_output_drv_unreg_funcs[])(void) __exitdata = {
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#ifdef CONFIG_OMAP2_DSS_VENC
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venc_uninit_platform_driver,
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#endif
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#ifdef CONFIG_OMAP2_DSS_DSI
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dsi_uninit_platform_driver,
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#endif
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#ifdef CONFIG_OMAP4_DSS_HDMI
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hdmi_uninit_platform_driver,
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#endif
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@ -49,34 +49,37 @@ static struct {
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struct omap_dss_output output;
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} dpi;
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static struct platform_device *dpi_get_dsidev(enum omap_dss_clk_source clk)
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static struct platform_device *dpi_get_dsidev(enum omap_channel channel)
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{
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int dsi_module;
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dsi_module = clk == OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC ? 0 : 1;
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return dsi_get_dsidev_from_id(dsi_module);
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switch (channel) {
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case OMAP_DSS_CHANNEL_LCD:
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return dsi_get_dsidev_from_id(0);
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case OMAP_DSS_CHANNEL_LCD2:
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return dsi_get_dsidev_from_id(1);
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default:
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return NULL;
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}
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}
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static bool dpi_use_dsi_pll(struct omap_dss_device *dssdev)
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static enum omap_dss_clk_source dpi_get_alt_clk_src(enum omap_channel channel)
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{
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if (dssdev->clocks.dispc.dispc_fclk_src ==
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OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC ||
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dssdev->clocks.dispc.dispc_fclk_src ==
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OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC ||
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dssdev->clocks.dispc.channel.lcd_clk_src ==
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OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC ||
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dssdev->clocks.dispc.channel.lcd_clk_src ==
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OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC)
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return true;
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else
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return false;
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switch (channel) {
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case OMAP_DSS_CHANNEL_LCD:
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return OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC;
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case OMAP_DSS_CHANNEL_LCD2:
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return OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC;
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default:
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/* this shouldn't happen */
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WARN_ON(1);
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return OMAP_DSS_CLK_SRC_FCK;
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}
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}
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static int dpi_set_dsi_clk(struct omap_dss_device *dssdev,
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unsigned long pck_req, unsigned long *fck, int *lck_div,
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int *pck_div)
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{
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struct omap_overlay_manager *mgr = dssdev->output->manager;
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struct dsi_clock_info dsi_cinfo;
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struct dispc_clock_info dispc_cinfo;
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int r;
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@ -90,7 +93,8 @@ static int dpi_set_dsi_clk(struct omap_dss_device *dssdev,
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if (r)
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return r;
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dss_select_dispc_clk_source(dssdev->clocks.dispc.dispc_fclk_src);
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dss_select_lcd_clk_source(mgr->id,
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dpi_get_alt_clk_src(mgr->id));
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dpi.mgr_config.clock_info = dispc_cinfo;
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@ -135,7 +139,7 @@ static int dpi_set_mode(struct omap_dss_device *dssdev)
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unsigned long pck;
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int r = 0;
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if (dpi_use_dsi_pll(dssdev))
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if (dpi.dsidev)
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r = dpi_set_dsi_clk(dssdev, t->pixel_clock * 1000, &fck,
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&lck_div, &pck_div);
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else
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@ -214,7 +218,7 @@ int omapdss_dpi_display_enable(struct omap_dss_device *dssdev)
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if (r)
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goto err_src_sel;
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if (dpi_use_dsi_pll(dssdev)) {
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if (dpi.dsidev) {
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r = dsi_runtime_get(dpi.dsidev);
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if (r)
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goto err_get_dsi;
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@ -242,10 +246,10 @@ int omapdss_dpi_display_enable(struct omap_dss_device *dssdev)
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err_mgr_enable:
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err_set_mode:
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if (dpi_use_dsi_pll(dssdev))
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if (dpi.dsidev)
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dsi_pll_uninit(dpi.dsidev, true);
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err_dsi_pll_init:
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if (dpi_use_dsi_pll(dssdev))
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if (dpi.dsidev)
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dsi_runtime_put(dpi.dsidev);
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err_get_dsi:
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err_src_sel:
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@ -271,8 +275,8 @@ void omapdss_dpi_display_disable(struct omap_dss_device *dssdev)
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dss_mgr_disable(mgr);
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if (dpi_use_dsi_pll(dssdev)) {
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dss_select_dispc_clk_source(OMAP_DSS_CLK_SRC_FCK);
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if (dpi.dsidev) {
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dss_select_lcd_clk_source(mgr->id, OMAP_DSS_CLK_SRC_FCK);
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dsi_pll_uninit(dpi.dsidev, true);
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dsi_runtime_put(dpi.dsidev);
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}
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@ -317,7 +321,7 @@ int dpi_check_timings(struct omap_dss_device *dssdev,
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if (timings->pixel_clock == 0)
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return -EINVAL;
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if (dpi_use_dsi_pll(dssdev)) {
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if (dpi.dsidev) {
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struct dsi_clock_info dsi_cinfo;
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r = dsi_pll_calc_clock_div_pck(dpi.dsidev,
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timings->pixel_clock * 1000,
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@ -359,8 +363,32 @@ void omapdss_dpi_set_data_lines(struct omap_dss_device *dssdev, int data_lines)
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}
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EXPORT_SYMBOL(omapdss_dpi_set_data_lines);
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static int __init dpi_verify_dsi_pll(struct platform_device *dsidev)
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{
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int r;
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/* do initial setup with the PLL to see if it is operational */
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r = dsi_runtime_get(dsidev);
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if (r)
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return r;
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r = dsi_pll_init(dsidev, 0, 1);
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if (r) {
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dsi_runtime_put(dsidev);
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return r;
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}
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dsi_pll_uninit(dsidev, true);
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dsi_runtime_put(dsidev);
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return 0;
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}
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static int __init dpi_init_display(struct omap_dss_device *dssdev)
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{
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struct platform_device *dsidev;
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DSSDBG("init_display\n");
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if (dss_has_feature(FEAT_DPI_USES_VDDS_DSI) &&
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@ -377,12 +405,23 @@ static int __init dpi_init_display(struct omap_dss_device *dssdev)
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dpi.vdds_dsi_reg = vdds_dsi;
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}
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if (dpi_use_dsi_pll(dssdev)) {
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enum omap_dss_clk_source dispc_fclk_src =
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dssdev->clocks.dispc.dispc_fclk_src;
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dpi.dsidev = dpi_get_dsidev(dispc_fclk_src);
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/*
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* XXX We shouldn't need dssdev->channel for this. The dsi pll clock
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* source for DPI is SoC integration detail, not something that should
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* be configured in the dssdev
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*/
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dsidev = dpi_get_dsidev(dssdev->channel);
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if (dpi_verify_dsi_pll(dsidev)) {
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dsidev = NULL;
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DSSWARN("DSI PLL not operational\n");
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}
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if (dsidev)
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DSSDBG("using DSI PLL for DPI clock\n");
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dpi.dsidev = dsidev;
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return 0;
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}
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@ -1386,6 +1386,11 @@ retry:
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cur.dsi_pll_hsdiv_dispc_clk =
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cur.clkin4ddr / cur.regm_dispc;
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if (cur.regm_dispc > 1 &&
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cur.regm_dispc % 2 != 0 &&
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req_pck >= 1000000)
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continue;
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/* this will narrow down the search a bit,
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* but still give pixclocks below what was
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* requested */
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@ -1736,6 +1741,12 @@ int dsi_pll_init(struct platform_device *dsidev, bool enable_hsclk,
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DSSDBG("PLL init\n");
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/*
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* It seems that on many OMAPs we need to enable both to have a
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* functional HSDivider.
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*/
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enable_hsclk = enable_hsdiv = true;
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if (dsi->vdds_dsi_reg == NULL) {
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struct regulator *vdds_dsi;
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@ -4709,7 +4720,6 @@ static int dsi_display_init_dsi(struct omap_dss_device *dssdev)
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if (r)
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goto err1;
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dss_select_dispc_clk_source(dssdev->clocks.dispc.dispc_fclk_src);
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dss_select_dsi_clk_source(dsi->module_id, dssdev->clocks.dsi.dsi_fclk_src);
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dss_select_lcd_clk_source(mgr->id,
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dssdev->clocks.dispc.channel.lcd_clk_src);
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@ -4744,7 +4754,6 @@ static int dsi_display_init_dsi(struct omap_dss_device *dssdev)
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err3:
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dsi_cio_uninit(dsidev);
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err2:
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dss_select_dispc_clk_source(OMAP_DSS_CLK_SRC_FCK);
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dss_select_dsi_clk_source(dsi->module_id, OMAP_DSS_CLK_SRC_FCK);
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dss_select_lcd_clk_source(mgr->id, OMAP_DSS_CLK_SRC_FCK);
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@ -4771,7 +4780,6 @@ static void dsi_display_uninit_dsi(struct omap_dss_device *dssdev,
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dsi_vc_enable(dsidev, 2, 0);
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dsi_vc_enable(dsidev, 3, 0);
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dss_select_dispc_clk_source(OMAP_DSS_CLK_SRC_FCK);
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dss_select_dsi_clk_source(dsi->module_id, OMAP_DSS_CLK_SRC_FCK);
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dss_select_lcd_clk_source(mgr->id, OMAP_DSS_CLK_SRC_FCK);
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dsi_cio_uninit(dsidev);
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@ -304,7 +304,7 @@ static void dss_dump_regs(struct seq_file *s)
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#undef DUMPREG
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}
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void dss_select_dispc_clk_source(enum omap_dss_clk_source clk_src)
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static void dss_select_dispc_clk_source(enum omap_dss_clk_source clk_src)
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{
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struct platform_device *dsidev;
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int b;
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@ -375,8 +375,10 @@ void dss_select_lcd_clk_source(enum omap_channel channel,
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struct platform_device *dsidev;
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int b, ix, pos;
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if (!dss_has_feature(FEAT_LCD_CLK_SRC))
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if (!dss_has_feature(FEAT_LCD_CLK_SRC)) {
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dss_select_dispc_clk_source(clk_src);
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return;
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}
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switch (clk_src) {
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case OMAP_DSS_CLK_SRC_FCK:
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@ -432,6 +434,29 @@ enum omap_dss_clk_source dss_get_lcd_clk_source(enum omap_channel channel)
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}
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}
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/* calculate clock rates using dividers in cinfo */
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int dss_calc_clock_rates(struct dss_clock_info *cinfo)
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{
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if (dss.dpll4_m4_ck) {
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unsigned long prate;
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if (cinfo->fck_div > dss.feat->fck_div_max ||
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cinfo->fck_div == 0)
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return -EINVAL;
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prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
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cinfo->fck = prate / cinfo->fck_div *
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dss.feat->dss_fck_multiplier;
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} else {
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if (cinfo->fck_div != 0)
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return -EINVAL;
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cinfo->fck = clk_get_rate(dss.dss_clk);
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}
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return 0;
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}
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int dss_set_clock_div(struct dss_clock_info *cinfo)
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{
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if (dss.dpll4_m4_ck) {
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@ -462,6 +487,36 @@ unsigned long dss_get_dpll4_rate(void)
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return 0;
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}
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static int dss_setup_default_clock(void)
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{
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unsigned long max_dss_fck, prate;
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unsigned fck_div;
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struct dss_clock_info dss_cinfo = { 0 };
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int r;
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if (dss.dpll4_m4_ck == NULL)
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return 0;
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max_dss_fck = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK);
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prate = dss_get_dpll4_rate();
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fck_div = DIV_ROUND_UP(prate * dss.feat->dss_fck_multiplier,
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max_dss_fck);
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dss_cinfo.fck_div = fck_div;
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r = dss_calc_clock_rates(&dss_cinfo);
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if (r)
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return r;
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r = dss_set_clock_div(&dss_cinfo);
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if (r)
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return r;
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return 0;
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}
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int dss_calc_clock_div(unsigned long req_pck, struct dss_clock_info *dss_cinfo,
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struct dispc_clock_info *dispc_cinfo)
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{
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@ -869,6 +924,10 @@ static int __init omap_dsshw_probe(struct platform_device *pdev)
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if (r)
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return r;
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r = dss_setup_default_clock();
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if (r)
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goto err_setup_clocks;
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pm_runtime_enable(&pdev->dev);
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r = dss_runtime_get();
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@ -878,6 +937,8 @@ static int __init omap_dsshw_probe(struct platform_device *pdev)
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/* Select DPLL */
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REG_FLD_MOD(DSS_CONTROL, 0, 0, 0);
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dss_select_dispc_clk_source(OMAP_DSS_CLK_SRC_FCK);
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#ifdef CONFIG_OMAP2_DSS_VENC
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REG_FLD_MOD(DSS_CONTROL, 1, 4, 4); /* venc dac demen */
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REG_FLD_MOD(DSS_CONTROL, 1, 3, 3); /* venc clock 4x enable */
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@ -901,6 +962,7 @@ static int __init omap_dsshw_probe(struct platform_device *pdev)
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err_runtime_get:
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pm_runtime_disable(&pdev->dev);
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err_setup_clocks:
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dss_put_clocks();
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return r;
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}
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@ -283,7 +283,6 @@ void dss_sdi_init(int datapairs);
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int dss_sdi_enable(void);
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void dss_sdi_disable(void);
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void dss_select_dispc_clk_source(enum omap_dss_clk_source clk_src);
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void dss_select_dsi_clk_source(int dsi_module,
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enum omap_dss_clk_source clk_src);
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void dss_select_lcd_clk_source(enum omap_channel channel,
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@ -296,6 +295,7 @@ void dss_set_venc_output(enum omap_dss_venc_type type);
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void dss_set_dac_pwrdn_bgz(bool enable);
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unsigned long dss_get_dpll4_rate(void);
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int dss_calc_clock_rates(struct dss_clock_info *cinfo);
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int dss_set_clock_div(struct dss_clock_info *cinfo);
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int dss_calc_clock_div(unsigned long req_pck, struct dss_clock_info *dss_cinfo,
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struct dispc_clock_info *dispc_cinfo);
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@ -528,14 +528,6 @@ static int hdmi_power_on_core(struct omap_dss_device *dssdev)
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/* Make selection of HDMI in DSS */
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dss_select_hdmi_venc_clk_source(DSS_HDMI_M_PCLK);
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/* Select the dispc clock source as PRCM clock, to ensure that it is not
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* DSI PLL source as the clock selected by DSI PLL might not be
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* sufficient for the resolution selected / that can be changed
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* dynamically by user. This can be moved to single location , say
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* Boardfile.
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*/
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dss_select_dispc_clk_source(dssdev->clocks.dispc.dispc_fclk_src);
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return 0;
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err_runtime_get:
|
||||
|
||||
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Reference in New Issue
Block a user