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clk: renesas: r8a779g0: Add watchdog clock

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Add the module clock used by the RCLK Watchdog Timer on the Renesas
R-Car V4H (R8A779G0) SoC.

Extracted from a larger patch in the BSP by Kazuya Mizuguchi.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/a012e4449b976efbeaabebb983fa6cfc1b9329d3.1662714852.git.geert+renesas@glider.be
This commit is contained in:
Geert Uytterhoeven 2022-09-09 11:25:12 +02:00
parent e312ae9207
commit a4f8a6e60c
1 changed files with 1 additions and 0 deletions
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drivers/clk/renesas/r8a779g0-cpg-mssr.c
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@ -154,6 +154,7 @@ static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = {
DEF_MOD("hscif1", 515, R8A779G0_CLK_S0D3_PER),
DEF_MOD("hscif2", 516, R8A779G0_CLK_S0D3_PER),
DEF_MOD("hscif3", 517, R8A779G0_CLK_S0D3_PER),
DEF_MOD("wdt1:wdt0", 907, R8A779G0_CLK_R),
};
/*