thermal: exynos: add exynos*_tmu_set_[trip,hyst]() helpers
Add exynos*_tmu_set_[trip,hyst]() helpers and convert all ->tmu_initialize implementations accordingly. Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Signed-off-by: Eduardo Valentin <edubezval@gmail.com>
This commit is contained in:
Bartlomiej Zolnierkiewicz
Eduardo Valentin
parent
fac36bac4b
commit
a503a10ff3
@ -305,30 +305,6 @@ static void sanitize_temp_error(struct exynos_tmu_data *data, u32 trim_info)
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EXYNOS_TMU_TEMP_MASK;
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}
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static u32 get_th_reg(struct exynos_tmu_data *data, u32 threshold, bool falling)
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{
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struct thermal_zone_device *tz = data->tzd;
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const struct thermal_trip * const trips =
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of_thermal_get_trip_points(tz);
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unsigned long temp;
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int i, ntrips = min_t(int, of_thermal_get_ntrips(tz), data->ntrip);
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for (i = 0; i < ntrips; i++) {
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if (trips[i].type == THERMAL_TRIP_CRITICAL)
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continue;
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temp = trips[i].temperature / MCELSIUS;
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if (falling)
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temp -= (trips[i].hysteresis / MCELSIUS);
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else
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threshold &= ~(0xff << 8 * i);
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threshold |= temp_to_code(data, temp) << 8 * i;
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}
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return threshold;
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}
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static int exynos_tmu_initialize(struct platform_device *pdev)
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{
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struct exynos_tmu_data *data = platform_get_drvdata(pdev);
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@ -411,37 +387,79 @@ static void exynos_tmu_control(struct platform_device *pdev, bool on)
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mutex_unlock(&data->lock);
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}
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static void exynos4210_tmu_set_trip_temp(struct exynos_tmu_data *data,
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int trip, u8 temp)
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{
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const struct thermal_trip * const trips =
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of_thermal_get_trip_points(data->tzd);
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u8 ref, th_code;
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ref = trips[0].temperature / MCELSIUS;
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if (trip == 0) {
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th_code = temp_to_code(data, ref);
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writeb(th_code, data->base + EXYNOS4210_TMU_REG_THRESHOLD_TEMP);
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}
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temp -= ref;
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writeb(temp, data->base + EXYNOS4210_TMU_REG_TRIG_LEVEL0 + trip * 4);
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}
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static void exynos4210_tmu_initialize(struct platform_device *pdev)
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{
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struct exynos_tmu_data *data = platform_get_drvdata(pdev);
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struct thermal_zone_device *tz = data->tzd;
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const struct thermal_trip * const trips =
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of_thermal_get_trip_points(tz);
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int threshold_code, i;
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unsigned long reference, temp;
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unsigned long temp;
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int i;
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sanitize_temp_error(data, readl(data->base + EXYNOS_TMU_REG_TRIMINFO));
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/* Write temperature code for threshold */
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reference = trips[0].temperature / MCELSIUS;
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threshold_code = temp_to_code(data, reference);
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writeb(threshold_code, data->base + EXYNOS4210_TMU_REG_THRESHOLD_TEMP);
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for (i = 0; i < of_thermal_get_ntrips(tz); i++) {
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temp = trips[i].temperature / MCELSIUS;
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writeb(temp - reference, data->base +
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EXYNOS4210_TMU_REG_TRIG_LEVEL0 + i * 4);
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exynos4210_tmu_set_trip_temp(data, i, temp);
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}
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}
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static void exynos4412_tmu_set_trip_temp(struct exynos_tmu_data *data,
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int trip, u8 temp)
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{
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u32 th, con;
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th = readl(data->base + EXYNOS_THD_TEMP_RISE);
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th &= ~(0xff << 8 * trip);
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th |= temp_to_code(data, temp) << 8 * trip;
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writel(th, data->base + EXYNOS_THD_TEMP_RISE);
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if (trip == 3) {
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con = readl(data->base + EXYNOS_TMU_REG_CONTROL);
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con |= (1 << EXYNOS_TMU_THERM_TRIP_EN_SHIFT);
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writel(con, data->base + EXYNOS_TMU_REG_CONTROL);
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}
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}
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static void exynos4412_tmu_set_trip_hyst(struct exynos_tmu_data *data,
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int trip, u8 temp, u8 hyst)
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{
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u32 th;
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th = readl(data->base + EXYNOS_THD_TEMP_FALL);
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th &= ~(0xff << 8 * trip);
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if (hyst)
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th |= temp_to_code(data, temp - hyst) << 8 * trip;
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writel(th, data->base + EXYNOS_THD_TEMP_FALL);
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}
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static void exynos4412_tmu_initialize(struct platform_device *pdev)
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{
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struct exynos_tmu_data *data = platform_get_drvdata(pdev);
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struct thermal_zone_device *tz = data->tzd;
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const struct thermal_trip * const trips =
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of_thermal_get_trip_points(data->tzd);
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unsigned int trim_info, con, ctrl, rising_threshold;
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int threshold_code, i;
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unsigned long crit_temp = 0;
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of_thermal_get_trip_points(tz);
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unsigned long temp, hyst;
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unsigned int trim_info, ctrl;
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int i, ntrips = min_t(int, of_thermal_get_ntrips(tz), data->ntrip);
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if (data->soc == SOC_ARCH_EXYNOS3250 ||
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data->soc == SOC_ARCH_EXYNOS4412 ||
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@ -465,27 +483,53 @@ static void exynos4412_tmu_initialize(struct platform_device *pdev)
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sanitize_temp_error(data, trim_info);
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/* Write temperature code for rising and falling threshold */
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rising_threshold = readl(data->base + EXYNOS_THD_TEMP_RISE);
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rising_threshold = get_th_reg(data, rising_threshold, false);
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writel(rising_threshold, data->base + EXYNOS_THD_TEMP_RISE);
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writel(get_th_reg(data, 0, true), data->base + EXYNOS_THD_TEMP_FALL);
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for (i = 0; i < ntrips; i++) {
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temp = trips[i].temperature / MCELSIUS;
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exynos4412_tmu_set_trip_temp(data, i, temp);
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/* if last threshold limit is also present */
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for (i = 0; i < of_thermal_get_ntrips(data->tzd); i++) {
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if (trips[i].type == THERMAL_TRIP_CRITICAL) {
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crit_temp = trips[i].temperature;
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break;
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}
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hyst = trips[i].hysteresis / MCELSIUS;
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exynos4412_tmu_set_trip_hyst(data, i, temp, hyst);
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}
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}
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static void exynos5433_tmu_set_trip_temp(struct exynos_tmu_data *data,
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int trip, u8 temp)
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{
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unsigned int reg_off, j;
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u32 th;
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if (trip > 3) {
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reg_off = EXYNOS5433_THD_TEMP_RISE7_4;
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j = trip - 4;
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} else {
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reg_off = EXYNOS5433_THD_TEMP_RISE3_0;
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j = trip;
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}
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threshold_code = temp_to_code(data, crit_temp / MCELSIUS);
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/* 1-4 level to be assigned in th0 reg */
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rising_threshold &= ~(0xff << 8 * i);
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rising_threshold |= threshold_code << 8 * i;
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writel(rising_threshold, data->base + EXYNOS_THD_TEMP_RISE);
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con = readl(data->base + EXYNOS_TMU_REG_CONTROL);
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con |= (1 << EXYNOS_TMU_THERM_TRIP_EN_SHIFT);
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writel(con, data->base + EXYNOS_TMU_REG_CONTROL);
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th = readl(data->base + reg_off);
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th &= ~(0xff << j * 8);
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th |= (temp_to_code(data, temp) << j * 8);
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writel(th, data->base + reg_off);
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}
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static void exynos5433_tmu_set_trip_hyst(struct exynos_tmu_data *data,
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int trip, u8 temp, u8 hyst)
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{
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unsigned int reg_off, j;
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u32 th;
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if (trip > 3) {
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reg_off = EXYNOS5433_THD_TEMP_FALL7_4;
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j = trip - 4;
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} else {
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reg_off = EXYNOS5433_THD_TEMP_FALL3_0;
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j = trip;
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}
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th = readl(data->base + reg_off);
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th &= ~(0xff << j * 8);
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th |= (temp_to_code(data, temp - hyst) << j * 8);
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writel(th, data->base + reg_off);
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}
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static void exynos5433_tmu_initialize(struct platform_device *pdev)
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@ -493,9 +537,7 @@ static void exynos5433_tmu_initialize(struct platform_device *pdev)
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struct exynos_tmu_data *data = platform_get_drvdata(pdev);
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struct thermal_zone_device *tz = data->tzd;
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unsigned int trim_info;
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unsigned int rising_threshold = 0, falling_threshold = 0;
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int temp, temp_hist;
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int threshold_code, i, sensor_id, cal_type;
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int sensor_id, cal_type, i, temp, hyst;
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trim_info = readl(data->base + EXYNOS_TMU_REG_TRIMINFO);
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sanitize_temp_error(data, trim_info);
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@ -525,111 +567,67 @@ static void exynos5433_tmu_initialize(struct platform_device *pdev)
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/* Write temperature code for rising and falling threshold */
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for (i = 0; i < of_thermal_get_ntrips(tz); i++) {
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int rising_reg_offset, falling_reg_offset;
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int j = 0;
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switch (i) {
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case 0:
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case 1:
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case 2:
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case 3:
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rising_reg_offset = EXYNOS5433_THD_TEMP_RISE3_0;
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falling_reg_offset = EXYNOS5433_THD_TEMP_FALL3_0;
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j = i;
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break;
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case 4:
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case 5:
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case 6:
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case 7:
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rising_reg_offset = EXYNOS5433_THD_TEMP_RISE7_4;
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falling_reg_offset = EXYNOS5433_THD_TEMP_FALL7_4;
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j = i - 4;
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break;
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default:
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continue;
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}
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/* Write temperature code for rising threshold */
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tz->ops->get_trip_temp(tz, i, &temp);
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temp /= MCELSIUS;
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threshold_code = temp_to_code(data, temp);
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rising_threshold = readl(data->base + rising_reg_offset);
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rising_threshold &= ~(0xff << j * 8);
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rising_threshold |= (threshold_code << j * 8);
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writel(rising_threshold, data->base + rising_reg_offset);
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exynos5433_tmu_set_trip_temp(data, i, temp);
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/* Write temperature code for falling threshold */
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tz->ops->get_trip_hyst(tz, i, &temp_hist);
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temp_hist = temp - (temp_hist / MCELSIUS);
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threshold_code = temp_to_code(data, temp_hist);
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falling_threshold = readl(data->base + falling_reg_offset);
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falling_threshold &= ~(0xff << j * 8);
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falling_threshold |= (threshold_code << j * 8);
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writel(falling_threshold, data->base + falling_reg_offset);
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tz->ops->get_trip_hyst(tz, i, &hyst);
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hyst /= MCELSIUS;
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exynos5433_tmu_set_trip_hyst(data, i, temp, hyst);
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}
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}
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static void exynos7_tmu_set_trip_temp(struct exynos_tmu_data *data,
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int trip, u8 temp)
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{
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unsigned int reg_off, bit_off;
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u32 th;
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reg_off = ((7 - trip) / 2) * 4;
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bit_off = ((8 - trip) % 2);
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th = readl(data->base + EXYNOS7_THD_TEMP_RISE7_6 + reg_off);
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th &= ~(EXYNOS7_TMU_TEMP_MASK << (16 * bit_off));
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th |= temp_to_code(data, temp) << (16 * bit_off);
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writel(th, data->base + EXYNOS7_THD_TEMP_RISE7_6 + reg_off);
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}
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static void exynos7_tmu_set_trip_hyst(struct exynos_tmu_data *data,
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int trip, u8 temp, u8 hyst)
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{
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unsigned int reg_off, bit_off;
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u32 th;
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reg_off = ((7 - trip) / 2) * 4;
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bit_off = ((8 - trip) % 2);
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th = readl(data->base + EXYNOS7_THD_TEMP_FALL7_6 + reg_off);
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th &= ~(EXYNOS7_TMU_TEMP_MASK << (16 * bit_off));
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th |= temp_to_code(data, temp - hyst) << (16 * bit_off);
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writel(th, data->base + EXYNOS7_THD_TEMP_FALL7_6 + reg_off);
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}
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static void exynos7_tmu_initialize(struct platform_device *pdev)
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{
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struct exynos_tmu_data *data = platform_get_drvdata(pdev);
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struct thermal_zone_device *tz = data->tzd;
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unsigned int trim_info;
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unsigned int rising_threshold = 0, falling_threshold = 0;
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int threshold_code, i;
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int temp, temp_hist;
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unsigned int reg_off, bit_off;
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int i, temp, hyst;
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trim_info = readl(data->base + EXYNOS_TMU_REG_TRIMINFO);
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sanitize_temp_error(data, trim_info);
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/* Write temperature code for rising and falling threshold */
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for (i = (of_thermal_get_ntrips(tz) - 1); i >= 0; i--) {
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/*
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* On exynos7 there are 4 rising and 4 falling threshold
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* registers (0x50-0x5c and 0x60-0x6c respectively). Each
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* register holds the value of two threshold levels (at bit
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* offsets 0 and 16). Based on the fact that there are atmost
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* eight possible trigger levels, calculate the register and
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* bit offsets where the threshold levels are to be written.
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*
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* e.g. EXYNOS7_THD_TEMP_RISE7_6 (0x50)
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* [24:16] - Threshold level 7
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* [8:0] - Threshold level 6
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* e.g. EXYNOS7_THD_TEMP_RISE5_4 (0x54)
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* [24:16] - Threshold level 5
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* [8:0] - Threshold level 4
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*
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* and similarly for falling thresholds.
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*
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* Based on the above, calculate the register and bit offsets
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* for rising/falling threshold levels and populate them.
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*/
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reg_off = ((7 - i) / 2) * 4;
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bit_off = ((8 - i) % 2);
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tz->ops->get_trip_temp(tz, i, &temp);
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temp /= MCELSIUS;
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exynos7_tmu_set_trip_temp(data, i, temp);
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tz->ops->get_trip_hyst(tz, i, &temp_hist);
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temp_hist = temp - (temp_hist / MCELSIUS);
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/* Set 9-bit temperature code for rising threshold levels */
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threshold_code = temp_to_code(data, temp);
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rising_threshold = readl(data->base +
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EXYNOS7_THD_TEMP_RISE7_6 + reg_off);
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rising_threshold &= ~(EXYNOS7_TMU_TEMP_MASK << (16 * bit_off));
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rising_threshold |= threshold_code << (16 * bit_off);
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writel(rising_threshold,
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data->base + EXYNOS7_THD_TEMP_RISE7_6 + reg_off);
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/* Set 9-bit temperature code for falling threshold levels */
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threshold_code = temp_to_code(data, temp_hist);
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falling_threshold &= ~(EXYNOS7_TMU_TEMP_MASK << (16 * bit_off));
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falling_threshold |= threshold_code << (16 * bit_off);
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writel(falling_threshold,
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data->base + EXYNOS7_THD_TEMP_FALL7_6 + reg_off);
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tz->ops->get_trip_hyst(tz, i, &hyst);
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hyst /= MCELSIUS;
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exynos7_tmu_set_trip_hyst(data, i, temp, hyst);
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}
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}
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