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ASoC: fsl_sai: implement 1:1 bclk:mclk ratio support

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With higher channel counts, we may need higher clock rates.  Starting
with SAI v3.1 (i.MX8MM), we can bypass the divider and get a 1:1
bclk:mclk ratio. Add the necessary support.

Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Link: https://lore.kernel.org/r/20220302083428.3804687-8-s.hauer@pengutronix.de
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Ahmad Fatoum 2022-03-02 09:34:28 +01:00 committed by Mark Brown
parent 1d4cbdf7bf
commit a50b7926d0
No known key found for this signature in database
GPG Key ID: 24D68B725D5487D0
1 changed files with 15 additions and 2 deletions
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17
sound/soc/fsl/fsl_sai.c
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@ -347,6 +347,7 @@ static int fsl_sai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq)
int adir = tx ? RX : TX; int adir = tx ? RX : TX;
int dir = tx ? TX : RX; int dir = tx ? TX : RX;
u32 id; u32 id;
bool support_1_1_ratio = sai->verid.version >= 0x0301;
/* Don't apply to consumer mode */ /* Don't apply to consumer mode */
if (sai->is_consumer_mode) if (sai->is_consumer_mode)
@ -367,7 +368,11 @@ static int fsl_sai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq)
continue; continue;
ratio = DIV_ROUND_CLOSEST(clk_rate, freq); ratio = DIV_ROUND_CLOSEST(clk_rate, freq);
if (!ratio || ratio > 512 || ratio & 1) if (!ratio || ratio > 512)
continue;
if (ratio == 1 && !support_1_1_ratio)
continue;
else if (ratio & 1)
continue; continue;
diff = abs((long)clk_rate - ratio * freq); diff = abs((long)clk_rate - ratio * freq);
@ -422,7 +427,15 @@ static int fsl_sai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq)
regmap_update_bits(sai->regmap, reg, FSL_SAI_CR2_MSEL_MASK, regmap_update_bits(sai->regmap, reg, FSL_SAI_CR2_MSEL_MASK,
FSL_SAI_CR2_MSEL(sai->mclk_id[tx])); FSL_SAI_CR2_MSEL(sai->mclk_id[tx]));
regmap_update_bits(sai->regmap, reg, FSL_SAI_CR2_DIV_MASK, savediv / 2 - 1);
if (savediv == 1)
regmap_update_bits(sai->regmap, reg,
FSL_SAI_CR2_DIV_MASK | FSL_SAI_CR2_BYP,
FSL_SAI_CR2_BYP);
else
regmap_update_bits(sai->regmap, reg,
FSL_SAI_CR2_DIV_MASK | FSL_SAI_CR2_BYP,
savediv / 2 - 1);
return 0; return 0;
} }