perf vendor events arm64: AmpereOne: Remove unsupported events
Some of the events included in the ampereone/core-imp-def are not supported on AmpereOne, remove them. Signed-off-by: Ilkka Koskinen <ilkka@os.amperecomputing.com> Cc: Adrian Hunter <adrian.hunter@intel.com> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Dave Kleikamp <dave.kleikamp@oracle.com> Cc: Ian Rogers <irogers@google.com> Cc: Ingo Molnar <mingo@redhat.com> Cc: James Clark <james.clark@arm.com> Cc: Jiri Olsa <jolsa@kernel.org> Cc: John Garry <john.g.garry@oracle.com> Cc: Leo Yan <leo.yan@linaro.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Mike Leach <mike.leach@linaro.org> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Will Deacon <will@kernel.org> Cc: linux-arm-kernel@lists.infradead.org Link: https://lore.kernel.org/r/20230803211331.140553-5-ilkka@os.amperecomputing.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
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@ -533,66 +533,6 @@
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"EventName": "MMU_D_OTB_ALLOC",
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"BriefDescription": "L2D OTB allocate"
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},
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{
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"PublicDescription": "DTLB Translation cache hit on S1L2 walk cache entry",
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"EventCode": "0xD801",
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"EventName": "MMU_D_TRANS_CACHE_HIT_S1L2_WALK",
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"BriefDescription": "DTLB Translation cache hit on S1L2 walk cache entry"
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},
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{
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"PublicDescription": "DTLB Translation cache hit on S1L1 walk cache entry",
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"EventCode": "0xD802",
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"EventName": "MMU_D_TRANS_CACHE_HIT_S1L1_WALK",
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"BriefDescription": "DTLB Translation cache hit on S1L1 walk cache entry"
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},
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{
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"PublicDescription": "DTLB Translation cache hit on S1L0 walk cache entry",
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"EventCode": "0xD803",
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"EventName": "MMU_D_TRANS_CACHE_HIT_S1L0_WALK",
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"BriefDescription": "DTLB Translation cache hit on S1L0 walk cache entry"
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},
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{
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"PublicDescription": "DTLB Translation cache hit on S2L2 walk cache entry",
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"EventCode": "0xD804",
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"EventName": "MMU_D_TRANS_CACHE_HIT_S2L2_WALK",
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"BriefDescription": "DTLB Translation cache hit on S2L2 walk cache entry"
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},
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{
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"PublicDescription": "DTLB Translation cache hit on S2L1 walk cache entry",
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"EventCode": "0xD805",
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"EventName": "MMU_D_TRANS_CACHE_HIT_S2L1_WALK",
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"BriefDescription": "DTLB Translation cache hit on S2L1 walk cache entry"
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},
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{
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"PublicDescription": "DTLB Translation cache hit on S2L0 walk cache entry",
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"EventCode": "0xD806",
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"EventName": "MMU_D_TRANS_CACHE_HIT_S2L0_WALK",
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"BriefDescription": "DTLB Translation cache hit on S2L0 walk cache entry"
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},
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{
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"PublicDescription": "D-side S1 Page walk cache lookup",
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"EventCode": "0xD807",
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"EventName": "MMU_D_S1_WALK_CACHE_LOOKUP",
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"BriefDescription": "D-side S1 Page walk cache lookup"
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},
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{
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"PublicDescription": "D-side S1 Page walk cache refill",
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"EventCode": "0xD808",
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"EventName": "MMU_D_S1_WALK_CACHE_REFILL",
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"BriefDescription": "D-side S1 Page walk cache refill"
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},
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{
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"PublicDescription": "D-side S2 Page walk cache lookup",
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"EventCode": "0xD809",
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"EventName": "MMU_D_S2_WALK_CACHE_LOOKUP",
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"BriefDescription": "D-side S2 Page walk cache lookup"
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},
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{
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"PublicDescription": "D-side S2 Page walk cache refill",
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"EventCode": "0xD80A",
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"EventName": "MMU_D_S2_WALK_CACHE_REFILL",
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"BriefDescription": "D-side S2 Page walk cache refill"
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},
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{
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"PublicDescription": "D-side Stage1 tablewalk fault",
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"EventCode": "0xD80B",
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@ -617,66 +557,6 @@
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"EventName": "MMU_I_OTB_ALLOC",
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"BriefDescription": "L2I OTB allocate"
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},
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{
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"PublicDescription": "ITLB Translation cache hit on S1L2 walk cache entry",
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"EventCode": "0xD901",
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"EventName": "MMU_I_TRANS_CACHE_HIT_S1L2_WALK",
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"BriefDescription": "ITLB Translation cache hit on S1L2 walk cache entry"
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},
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{
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"PublicDescription": "ITLB Translation cache hit on S1L1 walk cache entry",
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"EventCode": "0xD902",
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"EventName": "MMU_I_TRANS_CACHE_HIT_S1L1_WALK",
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"BriefDescription": "ITLB Translation cache hit on S1L1 walk cache entry"
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},
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{
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"PublicDescription": "ITLB Translation cache hit on S1L0 walk cache entry",
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"EventCode": "0xD903",
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"EventName": "MMU_I_TRANS_CACHE_HIT_S1L0_WALK",
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"BriefDescription": "ITLB Translation cache hit on S1L0 walk cache entry"
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},
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{
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"PublicDescription": "ITLB Translation cache hit on S2L2 walk cache entry",
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"EventCode": "0xD904",
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"EventName": "MMU_I_TRANS_CACHE_HIT_S2L2_WALK",
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"BriefDescription": "ITLB Translation cache hit on S2L2 walk cache entry"
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},
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{
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"PublicDescription": "ITLB Translation cache hit on S2L1 walk cache entry",
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"EventCode": "0xD905",
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"EventName": "MMU_I_TRANS_CACHE_HIT_S2L1_WALK",
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"BriefDescription": "ITLB Translation cache hit on S2L1 walk cache entry"
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},
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{
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"PublicDescription": "ITLB Translation cache hit on S2L0 walk cache entry",
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"EventCode": "0xD906",
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"EventName": "MMU_I_TRANS_CACHE_HIT_S2L0_WALK",
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"BriefDescription": "ITLB Translation cache hit on S2L0 walk cache entry"
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},
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{
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"PublicDescription": "I-side S1 Page walk cache lookup",
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"EventCode": "0xD907",
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"EventName": "MMU_I_S1_WALK_CACHE_LOOKUP",
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"BriefDescription": "I-side S1 Page walk cache lookup"
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},
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{
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"PublicDescription": "I-side S1 Page walk cache refill",
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"EventCode": "0xD908",
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"EventName": "MMU_I_S1_WALK_CACHE_REFILL",
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"BriefDescription": "I-side S1 Page walk cache refill"
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},
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{
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"PublicDescription": "I-side S2 Page walk cache lookup",
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"EventCode": "0xD909",
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"EventName": "MMU_I_S2_WALK_CACHE_LOOKUP",
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"BriefDescription": "I-side S2 Page walk cache lookup"
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},
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{
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"PublicDescription": "I-side S2 Page walk cache refill",
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"EventCode": "0xD90A",
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"EventName": "MMU_I_S2_WALK_CACHE_REFILL",
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"BriefDescription": "I-side S2 Page walk cache refill"
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},
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{
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"PublicDescription": "I-side Stage1 tablewalk fault",
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"EventCode": "0xD90B",
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