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perf vendor events arm64: AmpereOne: Remove unsupported events

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Some of the events included in the ampereone/core-imp-def are not
supported on AmpereOne, remove them.

Signed-off-by: Ilkka Koskinen <ilkka@os.amperecomputing.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Dave Kleikamp <dave.kleikamp@oracle.com>
Cc: Ian Rogers <irogers@google.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: James Clark <james.clark@arm.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.g.garry@oracle.com>
Cc: Leo Yan <leo.yan@linaro.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Mike Leach <mike.leach@linaro.org>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Will Deacon <will@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org
Link: https://lore.kernel.org/r/20230803211331.140553-5-ilkka@os.amperecomputing.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
This commit is contained in:
Ilkka Koskinen 2023-08-03 14:13:31 -07:00 committed by Arnaldo Carvalho de Melo
parent 705ed54914
commit a50b8db3ea
1 changed files with 0 additions and 120 deletions
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120
tools/perf/pmu-events/arch/arm64/ampere/ampereone/core-imp-def.json
View File

@ -533,66 +533,6 @@
"EventName": "MMU_D_OTB_ALLOC",
"BriefDescription": "L2D OTB allocate"
},
{
"PublicDescription": "DTLB Translation cache hit on S1L2 walk cache entry",
"EventCode": "0xD801",
"EventName": "MMU_D_TRANS_CACHE_HIT_S1L2_WALK",
"BriefDescription": "DTLB Translation cache hit on S1L2 walk cache entry"
},
{
"PublicDescription": "DTLB Translation cache hit on S1L1 walk cache entry",
"EventCode": "0xD802",
"EventName": "MMU_D_TRANS_CACHE_HIT_S1L1_WALK",
"BriefDescription": "DTLB Translation cache hit on S1L1 walk cache entry"
},
{
"PublicDescription": "DTLB Translation cache hit on S1L0 walk cache entry",
"EventCode": "0xD803",
"EventName": "MMU_D_TRANS_CACHE_HIT_S1L0_WALK",
"BriefDescription": "DTLB Translation cache hit on S1L0 walk cache entry"
},
{
"PublicDescription": "DTLB Translation cache hit on S2L2 walk cache entry",
"EventCode": "0xD804",
"EventName": "MMU_D_TRANS_CACHE_HIT_S2L2_WALK",
"BriefDescription": "DTLB Translation cache hit on S2L2 walk cache entry"
},
{
"PublicDescription": "DTLB Translation cache hit on S2L1 walk cache entry",
"EventCode": "0xD805",
"EventName": "MMU_D_TRANS_CACHE_HIT_S2L1_WALK",
"BriefDescription": "DTLB Translation cache hit on S2L1 walk cache entry"
},
{
"PublicDescription": "DTLB Translation cache hit on S2L0 walk cache entry",
"EventCode": "0xD806",
"EventName": "MMU_D_TRANS_CACHE_HIT_S2L0_WALK",
"BriefDescription": "DTLB Translation cache hit on S2L0 walk cache entry"
},
{
"PublicDescription": "D-side S1 Page walk cache lookup",
"EventCode": "0xD807",
"EventName": "MMU_D_S1_WALK_CACHE_LOOKUP",
"BriefDescription": "D-side S1 Page walk cache lookup"
},
{
"PublicDescription": "D-side S1 Page walk cache refill",
"EventCode": "0xD808",
"EventName": "MMU_D_S1_WALK_CACHE_REFILL",
"BriefDescription": "D-side S1 Page walk cache refill"
},
{
"PublicDescription": "D-side S2 Page walk cache lookup",
"EventCode": "0xD809",
"EventName": "MMU_D_S2_WALK_CACHE_LOOKUP",
"BriefDescription": "D-side S2 Page walk cache lookup"
},
{
"PublicDescription": "D-side S2 Page walk cache refill",
"EventCode": "0xD80A",
"EventName": "MMU_D_S2_WALK_CACHE_REFILL",
"BriefDescription": "D-side S2 Page walk cache refill"
},
{
"PublicDescription": "D-side Stage1 tablewalk fault",
"EventCode": "0xD80B",
@ -617,66 +557,6 @@
"EventName": "MMU_I_OTB_ALLOC",
"BriefDescription": "L2I OTB allocate"
},
{
"PublicDescription": "ITLB Translation cache hit on S1L2 walk cache entry",
"EventCode": "0xD901",
"EventName": "MMU_I_TRANS_CACHE_HIT_S1L2_WALK",
"BriefDescription": "ITLB Translation cache hit on S1L2 walk cache entry"
},
{
"PublicDescription": "ITLB Translation cache hit on S1L1 walk cache entry",
"EventCode": "0xD902",
"EventName": "MMU_I_TRANS_CACHE_HIT_S1L1_WALK",
"BriefDescription": "ITLB Translation cache hit on S1L1 walk cache entry"
},
{
"PublicDescription": "ITLB Translation cache hit on S1L0 walk cache entry",
"EventCode": "0xD903",
"EventName": "MMU_I_TRANS_CACHE_HIT_S1L0_WALK",
"BriefDescription": "ITLB Translation cache hit on S1L0 walk cache entry"
},
{
"PublicDescription": "ITLB Translation cache hit on S2L2 walk cache entry",
"EventCode": "0xD904",
"EventName": "MMU_I_TRANS_CACHE_HIT_S2L2_WALK",
"BriefDescription": "ITLB Translation cache hit on S2L2 walk cache entry"
},
{
"PublicDescription": "ITLB Translation cache hit on S2L1 walk cache entry",
"EventCode": "0xD905",
"EventName": "MMU_I_TRANS_CACHE_HIT_S2L1_WALK",
"BriefDescription": "ITLB Translation cache hit on S2L1 walk cache entry"
},
{
"PublicDescription": "ITLB Translation cache hit on S2L0 walk cache entry",
"EventCode": "0xD906",
"EventName": "MMU_I_TRANS_CACHE_HIT_S2L0_WALK",
"BriefDescription": "ITLB Translation cache hit on S2L0 walk cache entry"
},
{
"PublicDescription": "I-side S1 Page walk cache lookup",
"EventCode": "0xD907",
"EventName": "MMU_I_S1_WALK_CACHE_LOOKUP",
"BriefDescription": "I-side S1 Page walk cache lookup"
},
{
"PublicDescription": "I-side S1 Page walk cache refill",
"EventCode": "0xD908",
"EventName": "MMU_I_S1_WALK_CACHE_REFILL",
"BriefDescription": "I-side S1 Page walk cache refill"
},
{
"PublicDescription": "I-side S2 Page walk cache lookup",
"EventCode": "0xD909",
"EventName": "MMU_I_S2_WALK_CACHE_LOOKUP",
"BriefDescription": "I-side S2 Page walk cache lookup"
},
{
"PublicDescription": "I-side S2 Page walk cache refill",
"EventCode": "0xD90A",
"EventName": "MMU_I_S2_WALK_CACHE_REFILL",
"BriefDescription": "I-side S2 Page walk cache refill"
},
{
"PublicDescription": "I-side Stage1 tablewalk fault",
"EventCode": "0xD90B",