dt-bindings: media: mediatek,vcodec: Fix addressing cell sizes
'dma-ranges' in the example is written for cell sizes of 2 cells, but the schema and example specify sizes of 1 cell. As the h/w has a bus address of >32-bits, cell sizes of 2 is correct. Update the schema's '#address-cells' and '#size-cells' to be 2 and adjust the example throughout. There's no error currently because dtc only checks 'dma-ranges' is a correct multiple number of cells (3) and the schema checking is based on bracketing of entries. Signed-off-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220301233501.2110047-1-robh@kernel.org
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@ -72,10 +72,10 @@ properties:
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Describes the physical address space of IOMMU maps to memory.
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"#address-cells":
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const: 1
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const: 2
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"#size-cells":
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const: 1
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const: 2
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ranges: true
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@ -205,61 +205,67 @@ examples:
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#include <dt-bindings/clock/mt8192-clk.h>
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#include <dt-bindings/power/mt8192-power.h>
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video-codec@16000000 {
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compatible = "mediatek,mt8192-vcodec-dec";
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mediatek,scp = <&scp>;
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iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>;
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dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x16000000 0x40000>;
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reg = <0x16000000 0x1000>; /* VDEC_SYS */
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vcodec-lat@10000 {
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compatible = "mediatek,mtk-vcodec-lat";
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reg = <0x10000 0x800>;
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interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH 0>;
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iommus = <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD_EXT>,
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<&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD2_EXT>,
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<&iommu0 M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT>,
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<&iommu0 M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT>,
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<&iommu0 M4U_PORT_L5_VDEC_LAT0_TILE_EXT>,
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<&iommu0 M4U_PORT_L5_VDEC_LAT0_WDMA_EXT>,
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<&iommu0 M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT>,
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<&iommu0 M4U_PORT_L5_VDEC_UFO_ENC_EXT>;
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clocks = <&topckgen CLK_TOP_VDEC_SEL>,
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<&vdecsys_soc CLK_VDEC_SOC_VDEC>,
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<&vdecsys_soc CLK_VDEC_SOC_LAT>,
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<&vdecsys_soc CLK_VDEC_SOC_LARB1>,
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<&topckgen CLK_TOP_MAINPLL_D4>;
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clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top";
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assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
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assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
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power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>;
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};
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bus@16000000 {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0 0x16000000 0x16000000 0 0x40000>;
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vcodec-core@25000 {
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compatible = "mediatek,mtk-vcodec-core";
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reg = <0x25000 0x1000>;
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interrupts = <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH 0>;
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iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>,
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<&iommu0 M4U_PORT_L4_VDEC_UFO_EXT>,
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<&iommu0 M4U_PORT_L4_VDEC_PP_EXT>,
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<&iommu0 M4U_PORT_L4_VDEC_PRED_RD_EXT>,
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<&iommu0 M4U_PORT_L4_VDEC_PRED_WR_EXT>,
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<&iommu0 M4U_PORT_L4_VDEC_PPWRAP_EXT>,
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<&iommu0 M4U_PORT_L4_VDEC_TILE_EXT>,
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<&iommu0 M4U_PORT_L4_VDEC_VLD_EXT>,
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<&iommu0 M4U_PORT_L4_VDEC_VLD2_EXT>,
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<&iommu0 M4U_PORT_L4_VDEC_AVC_MV_EXT>,
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<&iommu0 M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT>;
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clocks = <&topckgen CLK_TOP_VDEC_SEL>,
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<&vdecsys CLK_VDEC_VDEC>,
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<&vdecsys CLK_VDEC_LAT>,
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<&vdecsys CLK_VDEC_LARB1>,
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<&topckgen CLK_TOP_MAINPLL_D4>;
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clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top";
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assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
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assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
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power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>;
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video-codec@16000000 {
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compatible = "mediatek,mt8192-vcodec-dec";
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mediatek,scp = <&scp>;
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iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>;
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dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0 0 0 0x16000000 0 0x40000>;
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reg = <0 0x16000000 0 0x1000>; /* VDEC_SYS */
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vcodec-lat@10000 {
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compatible = "mediatek,mtk-vcodec-lat";
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reg = <0 0x10000 0 0x800>;
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interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH 0>;
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iommus = <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD_EXT>,
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<&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD2_EXT>,
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<&iommu0 M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT>,
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<&iommu0 M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT>,
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<&iommu0 M4U_PORT_L5_VDEC_LAT0_TILE_EXT>,
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<&iommu0 M4U_PORT_L5_VDEC_LAT0_WDMA_EXT>,
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<&iommu0 M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT>,
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<&iommu0 M4U_PORT_L5_VDEC_UFO_ENC_EXT>;
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clocks = <&topckgen CLK_TOP_VDEC_SEL>,
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<&vdecsys_soc CLK_VDEC_SOC_VDEC>,
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<&vdecsys_soc CLK_VDEC_SOC_LAT>,
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<&vdecsys_soc CLK_VDEC_SOC_LARB1>,
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<&topckgen CLK_TOP_MAINPLL_D4>;
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clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top";
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assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
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assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
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power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>;
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};
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vcodec-core@25000 {
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compatible = "mediatek,mtk-vcodec-core";
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reg = <0 0x25000 0 0x1000>;
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interrupts = <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH 0>;
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iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>,
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<&iommu0 M4U_PORT_L4_VDEC_UFO_EXT>,
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<&iommu0 M4U_PORT_L4_VDEC_PP_EXT>,
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<&iommu0 M4U_PORT_L4_VDEC_PRED_RD_EXT>,
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<&iommu0 M4U_PORT_L4_VDEC_PRED_WR_EXT>,
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<&iommu0 M4U_PORT_L4_VDEC_PPWRAP_EXT>,
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<&iommu0 M4U_PORT_L4_VDEC_TILE_EXT>,
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<&iommu0 M4U_PORT_L4_VDEC_VLD_EXT>,
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<&iommu0 M4U_PORT_L4_VDEC_VLD2_EXT>,
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<&iommu0 M4U_PORT_L4_VDEC_AVC_MV_EXT>,
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<&iommu0 M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT>;
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clocks = <&topckgen CLK_TOP_VDEC_SEL>,
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<&vdecsys CLK_VDEC_VDEC>,
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<&vdecsys CLK_VDEC_LAT>,
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<&vdecsys CLK_VDEC_LARB1>,
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<&topckgen CLK_TOP_MAINPLL_D4>;
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clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top";
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assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
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assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
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power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>;
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};
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};
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};
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