From d20747b7df51178db5f5c7a03cbf17a91bdb6f0e Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 16 Mar 2017 15:07:25 +0100 Subject: [PATCH 01/22] ARM: dts: r8a7743: Add reset control properties Add properties to describe the reset topology for on-SoC devices: - Add the "#reset-cells" property to the CPG/MSSR device node, - Add resets and reset-names properties to the various device nodes. This allows to reset SoC devices using the Reset Controller API. Note that all resets added match the corresponding module clocks. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7743.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi index cd908796fb3b..0ddac81742e4 100644 --- a/arch/arm/boot/dts/r8a7743.dtsi +++ b/arch/arm/boot/dts/r8a7743.dtsi @@ -62,6 +62,7 @@ clocks = <&cpg CPG_MOD 408>; clock-names = "clk"; power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 408>; }; irqc: interrupt-controller@e61c0000 { @@ -81,6 +82,7 @@ ; clocks = <&cpg CPG_MOD 407>; power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 407>; }; timer { @@ -102,6 +104,7 @@ clock-names = "extal", "usb_extal"; #clock-cells = <2>; #power-domain-cells = <0>; + #reset-cells = <1>; }; prr: chipid@ff000044 { @@ -148,6 +151,7 @@ clocks = <&cpg CPG_MOD 219>; clock-names = "fck"; power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 219>; #dma-cells = <1>; dma-channels = <15>; }; @@ -180,6 +184,7 @@ clocks = <&cpg CPG_MOD 218>; clock-names = "fck"; power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 218>; #dma-cells = <1>; dma-channels = <15>; }; @@ -195,6 +200,7 @@ <&dmac1 0x21>, <&dmac1 0x22>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 204>; status = "disabled"; }; @@ -209,6 +215,7 @@ <&dmac1 0x25>, <&dmac1 0x26>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 203>; status = "disabled"; }; @@ -223,6 +230,7 @@ <&dmac1 0x27>, <&dmac1 0x28>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 202>; status = "disabled"; }; @@ -237,6 +245,7 @@ <&dmac1 0x1b>, <&dmac1 0x1c>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 1106>; status = "disabled"; }; @@ -251,6 +260,7 @@ <&dmac1 0x1f>, <&dmac1 0x20>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 1107>; status = "disabled"; }; @@ -265,6 +275,7 @@ <&dmac1 0x23>, <&dmac1 0x24>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 1108>; status = "disabled"; }; @@ -279,6 +290,7 @@ <&dmac1 0x3d>, <&dmac1 0x3e>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 206>; status = "disabled"; }; @@ -293,6 +305,7 @@ <&dmac1 0x19>, <&dmac1 0x1a>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 207>; status = "disabled"; }; @@ -307,6 +320,7 @@ <&dmac1 0x1d>, <&dmac1 0x1e>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 216>; status = "disabled"; }; @@ -322,6 +336,7 @@ <&dmac1 0x29>, <&dmac1 0x2a>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 721>; status = "disabled"; }; @@ -337,6 +352,7 @@ <&dmac1 0x2d>, <&dmac1 0x2e>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 720>; status = "disabled"; }; @@ -352,6 +368,7 @@ <&dmac1 0x2b>, <&dmac1 0x2c>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 719>; status = "disabled"; }; @@ -367,6 +384,7 @@ <&dmac1 0x2f>, <&dmac1 0x30>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 718>; status = "disabled"; }; @@ -382,6 +400,7 @@ <&dmac1 0xfb>, <&dmac1 0xfc>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 715>; status = "disabled"; }; @@ -397,6 +416,7 @@ <&dmac1 0xfd>, <&dmac1 0xfe>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 714>; status = "disabled"; }; @@ -412,6 +432,7 @@ <&dmac1 0x39>, <&dmac1 0x3a>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 717>; status = "disabled"; }; @@ -427,6 +448,7 @@ <&dmac1 0x4d>, <&dmac1 0x4e>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 716>; status = "disabled"; }; @@ -442,6 +464,7 @@ <&dmac1 0x3b>, <&dmac1 0x3c>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 713>; status = "disabled"; }; @@ -451,6 +474,7 @@ interrupts = ; clocks = <&cpg CPG_MOD 813>; power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 813>; phy-mode = "rmii"; #address-cells = <1>; #size-cells = <0>; From 1efab6e91e8e789f98a11d6618f0fd66f1c51f98 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 16 Mar 2017 15:07:26 +0100 Subject: [PATCH 02/22] ARM: dts: r8a7745: Add reset control properties Add properties to describe the reset topology for on-SoC devices: - Add the "#reset-cells" property to the CPG/MSSR device node, - Add resets and reset-names properties to the various device nodes. This allows to reset SoC devices using the Reset Controller API. Note that all resets added match the corresponding module clocks. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7745.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi index bca88715fada..2feb0084bb3b 100644 --- a/arch/arm/boot/dts/r8a7745.dtsi +++ b/arch/arm/boot/dts/r8a7745.dtsi @@ -62,6 +62,7 @@ clocks = <&cpg CPG_MOD 408>; clock-names = "clk"; power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 408>; }; irqc: interrupt-controller@e61c0000 { @@ -81,6 +82,7 @@ ; clocks = <&cpg CPG_MOD 407>; power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 407>; }; timer { @@ -102,6 +104,7 @@ clock-names = "extal", "usb_extal"; #clock-cells = <2>; #power-domain-cells = <0>; + #reset-cells = <1>; }; prr: chipid@ff000044 { @@ -148,6 +151,7 @@ clocks = <&cpg CPG_MOD 219>; clock-names = "fck"; power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 219>; #dma-cells = <1>; dma-channels = <15>; }; @@ -180,6 +184,7 @@ clocks = <&cpg CPG_MOD 218>; clock-names = "fck"; power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 218>; #dma-cells = <1>; dma-channels = <15>; }; @@ -195,6 +200,7 @@ <&dmac1 0x21>, <&dmac1 0x22>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 204>; status = "disabled"; }; @@ -209,6 +215,7 @@ <&dmac1 0x25>, <&dmac1 0x26>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 203>; status = "disabled"; }; @@ -223,6 +230,7 @@ <&dmac1 0x27>, <&dmac1 0x28>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 202>; status = "disabled"; }; @@ -237,6 +245,7 @@ <&dmac1 0x1b>, <&dmac1 0x1c>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 1106>; status = "disabled"; }; @@ -251,6 +260,7 @@ <&dmac1 0x1f>, <&dmac1 0x20>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 1107>; status = "disabled"; }; @@ -265,6 +275,7 @@ <&dmac1 0x23>, <&dmac1 0x24>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 1108>; status = "disabled"; }; @@ -279,6 +290,7 @@ <&dmac1 0x3d>, <&dmac1 0x3e>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 206>; status = "disabled"; }; @@ -293,6 +305,7 @@ <&dmac1 0x19>, <&dmac1 0x1a>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 207>; status = "disabled"; }; @@ -307,6 +320,7 @@ <&dmac1 0x1d>, <&dmac1 0x1e>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 216>; status = "disabled"; }; @@ -322,6 +336,7 @@ <&dmac1 0x29>, <&dmac1 0x2a>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 721>; status = "disabled"; }; @@ -337,6 +352,7 @@ <&dmac1 0x2d>, <&dmac1 0x2e>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 720>; status = "disabled"; }; @@ -352,6 +368,7 @@ <&dmac1 0x2b>, <&dmac1 0x2c>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 719>; status = "disabled"; }; @@ -367,6 +384,7 @@ <&dmac1 0x2f>, <&dmac1 0x30>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 718>; status = "disabled"; }; @@ -382,6 +400,7 @@ <&dmac1 0xfb>, <&dmac1 0xfc>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 715>; status = "disabled"; }; @@ -397,6 +416,7 @@ <&dmac1 0xfd>, <&dmac1 0xfe>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 714>; status = "disabled"; }; @@ -412,6 +432,7 @@ <&dmac1 0x39>, <&dmac1 0x3a>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 717>; status = "disabled"; }; @@ -427,6 +448,7 @@ <&dmac1 0x4d>, <&dmac1 0x4e>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 716>; status = "disabled"; }; @@ -442,6 +464,7 @@ <&dmac1 0x3b>, <&dmac1 0x3c>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 713>; status = "disabled"; }; @@ -451,6 +474,7 @@ interrupts = ; clocks = <&cpg CPG_MOD 813>; power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 813>; phy-mode = "rmii"; #address-cells = <1>; #size-cells = <0>; From 3932197c01e4ca7d743d07728656d938f1ae93d5 Mon Sep 17 00:00:00 2001 From: Chris Brandt Date: Thu, 9 Feb 2017 08:38:03 -0500 Subject: [PATCH 03/22] ARM: dts: r7s72100: add power-domains to sdhi Reported-by: Geert Uytterhoeven Signed-off-by: Chris Brandt Fixes: 66474697923c ("ARM: dts: r7s72100: add sdhi to device tree") Acked-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r7s72100.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi index 9b12d73e67dc..9fb2e510958a 100644 --- a/arch/arm/boot/dts/r7s72100.dtsi +++ b/arch/arm/boot/dts/r7s72100.dtsi @@ -501,6 +501,7 @@ clocks = <&mstp12_clks R7S72100_CLK_SDHI00>, <&mstp12_clks R7S72100_CLK_SDHI01>; clock-names = "core", "cd"; + power-domains = <&cpg_clocks>; cap-sd-highspeed; cap-sdio-irq; status = "disabled"; @@ -516,6 +517,7 @@ clocks = <&mstp12_clks R7S72100_CLK_SDHI10>, <&mstp12_clks R7S72100_CLK_SDHI11>; clock-names = "core", "cd"; + power-domains = <&cpg_clocks>; cap-sd-highspeed; cap-sdio-irq; status = "disabled"; From 1764f8081f1524bf629e0744b277db751281ff56 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 28 Mar 2017 12:45:30 +0200 Subject: [PATCH 04/22] ARM: dts: r8a7794: Add DU1 clock to device tree Add the missing module clock for the second channel of the display unit. Signed-off-by: Geert Uytterhoeven Acked-by: Laurent Pinchart Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7794.dtsi | 8 +++++--- include/dt-bindings/clock/r8a7794-clock.h | 1 + 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi index 38bf9ed8e739..f5f8d1c03ef7 100644 --- a/arch/arm/boot/dts/r8a7794.dtsi +++ b/arch/arm/boot/dts/r8a7794.dtsi @@ -1270,19 +1270,21 @@ clocks = <&mp_clk>, <&hp_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, - <&zx_clk>; + <&zx_clk>, <&zx_clk>; #clock-cells = <1>; clock-indices = < R8A7794_CLK_EHCI R8A7794_CLK_HSUSB R8A7794_CLK_HSCIF2 R8A7794_CLK_SCIF5 R8A7794_CLK_SCIF4 R8A7794_CLK_HSCIF1 R8A7794_CLK_HSCIF0 R8A7794_CLK_SCIF3 R8A7794_CLK_SCIF2 R8A7794_CLK_SCIF1 - R8A7794_CLK_SCIF0 R8A7794_CLK_DU0 + R8A7794_CLK_SCIF0 + R8A7794_CLK_DU1 R8A7794_CLK_DU0 >; clock-output-names = "ehci", "hsusb", "hscif2", "scif5", "scif4", "hscif1", "hscif0", - "scif3", "scif2", "scif1", "scif0", "du0"; + "scif3", "scif2", "scif1", "scif0", + "du1", "du0"; }; mstp8_clks: mstp8_clks@e6150990 { compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; diff --git a/include/dt-bindings/clock/r8a7794-clock.h b/include/dt-bindings/clock/r8a7794-clock.h index a26776f7dedd..93e99c3ffc8d 100644 --- a/include/dt-bindings/clock/r8a7794-clock.h +++ b/include/dt-bindings/clock/r8a7794-clock.h @@ -82,6 +82,7 @@ #define R8A7794_CLK_SCIF2 19 #define R8A7794_CLK_SCIF1 20 #define R8A7794_CLK_SCIF0 21 +#define R8A7794_CLK_DU1 23 #define R8A7794_CLK_DU0 24 /* MSTP8 */ From 89675f36c9e17512812b9d14d9824f8ef92782c3 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 28 Mar 2017 12:45:31 +0200 Subject: [PATCH 05/22] ARM: dts: r8a7794: Correct clock of DU1 The second channel of the display unit uses a different module clock than the first channel. Fixes: 46c4f13d04d729fa ("ARM: shmobile: r8a7794: Add DU node to device tree") Signed-off-by: Geert Uytterhoeven Acked-by: Laurent Pinchart Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7794.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi index f5f8d1c03ef7..2f6e94fd408c 100644 --- a/arch/arm/boot/dts/r8a7794.dtsi +++ b/arch/arm/boot/dts/r8a7794.dtsi @@ -925,7 +925,7 @@ interrupts = , ; clocks = <&mstp7_clks R8A7794_CLK_DU0>, - <&mstp7_clks R8A7794_CLK_DU0>; + <&mstp7_clks R8A7794_CLK_DU1>; clock-names = "du.0", "du.1"; status = "disabled"; From 7f698bf60e3a13c991577f5360f371e2a41cf40e Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 28 Mar 2017 12:45:32 +0200 Subject: [PATCH 06/22] ARM: dts: alt: Correct clock of DU1 The second channel of the display unit uses a different module clock than the first channel. Fixes: 876e7fb9f418fd86 ("ARM: shmobile: r8a7794: alt: Enable VGA port") Signed-off-by: Geert Uytterhoeven Acked-by: Laurent Pinchart Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7794-alt.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/r8a7794-alt.dts b/arch/arm/boot/dts/r8a7794-alt.dts index 3fcf76b8e923..f1eea13cdf44 100644 --- a/arch/arm/boot/dts/r8a7794-alt.dts +++ b/arch/arm/boot/dts/r8a7794-alt.dts @@ -168,7 +168,7 @@ status = "okay"; clocks = <&mstp7_clks R8A7794_CLK_DU0>, - <&mstp7_clks R8A7794_CLK_DU0>, + <&mstp7_clks R8A7794_CLK_DU1>, <&x13_clk>, <&x2_clk>; clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1"; From 403fe77e22eb72c962c3889efc9d4fa62e454737 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 28 Mar 2017 12:45:33 +0200 Subject: [PATCH 07/22] ARM: dts: silk: Correct clock of DU1 The second channel of the display unit uses a different module clock than the first channel. Fixes: 84e734f497cd48f6 ("ARM: dts: silk: add DU DT support") Signed-off-by: Geert Uytterhoeven Acked-by: Laurent Pinchart Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7794-silk.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/r8a7794-silk.dts b/arch/arm/boot/dts/r8a7794-silk.dts index c742d80d6dca..4cb5278d104d 100644 --- a/arch/arm/boot/dts/r8a7794-silk.dts +++ b/arch/arm/boot/dts/r8a7794-silk.dts @@ -424,7 +424,7 @@ status = "okay"; clocks = <&mstp7_clks R8A7794_CLK_DU0>, - <&mstp7_clks R8A7794_CLK_DU0>, + <&mstp7_clks R8A7794_CLK_DU1>, <&x2_clk>, <&x3_clk>; clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1"; From 91a7c50cb4fabfba218549dfa84356069918bfbf Mon Sep 17 00:00:00 2001 From: Chris Brandt Date: Thu, 30 Mar 2017 14:16:09 -0700 Subject: [PATCH 08/22] ARM: dts: r7s72100: fix ethernet clock parent Technically, the Ethernet block is run off the 133MHz Bus (B) clock, not the 33MHz Peripheral 0 (P0) clock. Fixes: 969244f9c720 ("ARM: dts: r7s72100: add ethernet clock to device tree") Signed-off-by: Chris Brandt Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r7s72100.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi index 9fb2e510958a..47ef53a4c8bf 100644 --- a/arch/arm/boot/dts/r7s72100.dtsi +++ b/arch/arm/boot/dts/r7s72100.dtsi @@ -121,7 +121,7 @@ #clock-cells = <1>; compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0xfcfe0430 4>; - clocks = <&p0_clk>; + clocks = <&b_clk>; clock-indices = ; clock-output-names = "ether"; }; From d13d4e063d4a08eb1686e890e9183dde709871bf Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 3 Apr 2017 11:45:41 +0200 Subject: [PATCH 09/22] ARM: dts: r8a7790: Correct parent of SSI[0-9] clocks The SSI-ALL gate clock is located in between the P clock and the individual SSI[0-9] clocks, hence the former should be listed as their parent. Fixes: bcde372254386872 ("ARM: shmobile: r8a7790: add MSTP10 support on DTSI") Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7790.dtsi | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index 534525665bb3..fe6b8c2a2d71 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -1443,8 +1443,11 @@ compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>; clocks = <&p_clk>, - <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, - <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, + <&mstp10_clks R8A7790_CLK_SSI_ALL>, <&mstp10_clks R8A7790_CLK_SSI_ALL>, + <&mstp10_clks R8A7790_CLK_SSI_ALL>, <&mstp10_clks R8A7790_CLK_SSI_ALL>, + <&mstp10_clks R8A7790_CLK_SSI_ALL>, <&mstp10_clks R8A7790_CLK_SSI_ALL>, + <&mstp10_clks R8A7790_CLK_SSI_ALL>, <&mstp10_clks R8A7790_CLK_SSI_ALL>, + <&mstp10_clks R8A7790_CLK_SSI_ALL>, <&mstp10_clks R8A7790_CLK_SSI_ALL>, <&p_clk>, <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>, From 16fe68dcab5702a024d85229ff7e98979cb701a5 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 3 Apr 2017 11:45:42 +0200 Subject: [PATCH 10/22] ARM: dts: r8a7791: Correct parent of SSI[0-9] clocks The SSI-ALL gate clock is located in between the P clock and the individual SSI[0-9] clocks, hence the former should be listed as their parent. Fixes: ee9141522dcf13f8 ("ARM: shmobile: r8a7791: add MSTP10 support on DTSI") Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7791.dtsi | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index b319ef4d57b0..a6478ca3f4ca 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -1447,8 +1447,11 @@ compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>; clocks = <&p_clk>, - <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, - <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, + <&mstp10_clks R8A7791_CLK_SSI_ALL>, <&mstp10_clks R8A7791_CLK_SSI_ALL>, + <&mstp10_clks R8A7791_CLK_SSI_ALL>, <&mstp10_clks R8A7791_CLK_SSI_ALL>, + <&mstp10_clks R8A7791_CLK_SSI_ALL>, <&mstp10_clks R8A7791_CLK_SSI_ALL>, + <&mstp10_clks R8A7791_CLK_SSI_ALL>, <&mstp10_clks R8A7791_CLK_SSI_ALL>, + <&mstp10_clks R8A7791_CLK_SSI_ALL>, <&mstp10_clks R8A7791_CLK_SSI_ALL>, <&p_clk>, <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>, From 1cd9028027c7a7c10b774df698c3cfafec6aa67d Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 3 Apr 2017 11:45:43 +0200 Subject: [PATCH 11/22] ARM: dts: r8a7793: Correct parent of SSI[0-9] clocks The SSI-ALL gate clock is located in between the P clock and the individual SSI[0-9] clocks, hence the former should be listed as their parent. Fixes: 072d326542e49187 ("ARM: dts: r8a7793: add MSTP10 clocks to device tree") Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7793.dtsi | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi index 9fcf3a9ca084..4de6041d61f9 100644 --- a/arch/arm/boot/dts/r8a7793.dtsi +++ b/arch/arm/boot/dts/r8a7793.dtsi @@ -1269,8 +1269,11 @@ compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>; clocks = <&p_clk>, - <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, - <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, + <&mstp10_clks R8A7793_CLK_SSI_ALL>, <&mstp10_clks R8A7793_CLK_SSI_ALL>, + <&mstp10_clks R8A7793_CLK_SSI_ALL>, <&mstp10_clks R8A7793_CLK_SSI_ALL>, + <&mstp10_clks R8A7793_CLK_SSI_ALL>, <&mstp10_clks R8A7793_CLK_SSI_ALL>, + <&mstp10_clks R8A7793_CLK_SSI_ALL>, <&mstp10_clks R8A7793_CLK_SSI_ALL>, + <&mstp10_clks R8A7793_CLK_SSI_ALL>, <&mstp10_clks R8A7793_CLK_SSI_ALL>, <&p_clk>, <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>, From 7b39e985cfc18bba43646240b10a830046382abf Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 3 Apr 2017 11:53:08 +0200 Subject: [PATCH 12/22] ARM: dts: r8a7792: Correct Z clock Unlike other R-Car Gen2 SoCs with Cortex-A15 CPU cores, R-Car V2H does not have a programmable Z clock (Cortex-A15 CPU core clock), but uses a fixed divider. This is similar to the Z2 clock (Cortex-A7 CPU core clock) on R-Car E2. Hence: - Remove the Z clock output from the cpg_clocks node, as this implied a programmable clock, - Add the Z clock as a fixed factor clock, - Let the first CPU node point to the new Z clock, - Remove the Z clock index from the bindings (this definition was used by r8a7792.dtsi only, and was not a contract between DT and driver). Fixes: 7c4163aae3d8e5b9 ("ARM: dts: r8a7792: initial SoC device tree") Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7792.dtsi | 11 +++++++++-- include/dt-bindings/clock/r8a7792-clock.h | 1 - 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi index 6c0797ebc08f..0efecb232ee5 100644 --- a/arch/arm/boot/dts/r8a7792.dtsi +++ b/arch/arm/boot/dts/r8a7792.dtsi @@ -46,7 +46,7 @@ compatible = "arm,cortex-a15"; reg = <0>; clock-frequency = <1000000000>; - clocks = <&cpg_clocks R8A7792_CLK_Z>; + clocks = <&z_clk>; power-domains = <&sysc R8A7792_PD_CA15_CPU0>; next-level-cache = <&L2_CA15>; }; @@ -766,7 +766,7 @@ clocks = <&extal_clk>; #clock-cells = <1>; clock-output-names = "main", "pll0", "pll1", "pll3", - "lb", "qspi", "z"; + "lb", "qspi"; #power-domain-cells = <0>; }; @@ -778,6 +778,13 @@ clock-div = <2>; clock-mult = <1>; }; + z_clk: z { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7792_CLK_PLL0>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + }; zx_clk: zx { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7792_CLK_PLL1>; diff --git a/include/dt-bindings/clock/r8a7792-clock.h b/include/dt-bindings/clock/r8a7792-clock.h index 94dd16a1e6e6..5be90bc23bd7 100644 --- a/include/dt-bindings/clock/r8a7792-clock.h +++ b/include/dt-bindings/clock/r8a7792-clock.h @@ -17,7 +17,6 @@ #define R8A7792_CLK_PLL3 3 #define R8A7792_CLK_LB 4 #define R8A7792_CLK_QSPI 5 -#define R8A7792_CLK_Z 6 /* MSTP0 */ #define R8A7792_CLK_MSIOF0 0 From 57ff9d736e05bede56fdb47599fdddb3408d4651 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 3 Apr 2017 11:54:14 +0200 Subject: [PATCH 13/22] ARM: dts: r8a7794: Add Z2 clock Add the Z2 clock (Cortex-A7 CPU core clock), which uses a fixed divider, and link the first CPU node to it. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7794.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi index 2f6e94fd408c..a19b884fb258 100644 --- a/arch/arm/boot/dts/r8a7794.dtsi +++ b/arch/arm/boot/dts/r8a7794.dtsi @@ -43,6 +43,7 @@ compatible = "arm,cortex-a7"; reg = <0>; clock-frequency = <1000000000>; + clocks = <&z2_clk>; power-domains = <&sysc R8A7794_PD_CA7_CPU0>; next-level-cache = <&L2_CA7>; }; @@ -1064,6 +1065,13 @@ clock-div = <2>; clock-mult = <1>; }; + z2_clk: z2 { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7794_CLK_PLL0>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + }; zg_clk: zg { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7794_CLK_PLL1>; From ebf06af55c7594ed1fc18469a5cddf911c40e687 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 3 Apr 2017 11:55:19 +0200 Subject: [PATCH 14/22] ARM: dts: koelsch: Correct clock frequency of X2 DU clock input MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The X2 crystal oscillator on the Koelsch development board provides a 74.25 MHz clock, not a 148.5 MHz clock. Fixes: cd21cb46e14aae3a ("ARM: shmobile: koelsch: Add DU external pixel clocks to DT") Signed-off-by: Geert Uytterhoeven Acked-by: Laurent Pinchart Tested-by: Niklas Söderlund Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7791-koelsch.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts index 59beb8402a36..001e6116c47c 100644 --- a/arch/arm/boot/dts/r8a7791-koelsch.dts +++ b/arch/arm/boot/dts/r8a7791-koelsch.dts @@ -292,7 +292,7 @@ x2_clk: x2-clock { compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency = <148500000>; + clock-frequency = <74250000>; }; x13_clk: x13-clock { From 929ded3dd7ce91d9ef4143d673b4ace2eb9ab355 Mon Sep 17 00:00:00 2001 From: Chris Brandt Date: Wed, 29 Mar 2017 10:30:31 -0700 Subject: [PATCH 15/22] ARM: dts: r7s72100: add rtc clock to device tree Add the realtime clock functional clock source. Signed-off-by: Chris Brandt Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r7s72100.dtsi | 9 +++++++++ include/dt-bindings/clock/r7s72100-clock.h | 3 +++ 2 files changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi index 47ef53a4c8bf..9eace892fec7 100644 --- a/arch/arm/boot/dts/r7s72100.dtsi +++ b/arch/arm/boot/dts/r7s72100.dtsi @@ -117,6 +117,15 @@ clock-output-names = "ostm0", "ostm1"; }; + mstp6_clks: mstp6_clks@fcfe042c { + #clock-cells = <1>; + compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0xfcfe042c 4>; + clocks = <&p0_clk>; + clock-indices = ; + clock-output-names = "rtc"; + }; + mstp7_clks: mstp7_clks@fcfe0430 { #clock-cells = <1>; compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; diff --git a/include/dt-bindings/clock/r7s72100-clock.h b/include/dt-bindings/clock/r7s72100-clock.h index cd2ed5194255..bc256d31099a 100644 --- a/include/dt-bindings/clock/r7s72100-clock.h +++ b/include/dt-bindings/clock/r7s72100-clock.h @@ -29,6 +29,9 @@ #define R7S72100_CLK_OSTM0 1 #define R7S72100_CLK_OSTM1 0 +/* MSTP6 */ +#define R7S72100_CLK_RTC 0 + /* MSTP7 */ #define R7S72100_CLK_ETHER 4 From deddcb891d0d2b4f437dea9bdea4752982c4b133 Mon Sep 17 00:00:00 2001 From: Chris Brandt Date: Wed, 29 Mar 2017 10:30:32 -0700 Subject: [PATCH 16/22] ARM: dts: r7s72100: add RTC_X clock inputs to device tree Add the RTC clocks to device tree. The frequencies must be fixed values according to the hardware manual. Signed-off-by: Chris Brandt Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r7s72100.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi index 9eace892fec7..9db46ac08ba7 100644 --- a/arch/arm/boot/dts/r7s72100.dtsi +++ b/arch/arm/boot/dts/r7s72100.dtsi @@ -51,6 +51,20 @@ clock-frequency = <0>; }; + rtc_x1_clk: rtc_x1 { + #clock-cells = <0>; + compatible = "fixed-clock"; + /* If clk present, value must be set by board to 32678 */ + clock-frequency = <0>; + }; + + rtc_x3_clk: rtc_x3 { + #clock-cells = <0>; + compatible = "fixed-clock"; + /* If clk present, value must be set by board to 4000000 */ + clock-frequency = <0>; + }; + /* Fixed factor clocks */ b_clk: b { #clock-cells = <0>; From 3b5e3f0455442f376f91c69147526535a0389ac3 Mon Sep 17 00:00:00 2001 From: Chris Brandt Date: Wed, 29 Mar 2017 10:30:33 -0700 Subject: [PATCH 17/22] ARM: dts: r7s72100: add rtc to device tree Add the realtime clock device node. Signed-off-by: Chris Brandt Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r7s72100.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi index 9db46ac08ba7..ab9ced453118 100644 --- a/arch/arm/boot/dts/r7s72100.dtsi +++ b/arch/arm/boot/dts/r7s72100.dtsi @@ -563,4 +563,18 @@ power-domains = <&cpg_clocks>; status = "disabled"; }; + + rtc: rtc@fcff1000 { + compatible = "renesas,r7s72100-rtc", "renesas,sh-rtc"; + reg = <0xfcff1000 0x2e>; + interrupts = ; + interrupt-names = "alarm", "period", "carry"; + clocks = <&mstp6_clks R7S72100_CLK_RTC>, <&rtc_x1_clk>, + <&rtc_x3_clk>, <&extal_clk>; + clock-names = "fck", "rtc_x1", "rtc_x3", "extal"; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; }; From f90c36448aacde1fd41332659a12cbc9558b1137 Mon Sep 17 00:00:00 2001 From: Chris Brandt Date: Wed, 29 Mar 2017 10:30:34 -0700 Subject: [PATCH 18/22] ARM: dts: rskrza1: set rtc_x1 clock value Enable the 32.768 kHz RTC_X1 clock by setting the frequency value to non-zero. Signed-off-by: Chris Brandt Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r7s72100-rskrza1.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/r7s72100-rskrza1.dts b/arch/arm/boot/dts/r7s72100-rskrza1.dts index 02b59c5b3c53..cab5857bfb41 100644 --- a/arch/arm/boot/dts/r7s72100-rskrza1.dts +++ b/arch/arm/boot/dts/r7s72100-rskrza1.dts @@ -43,6 +43,10 @@ clock-frequency = <48000000>; }; +&rtc_x1_clk { + clock-frequency = <32768>; +}; + &mtu2 { status = "okay"; }; From 931f3dc3f0d14cc7758aa2d48fc2d713f8c6ebff Mon Sep 17 00:00:00 2001 From: Chris Brandt Date: Wed, 29 Mar 2017 10:30:35 -0700 Subject: [PATCH 19/22] ARM: dts: rskrza1: add rtc DT support Enable the realtime clock. Signed-off-by: Chris Brandt Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r7s72100-rskrza1.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/r7s72100-rskrza1.dts b/arch/arm/boot/dts/r7s72100-rskrza1.dts index cab5857bfb41..72df20a04320 100644 --- a/arch/arm/boot/dts/r7s72100-rskrza1.dts +++ b/arch/arm/boot/dts/r7s72100-rskrza1.dts @@ -73,6 +73,10 @@ status = "okay"; }; +&rtc { + status = "okay"; +}; + &scif2 { status = "okay"; }; From e533a459f07c2b7bcc60121032b3b24d0c58133a Mon Sep 17 00:00:00 2001 From: Jacopo Mondi Date: Mon, 3 Apr 2017 18:03:18 +0200 Subject: [PATCH 20/22] ARM: dts: genmai: Enable rtc and rtc_x1 clock Enable the 32.768 kHz RTC_X1 clock by setting the frequency value to non-zero and enable the realtime clock. Signed-off-by: Jacopo Mondi Signed-off-by: Simon Horman --- arch/arm/boot/dts/r7s72100-genmai.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/r7s72100-genmai.dts b/arch/arm/boot/dts/r7s72100-genmai.dts index 118a8e2b86bd..52a7b586bac7 100644 --- a/arch/arm/boot/dts/r7s72100-genmai.dts +++ b/arch/arm/boot/dts/r7s72100-genmai.dts @@ -44,6 +44,10 @@ clock-frequency = <48000000>; }; +&rtc_x1_clk { + clock-frequency = <32768>; +}; + &mtu2 { status = "okay"; }; @@ -59,6 +63,10 @@ }; }; +&rtc { + status = "okay"; +}; + &scif2 { status = "okay"; }; From 5b476a9610910a6ac5222bee4ae83a8d41800dbd Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 3 Apr 2017 12:08:07 +0200 Subject: [PATCH 21/22] ARM: dts: r8a7790: Drop _clk suffix from external CAN clock node name The current practice is to not add _clk suffixes to clock node names in DT, as these names are used as the actual clock names. Signed-off-by: Geert Uytterhoeven Acked-by: Stephen Boyd Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7790.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index fe6b8c2a2d71..99269aaca6fc 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -1101,7 +1101,7 @@ }; /* External CAN clock */ - can_clk: can_clk { + can_clk: can { compatible = "fixed-clock"; #clock-cells = <0>; /* This value must be overridden by the board. */ From eb77d7260c4c25206e2a455be0dbe6443e0856b5 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 3 Apr 2017 12:08:08 +0200 Subject: [PATCH 22/22] ARM: dts: r8a7791: Drop _clk suffix from external CAN clock node name The current practice is to not add _clk suffixes to clock node names in DT, as these names are used as the actual clock names. Signed-off-by: Geert Uytterhoeven Acked-by: Stephen Boyd Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7791.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index a6478ca3f4ca..4d0c2ce59900 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -1126,7 +1126,7 @@ }; /* External CAN clock */ - can_clk: can_clk { + can_clk: can { compatible = "fixed-clock"; #clock-cells = <0>; /* This value must be overridden by the board. */