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clk: sunxi-ng: a83t: Add max. rate constraint to video PLLs

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It may happen that clock framework finds optimal video PLL rate above
that which is really supported by HW.

User manual doesn't really say what is upper limit for video PLLs on
A83T. Because of that, use the maximum rate defined in BSP clk driver
which is 3 GHz.

Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
This commit is contained in:
Jernej Skrabec 2018-08-09 18:52:17 +02:00 committed by Maxime Ripard
parent a8e5433cdc
commit a528872dbb
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1 changed files with 2 additions and 0 deletions
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drivers/clk/sunxi-ng/ccu-sun8i-a83t.c
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@ -108,6 +108,7 @@ static struct ccu_nkmp pll_video0_clk = {
.n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0), .n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0),
.m = _SUNXI_CCU_DIV(16, 1), /* input divider */ .m = _SUNXI_CCU_DIV(16, 1), /* input divider */
.p = _SUNXI_CCU_DIV(0, 2), /* output divider */ .p = _SUNXI_CCU_DIV(0, 2), /* output divider */
.max_rate = 3000000000UL,
.common = { .common = {
.reg = 0x010, .reg = 0x010,
.lock_reg = CCU_SUN8I_A83T_LOCK_REG, .lock_reg = CCU_SUN8I_A83T_LOCK_REG,
@ -220,6 +221,7 @@ static struct ccu_nkmp pll_video1_clk = {
.n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0), .n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0),
.m = _SUNXI_CCU_DIV(16, 1), /* input divider */ .m = _SUNXI_CCU_DIV(16, 1), /* input divider */
.p = _SUNXI_CCU_DIV(0, 2), /* external divider p */ .p = _SUNXI_CCU_DIV(0, 2), /* external divider p */
.max_rate = 3000000000UL,
.common = { .common = {
.reg = 0x04c, .reg = 0x04c,
.lock_reg = CCU_SUN8I_A83T_LOCK_REG, .lock_reg = CCU_SUN8I_A83T_LOCK_REG,