riscv: dts: sifive: convert isa detection to new properties
Convert the fu540 and fu740 devicetrees to use the new properties "riscv,isa-base" & "riscv,isa-extensions". For compatibility with other projects, "riscv,isa" remains. Reviewed-by: Samuel Holland <samuel.holland@sifive.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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@ -30,6 +30,9 @@
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i-cache-size = <16384>;
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reg = <0>;
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riscv,isa = "rv64imac";
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riscv,isa-base = "rv64i";
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riscv,isa-extensions = "i", "m", "a", "c", "zicntr", "zicsr", "zifencei",
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"zihpm";
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status = "disabled";
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cpu0_intc: interrupt-controller {
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#interrupt-cells = <1>;
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@ -53,6 +56,9 @@
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mmu-type = "riscv,sv39";
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reg = <1>;
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riscv,isa = "rv64imafdc";
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riscv,isa-base = "rv64i";
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riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
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"zifencei", "zihpm";
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tlb-split;
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next-level-cache = <&l2cache>;
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cpu1_intc: interrupt-controller {
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@ -77,6 +83,9 @@
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mmu-type = "riscv,sv39";
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reg = <2>;
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riscv,isa = "rv64imafdc";
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riscv,isa-base = "rv64i";
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riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
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"zifencei", "zihpm";
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tlb-split;
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next-level-cache = <&l2cache>;
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cpu2_intc: interrupt-controller {
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@ -101,6 +110,9 @@
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mmu-type = "riscv,sv39";
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reg = <3>;
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riscv,isa = "rv64imafdc";
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riscv,isa-base = "rv64i";
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riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
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"zifencei", "zihpm";
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tlb-split;
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next-level-cache = <&l2cache>;
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cpu3_intc: interrupt-controller {
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@ -125,6 +137,9 @@
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mmu-type = "riscv,sv39";
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reg = <4>;
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riscv,isa = "rv64imafdc";
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riscv,isa-base = "rv64i";
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riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
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"zifencei", "zihpm";
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tlb-split;
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next-level-cache = <&l2cache>;
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cpu4_intc: interrupt-controller {
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@ -31,6 +31,9 @@
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next-level-cache = <&ccache>;
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reg = <0x0>;
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riscv,isa = "rv64imac";
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riscv,isa-base = "rv64i";
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riscv,isa-extensions = "i", "m", "a", "c", "zicntr", "zicsr", "zifencei",
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"zihpm";
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status = "disabled";
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cpu0_intc: interrupt-controller {
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#interrupt-cells = <1>;
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@ -55,6 +58,9 @@
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next-level-cache = <&ccache>;
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reg = <0x1>;
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riscv,isa = "rv64imafdc";
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riscv,isa-base = "rv64i";
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riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
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"zifencei", "zihpm";
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tlb-split;
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cpu1_intc: interrupt-controller {
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#interrupt-cells = <1>;
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@ -79,6 +85,9 @@
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next-level-cache = <&ccache>;
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reg = <0x2>;
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riscv,isa = "rv64imafdc";
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riscv,isa-base = "rv64i";
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riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
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"zifencei", "zihpm";
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tlb-split;
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cpu2_intc: interrupt-controller {
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#interrupt-cells = <1>;
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@ -103,6 +112,9 @@
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next-level-cache = <&ccache>;
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reg = <0x3>;
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riscv,isa = "rv64imafdc";
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riscv,isa-base = "rv64i";
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riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
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"zifencei", "zihpm";
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tlb-split;
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cpu3_intc: interrupt-controller {
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#interrupt-cells = <1>;
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@ -127,6 +139,9 @@
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next-level-cache = <&ccache>;
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reg = <0x4>;
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riscv,isa = "rv64imafdc";
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riscv,isa-base = "rv64i";
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riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
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"zifencei", "zihpm";
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tlb-split;
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cpu4_intc: interrupt-controller {
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#interrupt-cells = <1>;
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