phy: add the EEE support and the way to access to the MMD registers.
This patch adds the support for the Energy-Efficient Ethernet (EEE)
to the Physical Abstraction Layer.
To support the EEE we have to access to the MMD registers 3.20 and
7.60/61. So two new functions have been added to read/write the MMD
registers (clause 45).
An Ethernet driver (I tested the stmmac) can invoke the phy_init_eee to properly
check if the EEE is supported by the PHYs and it can also set the clock
stop enable bit in the 3.0 register.
The phy_get_eee_err can be used for reporting the number of time where
the PHY failed to complete its normal wake sequence.
In the end, this patch also adds the EEE ethtool support implementing:
o phy_ethtool_set_eee
o phy_ethtool_get_eee
v1: initial patch
v2: fixed some errors especially on naming convention
v3: renamed again the mmd read/write functions thank to Ben's feedback
v4: moved file to phy.c and added the ethtool support.
v5: fixed phy_adv_to_eee, phy_eee_to_supported, phy_eee_to_adv return
values according to ethtool API (thanks to Ben's feedback).
Renamed some macros to avoid too long names.
v6: fixed kernel-doc comments to be properly parsed.
Fixed the phy_init_eee function: we need to check which link mode
was autonegotiated and then the corresponding bits in 7.60 and 7.61
registers.
v7: reviewed the way to get the negotiated settings.
v8: fixed a problem in the phy_init_eee return value erroneously added
when included the phy_read_status call.
v9: do not remove the MDIO_AN_EEE_ADV_100TX and MDIO_AN_EEE_ADV_1000T
and fixed the eee_{cap,lp,adv} declaration as "int" instead of u16.
Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
Reviewed-by: Ben Hutchings <bhutchings@solarflare.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Giuseppe CAVALLARO
David S. Miller
parent
d765955d2a
commit
a59a4d1921
@ -35,6 +35,7 @@
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#include <linux/phy.h>
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#include <linux/timer.h>
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#include <linux/workqueue.h>
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#include <linux/mdio.h>
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#include <linux/atomic.h>
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#include <asm/io.h>
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@ -967,3 +968,283 @@ void phy_state_machine(struct work_struct *work)
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schedule_delayed_work(&phydev->state_queue, PHY_STATE_TIME * HZ);
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}
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static inline void mmd_phy_indirect(struct mii_bus *bus, int prtad, int devad,
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int addr)
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{
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/* Write the desired MMD Devad */
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bus->write(bus, addr, MII_MMD_CTRL, devad);
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/* Write the desired MMD register address */
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bus->write(bus, addr, MII_MMD_DATA, prtad);
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/* Select the Function : DATA with no post increment */
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bus->write(bus, addr, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR));
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}
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/**
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* phy_read_mmd_indirect - reads data from the MMD registers
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* @bus: the target MII bus
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* @prtad: MMD Address
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* @devad: MMD DEVAD
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* @addr: PHY address on the MII bus
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*
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* Description: it reads data from the MMD registers (clause 22 to access to
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* clause 45) of the specified phy address.
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* To read these register we have:
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* 1) Write reg 13 // DEVAD
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* 2) Write reg 14 // MMD Address
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* 3) Write reg 13 // MMD Data Command for MMD DEVAD
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* 3) Read reg 14 // Read MMD data
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*/
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static int phy_read_mmd_indirect(struct mii_bus *bus, int prtad, int devad,
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int addr)
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{
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u32 ret;
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mmd_phy_indirect(bus, prtad, devad, addr);
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/* Read the content of the MMD's selected register */
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ret = bus->read(bus, addr, MII_MMD_DATA);
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return ret;
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}
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/**
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* phy_write_mmd_indirect - writes data to the MMD registers
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* @bus: the target MII bus
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* @prtad: MMD Address
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* @devad: MMD DEVAD
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* @addr: PHY address on the MII bus
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* @data: data to write in the MMD register
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*
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* Description: Write data from the MMD registers of the specified
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* phy address.
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* To write these register we have:
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* 1) Write reg 13 // DEVAD
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* 2) Write reg 14 // MMD Address
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* 3) Write reg 13 // MMD Data Command for MMD DEVAD
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* 3) Write reg 14 // Write MMD data
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*/
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static void phy_write_mmd_indirect(struct mii_bus *bus, int prtad, int devad,
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int addr, u32 data)
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{
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mmd_phy_indirect(bus, prtad, devad, addr);
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/* Write the data into MMD's selected register */
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bus->write(bus, addr, MII_MMD_DATA, data);
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}
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static u32 phy_eee_to_adv(u16 eee_adv)
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{
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u32 adv = 0;
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if (eee_adv & MDIO_EEE_100TX)
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adv |= ADVERTISED_100baseT_Full;
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if (eee_adv & MDIO_EEE_1000T)
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adv |= ADVERTISED_1000baseT_Full;
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if (eee_adv & MDIO_EEE_10GT)
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adv |= ADVERTISED_10000baseT_Full;
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if (eee_adv & MDIO_EEE_1000KX)
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adv |= ADVERTISED_1000baseKX_Full;
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if (eee_adv & MDIO_EEE_10GKX4)
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adv |= ADVERTISED_10000baseKX4_Full;
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if (eee_adv & MDIO_EEE_10GKR)
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adv |= ADVERTISED_10000baseKR_Full;
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return adv;
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}
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static u32 phy_eee_to_supported(u16 eee_caported)
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{
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u32 supported = 0;
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if (eee_caported & MDIO_EEE_100TX)
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supported |= SUPPORTED_100baseT_Full;
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if (eee_caported & MDIO_EEE_1000T)
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supported |= SUPPORTED_1000baseT_Full;
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if (eee_caported & MDIO_EEE_10GT)
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supported |= SUPPORTED_10000baseT_Full;
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if (eee_caported & MDIO_EEE_1000KX)
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supported |= SUPPORTED_1000baseKX_Full;
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if (eee_caported & MDIO_EEE_10GKX4)
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supported |= SUPPORTED_10000baseKX4_Full;
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if (eee_caported & MDIO_EEE_10GKR)
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supported |= SUPPORTED_10000baseKR_Full;
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return supported;
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}
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static u16 phy_adv_to_eee(u32 adv)
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{
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u16 reg = 0;
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if (adv & ADVERTISED_100baseT_Full)
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reg |= MDIO_EEE_100TX;
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if (adv & ADVERTISED_1000baseT_Full)
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reg |= MDIO_EEE_1000T;
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if (adv & ADVERTISED_10000baseT_Full)
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reg |= MDIO_EEE_10GT;
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if (adv & ADVERTISED_1000baseKX_Full)
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reg |= MDIO_EEE_1000KX;
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if (adv & ADVERTISED_10000baseKX4_Full)
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reg |= MDIO_EEE_10GKX4;
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if (adv & ADVERTISED_10000baseKR_Full)
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reg |= MDIO_EEE_10GKR;
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return reg;
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}
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/**
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* phy_init_eee - init and check the EEE feature
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* @phydev: target phy_device struct
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* @clk_stop_enable: PHY may stop the clock during LPI
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*
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* Description: it checks if the Energy-Efficient Ethernet (EEE)
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* is supported by looking at the MMD registers 3.20 and 7.60/61
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* and it programs the MMD register 3.0 setting the "Clock stop enable"
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* bit if required.
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*/
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int phy_init_eee(struct phy_device *phydev, bool clk_stop_enable)
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{
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int ret = -EPROTONOSUPPORT;
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/* According to 802.3az,the EEE is supported only in full duplex-mode.
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* Also EEE feature is active when core is operating with MII, GMII
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* or RGMII.
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*/
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if ((phydev->duplex == DUPLEX_FULL) &&
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((phydev->interface == PHY_INTERFACE_MODE_MII) ||
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(phydev->interface == PHY_INTERFACE_MODE_GMII) ||
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(phydev->interface == PHY_INTERFACE_MODE_RGMII))) {
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int eee_lp, eee_cap, eee_adv;
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u32 lp, cap, adv;
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int idx, status;
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/* Read phy status to properly get the right settings */
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status = phy_read_status(phydev);
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if (status)
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return status;
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/* First check if the EEE ability is supported */
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eee_cap = phy_read_mmd_indirect(phydev->bus, MDIO_PCS_EEE_ABLE,
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MDIO_MMD_PCS, phydev->addr);
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if (eee_cap < 0)
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return eee_cap;
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cap = phy_eee_to_supported(eee_cap);
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if (!cap)
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goto eee_exit;
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/* Check which link settings negotiated and verify it in
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* the EEE advertising registers.
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*/
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eee_lp = phy_read_mmd_indirect(phydev->bus, MDIO_AN_EEE_LPABLE,
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MDIO_MMD_AN, phydev->addr);
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if (eee_lp < 0)
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return eee_lp;
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eee_adv = phy_read_mmd_indirect(phydev->bus, MDIO_AN_EEE_ADV,
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MDIO_MMD_AN, phydev->addr);
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if (eee_adv < 0)
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return eee_adv;
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adv = phy_eee_to_adv(eee_adv);
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lp = phy_eee_to_adv(eee_lp);
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idx = phy_find_setting(phydev->speed, phydev->duplex);
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if ((lp & adv & settings[idx].setting))
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goto eee_exit;
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if (clk_stop_enable) {
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/* Configure the PHY to stop receiving xMII
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* clock while it is signaling LPI.
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*/
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int val = phy_read_mmd_indirect(phydev->bus, MDIO_CTRL1,
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MDIO_MMD_PCS,
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phydev->addr);
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if (val < 0)
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return val;
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val |= MDIO_PCS_CTRL1_CLKSTOP_EN;
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phy_write_mmd_indirect(phydev->bus, MDIO_CTRL1,
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MDIO_MMD_PCS, phydev->addr, val);
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}
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ret = 0; /* EEE supported */
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}
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eee_exit:
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return ret;
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}
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EXPORT_SYMBOL(phy_init_eee);
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/**
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* phy_get_eee_err - report the EEE wake error count
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* @phydev: target phy_device struct
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*
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* Description: it is to report the number of time where the PHY
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* failed to complete its normal wake sequence.
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*/
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int phy_get_eee_err(struct phy_device *phydev)
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{
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return phy_read_mmd_indirect(phydev->bus, MDIO_PCS_EEE_WK_ERR,
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MDIO_MMD_PCS, phydev->addr);
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}
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EXPORT_SYMBOL(phy_get_eee_err);
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/**
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* phy_ethtool_get_eee - get EEE supported and status
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* @phydev: target phy_device struct
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* @data: ethtool_eee data
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*
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* Description: it reportes the Supported/Advertisement/LP Advertisement
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* capabilities.
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*/
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int phy_ethtool_get_eee(struct phy_device *phydev, struct ethtool_eee *data)
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{
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int val;
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/* Get Supported EEE */
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val = phy_read_mmd_indirect(phydev->bus, MDIO_PCS_EEE_ABLE,
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MDIO_MMD_PCS, phydev->addr);
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if (val < 0)
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return val;
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data->supported = phy_eee_to_supported(val);
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/* Get advertisement EEE */
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val = phy_read_mmd_indirect(phydev->bus, MDIO_AN_EEE_ADV,
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MDIO_MMD_AN, phydev->addr);
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if (val < 0)
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return val;
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data->advertised = phy_eee_to_adv(val);
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/* Get LP advertisement EEE */
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val = phy_read_mmd_indirect(phydev->bus, MDIO_AN_EEE_LPABLE,
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MDIO_MMD_AN, phydev->addr);
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if (val < 0)
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return val;
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data->lp_advertised = phy_eee_to_adv(val);
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return 0;
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}
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EXPORT_SYMBOL(phy_ethtool_get_eee);
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/**
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* phy_ethtool_set_eee - set EEE supported and status
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* @phydev: target phy_device struct
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* @data: ethtool_eee data
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*
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* Description: it is to program the Advertisement EEE register.
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*/
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int phy_ethtool_set_eee(struct phy_device *phydev, struct ethtool_eee *data)
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{
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int val;
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val = phy_adv_to_eee(data->advertised);
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phy_write_mmd_indirect(phydev->bus, MDIO_AN_EEE_ADV, MDIO_MMD_AN,
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phydev->addr, val);
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return 0;
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}
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EXPORT_SYMBOL(phy_ethtool_set_eee);
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@ -43,7 +43,11 @@
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#define MDIO_PKGID2 15
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#define MDIO_AN_ADVERTISE 16 /* AN advertising (base page) */
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#define MDIO_AN_LPA 19 /* AN LP abilities (base page) */
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#define MDIO_PCS_EEE_ABLE 20 /* EEE Capability register */
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#define MDIO_PCS_EEE_WK_ERR 22 /* EEE wake error counter */
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#define MDIO_PHYXS_LNSTAT 24 /* PHY XGXS lane state */
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#define MDIO_AN_EEE_ADV 60 /* EEE advertisement */
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#define MDIO_AN_EEE_LPABLE 61 /* EEE link partner ability */
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/* Media-dependent registers. */
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#define MDIO_PMA_10GBT_SWAPPOL 130 /* 10GBASE-T pair swap & polarity */
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@ -56,7 +60,6 @@
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#define MDIO_PCS_10GBRT_STAT2 33 /* 10GBASE-R/-T PCS status 2 */
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#define MDIO_AN_10GBT_CTRL 32 /* 10GBASE-T auto-negotiation control */
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#define MDIO_AN_10GBT_STAT 33 /* 10GBASE-T auto-negotiation status */
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#define MDIO_AN_EEE_ADV 60 /* EEE advertisement */
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/* LASI (Link Alarm Status Interrupt) registers, defined by XENPAK MSA. */
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#define MDIO_PMA_LASI_RXCTRL 0x9000 /* RX_ALARM control */
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@ -82,6 +85,7 @@
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#define MDIO_AN_CTRL1_RESTART BMCR_ANRESTART
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#define MDIO_AN_CTRL1_ENABLE BMCR_ANENABLE
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#define MDIO_AN_CTRL1_XNP 0x2000 /* Enable extended next page */
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#define MDIO_PCS_CTRL1_CLKSTOP_EN 0x400 /* Stop the clock during LPI */
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/* 10 Gb/s */
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#define MDIO_CTRL1_SPEED10G (MDIO_CTRL1_SPEEDSELEXT | 0x00)
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@ -237,9 +241,25 @@
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#define MDIO_AN_10GBT_STAT_MS 0x4000 /* Master/slave config */
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#define MDIO_AN_10GBT_STAT_MSFLT 0x8000 /* Master/slave config fault */
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/* AN EEE Advertisement register. */
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/* EEE Supported/Advertisement/LP Advertisement registers.
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*
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* EEE capability Register (3.20), Advertisement (7.60) and
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* Link partner ability (7.61) registers have and can use the same identical
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* bit masks.
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*/
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#define MDIO_AN_EEE_ADV_100TX 0x0002 /* Advertise 100TX EEE cap */
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#define MDIO_AN_EEE_ADV_1000T 0x0004 /* Advertise 1000T EEE cap */
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/* Note: the two defines above can be potentially used by the user-land
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* and cannot remove them now.
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* So, we define the new generic MDIO_EEE_100TX and MDIO_EEE_1000T macros
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* using the previous ones (that can be considered obsolete).
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*/
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#define MDIO_EEE_100TX MDIO_AN_EEE_ADV_100TX /* 100TX EEE cap */
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#define MDIO_EEE_1000T MDIO_AN_EEE_ADV_1000T /* 1000T EEE cap */
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#define MDIO_EEE_10GT 0x0008 /* 10GT EEE cap */
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#define MDIO_EEE_1000KX 0x0010 /* 1000KX EEE cap */
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#define MDIO_EEE_10GKX4 0x0020 /* 10G KX4 EEE cap */
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#define MDIO_EEE_10GKR 0x0040 /* 10G KR EEE cap */
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/* LASI RX_ALARM control/status registers. */
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#define MDIO_PMA_LASI_RX_PHYXSLFLT 0x0001 /* PHY XS RX local fault */
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@ -21,6 +21,8 @@
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#define MII_EXPANSION 0x06 /* Expansion register */
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#define MII_CTRL1000 0x09 /* 1000BASE-T control */
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#define MII_STAT1000 0x0a /* 1000BASE-T status */
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#define MII_MMD_CTRL 0x0d /* MMD Access Control Register */
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#define MII_MMD_DATA 0x0e /* MMD Access Data Register */
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#define MII_ESTATUS 0x0f /* Extended Status */
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#define MII_DCOUNTER 0x12 /* Disconnect counter */
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#define MII_FCSCOUNTER 0x13 /* False carrier counter */
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@ -141,6 +143,13 @@
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#define FLOW_CTRL_TX 0x01
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#define FLOW_CTRL_RX 0x02
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/* MMD Access Control register fields */
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#define MII_MMD_CTRL_DEVAD_MASK 0x1f /* Mask MMD DEVAD*/
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#define MII_MMD_CTRL_ADDR 0x0000 /* Address */
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#define MII_MMD_CTRL_NOINCR 0x4000 /* no post increment */
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#define MII_MMD_CTRL_INCR_RDWT 0x8000 /* post increment on reads & writes */
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#define MII_MMD_CTRL_INCR_ON_WT 0xC000 /* post increment on writes only */
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/* This structure is used in all SIOCxMIIxxx ioctl calls */
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struct mii_ioctl_data {
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__u16 phy_id;
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@ -554,6 +554,11 @@ int phy_register_fixup_for_uid(u32 phy_uid, u32 phy_uid_mask,
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int (*run)(struct phy_device *));
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int phy_scan_fixups(struct phy_device *phydev);
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int phy_init_eee(struct phy_device *phydev, bool clk_stop_enable);
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int phy_get_eee_err(struct phy_device *phydev);
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int phy_ethtool_set_eee(struct phy_device *phydev, struct ethtool_eee *data);
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int phy_ethtool_get_eee(struct phy_device *phydev, struct ethtool_eee *data);
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int __init mdio_bus_init(void);
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void mdio_bus_exit(void);
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