drm/i915/perf: Determine gen12 oa ctx offset at runtime
Some SKUs of same gen12 platform may have different oactxctrl offsets. For gen12, determine oactxctrl offsets at runtime. v2: (Lionel) - Move MI definitions to intel_gpu_commands.h - Ensure __find_reg_in_lri does read past context image size v3: (Ashutosh) - Drop unnecessary use of double underscores - fix find_reg_in_lri - Return error if oa context offset is U32_MAX - Error out if oa_ctx_ctrl_offset does not find offset v4: (Ashutosh) - Warn on odd MI LRI_LEN - Remove unnecessary check for valid_oactxctrl_offset - Drop valid_oactxctrl_offset macro v5: Drop unrelated comment Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com> Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com> Signed-off-by: John Harrison <John.C.Harrison@Intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20221026222102.5526-5-umesh.nerlige.ramappa@intel.com
This commit is contained in:
Umesh Nerlige Ramappa
John Harrison
parent
2d9da58521
commit
a5c3a3cbf0
@ -187,6 +187,10 @@
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#define MI_BATCH_RESOURCE_STREAMER REG_BIT(10)
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#define MI_BATCH_PREDICATE REG_BIT(15) /* HSW+ on RCS only*/
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#define MI_OPCODE(x) (((x) >> 23) & 0x3f)
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#define IS_MI_LRI_CMD(x) (MI_OPCODE(x) == MI_OPCODE(MI_INSTR(0x22, 0)))
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#define MI_LRI_LEN(x) (((x) & 0xff) + 1)
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/*
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* 3D instructions used by the kernel
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*/
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@ -1356,6 +1356,74 @@ static int gen12_get_render_context_id(struct i915_perf_stream *stream)
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return 0;
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}
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static bool oa_find_reg_in_lri(u32 *state, u32 reg, u32 *offset, u32 end)
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{
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u32 idx = *offset;
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u32 len = min(MI_LRI_LEN(state[idx]) + idx, end);
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bool found = false;
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idx++;
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for (; idx < len; idx += 2) {
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if (state[idx] == reg) {
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found = true;
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break;
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}
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}
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*offset = idx;
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return found;
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}
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static u32 oa_context_image_offset(struct intel_context *ce, u32 reg)
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{
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u32 offset, len = (ce->engine->context_size - PAGE_SIZE) / 4;
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u32 *state = ce->lrc_reg_state;
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for (offset = 0; offset < len; ) {
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if (IS_MI_LRI_CMD(state[offset])) {
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/*
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* We expect reg-value pairs in MI_LRI command, so
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* MI_LRI_LEN() should be even, if not, issue a warning.
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*/
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drm_WARN_ON(&ce->engine->i915->drm,
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MI_LRI_LEN(state[offset]) & 0x1);
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if (oa_find_reg_in_lri(state, reg, &offset, len))
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break;
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} else {
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offset++;
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}
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}
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return offset < len ? offset : U32_MAX;
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}
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static int set_oa_ctx_ctrl_offset(struct intel_context *ce)
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{
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i915_reg_t reg = GEN12_OACTXCONTROL(ce->engine->mmio_base);
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struct i915_perf *perf = &ce->engine->i915->perf;
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u32 offset = perf->ctx_oactxctrl_offset;
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/* Do this only once. Failure is stored as offset of U32_MAX */
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if (offset)
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goto exit;
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offset = oa_context_image_offset(ce, i915_mmio_reg_offset(reg));
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perf->ctx_oactxctrl_offset = offset;
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drm_dbg(&ce->engine->i915->drm,
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"%s oa ctx control at 0x%08x dword offset\n",
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ce->engine->name, offset);
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exit:
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return offset && offset != U32_MAX ? 0 : -ENODEV;
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}
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static bool engine_supports_mi_query(struct intel_engine_cs *engine)
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{
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return engine->class == RENDER_CLASS;
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}
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/**
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* oa_get_render_ctx_id - determine and hold ctx hw id
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* @stream: An i915-perf stream opened for OA metrics
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@ -1375,6 +1443,21 @@ static int oa_get_render_ctx_id(struct i915_perf_stream *stream)
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if (IS_ERR(ce))
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return PTR_ERR(ce);
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if (engine_supports_mi_query(stream->engine)) {
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/*
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* We are enabling perf query here. If we don't find the context
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* offset here, just return an error.
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*/
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ret = set_oa_ctx_ctrl_offset(ce);
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if (ret) {
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intel_context_unpin(ce);
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drm_err(&stream->perf->i915->drm,
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"Enabling perf query failed for %s\n",
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stream->engine->name);
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return ret;
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}
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}
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switch (GRAPHICS_VER(ce->engine->i915)) {
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case 7: {
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/*
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@ -2406,10 +2489,11 @@ static int gen12_configure_oar_context(struct i915_perf_stream *stream,
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int err;
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struct intel_context *ce = stream->pinned_ctx;
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u32 format = stream->oa_buffer.format;
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u32 offset = stream->perf->ctx_oactxctrl_offset;
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struct flex regs_context[] = {
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{
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GEN8_OACTXCONTROL,
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stream->perf->ctx_oactxctrl_offset + 1,
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offset + 1,
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active ? GEN8_OA_COUNTER_RESUME : 0,
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},
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};
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@ -2434,12 +2518,13 @@ static int gen12_configure_oar_context(struct i915_perf_stream *stream,
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},
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};
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/* Modify the context image of pinned context with regs_context*/
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/* Modify the context image of pinned context with regs_context */
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err = intel_context_lock_pinned(ce);
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if (err)
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return err;
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err = gen8_modify_context(ce, regs_context, ARRAY_SIZE(regs_context));
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err = gen8_modify_context(ce, regs_context,
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ARRAY_SIZE(regs_context));
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intel_context_unlock_pinned(ce);
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if (err)
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return err;
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@ -2564,6 +2649,7 @@ lrc_configure_all_contexts(struct i915_perf_stream *stream,
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const struct i915_oa_config *oa_config,
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struct i915_active *active)
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{
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u32 ctx_oactxctrl = stream->perf->ctx_oactxctrl_offset;
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/* The MMIO offsets for Flex EU registers aren't contiguous */
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const u32 ctx_flexeu0 = stream->perf->ctx_flexeu0_offset;
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#define ctx_flexeuN(N) (ctx_flexeu0 + 2 * (N) + 1)
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@ -2574,7 +2660,7 @@ lrc_configure_all_contexts(struct i915_perf_stream *stream,
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},
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{
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GEN8_OACTXCONTROL,
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stream->perf->ctx_oactxctrl_offset + 1,
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ctx_oactxctrl + 1,
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},
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{ EU_PERF_CNTL0, ctx_flexeuN(0) },
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{ EU_PERF_CNTL1, ctx_flexeuN(1) },
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@ -4543,6 +4629,37 @@ static void oa_init_supported_formats(struct i915_perf *perf)
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}
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}
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static void i915_perf_init_info(struct drm_i915_private *i915)
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{
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struct i915_perf *perf = &i915->perf;
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switch (GRAPHICS_VER(i915)) {
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case 8:
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perf->ctx_oactxctrl_offset = 0x120;
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perf->ctx_flexeu0_offset = 0x2ce;
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perf->gen8_valid_ctx_bit = BIT(25);
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break;
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case 9:
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perf->ctx_oactxctrl_offset = 0x128;
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perf->ctx_flexeu0_offset = 0x3de;
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perf->gen8_valid_ctx_bit = BIT(16);
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break;
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case 11:
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perf->ctx_oactxctrl_offset = 0x124;
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perf->ctx_flexeu0_offset = 0x78e;
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perf->gen8_valid_ctx_bit = BIT(16);
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break;
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case 12:
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/*
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* Calculate offset at runtime in oa_pin_context for gen12 and
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* cache the value in perf->ctx_oactxctrl_offset.
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*/
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break;
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default:
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MISSING_CASE(GRAPHICS_VER(i915));
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}
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}
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/**
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* i915_perf_init - initialize i915-perf state on module bind
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* @i915: i915 device instance
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@ -4581,6 +4698,7 @@ void i915_perf_init(struct drm_i915_private *i915)
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* execlist mode by default.
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*/
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perf->ops.read = gen8_oa_read;
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i915_perf_init_info(i915);
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if (IS_GRAPHICS_VER(i915, 8, 9)) {
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perf->ops.is_valid_b_counter_reg =
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@ -4600,18 +4718,6 @@ void i915_perf_init(struct drm_i915_private *i915)
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perf->ops.enable_metric_set = gen8_enable_metric_set;
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perf->ops.disable_metric_set = gen8_disable_metric_set;
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perf->ops.oa_hw_tail_read = gen8_oa_hw_tail_read;
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if (GRAPHICS_VER(i915) == 8) {
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perf->ctx_oactxctrl_offset = 0x120;
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perf->ctx_flexeu0_offset = 0x2ce;
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perf->gen8_valid_ctx_bit = BIT(25);
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} else {
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perf->ctx_oactxctrl_offset = 0x128;
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perf->ctx_flexeu0_offset = 0x3de;
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perf->gen8_valid_ctx_bit = BIT(16);
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}
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} else if (GRAPHICS_VER(i915) == 11) {
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perf->ops.is_valid_b_counter_reg =
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gen7_is_valid_b_counter_addr;
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@ -4625,11 +4731,6 @@ void i915_perf_init(struct drm_i915_private *i915)
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perf->ops.enable_metric_set = gen8_enable_metric_set;
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perf->ops.disable_metric_set = gen11_disable_metric_set;
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perf->ops.oa_hw_tail_read = gen8_oa_hw_tail_read;
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perf->ctx_oactxctrl_offset = 0x124;
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perf->ctx_flexeu0_offset = 0x78e;
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perf->gen8_valid_ctx_bit = BIT(16);
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} else if (GRAPHICS_VER(i915) == 12) {
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perf->ops.is_valid_b_counter_reg =
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gen12_is_valid_b_counter_addr;
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@ -4643,9 +4744,6 @@ void i915_perf_init(struct drm_i915_private *i915)
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perf->ops.enable_metric_set = gen12_enable_metric_set;
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perf->ops.disable_metric_set = gen12_disable_metric_set;
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perf->ops.oa_hw_tail_read = gen12_oa_hw_tail_read;
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perf->ctx_flexeu0_offset = 0;
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perf->ctx_oactxctrl_offset = 0x144;
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}
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}
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@ -97,7 +97,7 @@
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#define GEN12_OAR_OACONTROL_COUNTER_FORMAT_SHIFT 1
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#define GEN12_OAR_OACONTROL_COUNTER_ENABLE (1 << 0)
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#define GEN12_OACTXCONTROL _MMIO(0x2360)
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#define GEN12_OACTXCONTROL(base) _MMIO((base) + 0x360)
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#define GEN12_OAR_OASTATUS _MMIO(0x2968)
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/* Gen12 OAG unit */
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