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Use physical addresses at the interface level, letting drivers remap

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them as appropriate.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Maciej W. Rozycki 2005-07-01 16:10:40 +00:00 committed by Ralf Baechle
parent 7d7ee22121
commit a5fc9c0bbe
18 changed files with 152 additions and 167 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
arch/mips/dec/ecc-berr.c
View File

@ -227,11 +227,11 @@ irqreturn_t dec_ecc_be_interrupt(int irq, void *dev_id, struct pt_regs *regs)
*/
static inline void dec_kn02_be_init(void)
{
volatile u32 *csr = (void *)KN02_CSR_BASE;
volatile u32 *csr = (void *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_CSR);
unsigned long flags;
kn0x_erraddr = (void *)(KN02_SLOT_BASE + KN02_ERRADDR);
kn0x_chksyn = (void *)(KN02_SLOT_BASE + KN02_CHKSYN);
kn0x_erraddr = (void *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_ERRADDR);
kn0x_chksyn = (void *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_CHKSYN);
spin_lock_irqsave(&kn02_lock, flags);
@ -250,11 +250,11 @@ static inline void dec_kn02_be_init(void)
static inline void dec_kn03_be_init(void)
{
volatile u32 *mcr = (void *)(KN03_SLOT_BASE + IOASIC_MCR);
volatile u32 *mbcs = (void *)(KN4K_SLOT_BASE + KN4K_MB_CSR);
volatile u32 *mcr = (void *)CKSEG1ADDR(KN03_SLOT_BASE + IOASIC_MCR);
volatile u32 *mbcs = (void *)CKSEG1ADDR(KN4K_SLOT_BASE + KN4K_MB_CSR);
kn0x_erraddr = (void *)(KN03_SLOT_BASE + IOASIC_ERRADDR);
kn0x_chksyn = (void *)(KN03_SLOT_BASE + IOASIC_CHKSYN);
kn0x_erraddr = (void *)CKSEG1ADDR(KN03_SLOT_BASE + IOASIC_ERRADDR);
kn0x_chksyn = (void *)CKSEG1ADDR(KN03_SLOT_BASE + IOASIC_CHKSYN);
/*
* Set normal ECC detection and generation, enable ECC correction.

22
arch/mips/dec/int-handler.S
View File

@ -2,9 +2,9 @@
* arch/mips/dec/int-handler.S
*
* Copyright (C) 1995, 1996, 1997 Paul M. Antoine and Harald Koerfgen
* Copyright (C) 2000, 2001, 2002, 2003 Maciej W. Rozycki
* Copyright (C) 2000, 2001, 2002, 2003, 2005 Maciej W. Rozycki
*
* Written by Ralf Baechle and Andreas Busse, modified for DECStation
* Written by Ralf Baechle and Andreas Busse, modified for DECstation
* support by Paul Antoine and Harald Koerfgen.
*
* completly rewritten:
@ -14,11 +14,12 @@
* by Maciej W. Rozycki.
*/
#include <linux/config.h>
#include <asm/asm.h>
#include <asm/regdef.h>
#include <asm/mipsregs.h>
#include <asm/stackframe.h>
#include <asm/addrspace.h>
#include <asm/asm.h>
#include <asm/mipsregs.h>
#include <asm/regdef.h>
#include <asm/stackframe.h>
#include <asm/dec/interrupts.h>
#include <asm/dec/ioasic_addrs.h>
@ -28,11 +29,14 @@
#include <asm/dec/kn02xa.h>
#include <asm/dec/kn03.h>
#define KN02_CSR_BASE CKSEG1ADDR(KN02_SLOT_BASE + KN02_CSR)
#define KN02XA_IOASIC_BASE CKSEG1ADDR(KN02XA_SLOT_BASE + IOASIC_IOCTL)
#define KN03_IOASIC_BASE CKSEG1ADDR(KN03_SLOT_BASE + IOASIC_IOCTL)
.text
.set noreorder
/*
* decstation_handle_int: Interrupt handler for DECStations
* decstation_handle_int: Interrupt handler for DECstations
*
* We follow the model in the Indy interrupt code by David Miller, where he
* says: a lot of complication here is taken away because:
@ -48,7 +52,7 @@
* 3) Linux only thinks in terms of all IRQs on or all IRQs
* off, nothing in between like BSD spl() brain-damage.
*
* Furthermore, the IRQs on the DECStations look basically (barring
* Furthermore, the IRQs on the DECstations look basically (barring
* software IRQs which we don't use at all) like...
*
* DS2100/3100's, aka kn01, aka Pmax:
@ -61,7 +65,7 @@
* 3 Lance Ethernet
* 4 DZ11 serial
* 5 RTC
* 6 Memory Controller
* 6 Memory Controller & Video
* 7 FPU
*
* DS5000/200, aka kn02, aka 3max:

9
arch/mips/dec/kn01-berr.c
View File

@ -51,7 +51,7 @@ DEFINE_SPINLOCK(kn01_lock);
static inline void dec_kn01_be_ack(void)
{
volatile u16 *csr = (void *)(KN01_SLOT_BASE + KN01_CSR);
volatile u16 *csr = (void *)CKSEG1ADDR(KN01_SLOT_BASE + KN01_CSR);
unsigned long flags;
spin_lock_irqsave(&kn01_lock, flags);
@ -64,7 +64,8 @@ static inline void dec_kn01_be_ack(void)
static int dec_kn01_be_backend(struct pt_regs *regs, int is_fixup, int invoker)
{
volatile u32 *kn01_erraddr = (void *)(KN01_SLOT_BASE + KN01_ERRADDR);
volatile u32 *kn01_erraddr = (void *)CKSEG1ADDR(KN01_SLOT_BASE +
KN01_ERRADDR);
static const char excstr[] = "exception";
static const char intstr[] = "interrupt";
@ -152,7 +153,7 @@ int dec_kn01_be_handler(struct pt_regs *regs, int is_fixup)
irqreturn_t dec_kn01_be_interrupt(int irq, void *dev_id,
struct pt_regs *regs)
{
volatile u16 *csr = (void *)(KN01_SLOT_BASE + KN01_CSR);
volatile u16 *csr = (void *)CKSEG1ADDR(KN01_SLOT_BASE + KN01_CSR);
int action;
if (!(*csr & KN01_CSR_MEMERR))
@ -178,7 +179,7 @@ irqreturn_t dec_kn01_be_interrupt(int irq, void *dev_id,
void __init dec_kn01_be_init(void)
{
volatile u16 *csr = (void *)(KN01_SLOT_BASE + KN01_CSR);
volatile u16 *csr = (void *)CKSEG1ADDR(KN01_SLOT_BASE + KN01_CSR);
unsigned long flags;
spin_lock_irqsave(&kn01_lock, flags);

9
arch/mips/dec/kn02-irq.c
View File

@ -37,7 +37,8 @@ static int kn02_irq_base;
static inline void unmask_kn02_irq(unsigned int irq)
{
volatile u32 *csr = (volatile u32 *)KN02_CSR_BASE;
volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE +
KN02_CSR);
cached_kn02_csr |= (1 << (irq - kn02_irq_base + 16));
*csr = cached_kn02_csr;
@ -45,7 +46,8 @@ static inline void unmask_kn02_irq(unsigned int irq)
static inline void mask_kn02_irq(unsigned int irq)
{
volatile u32 *csr = (volatile u32 *)KN02_CSR_BASE;
volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE +
KN02_CSR);
cached_kn02_csr &= ~(1 << (irq - kn02_irq_base + 16));
*csr = cached_kn02_csr;
@ -105,7 +107,8 @@ static struct hw_interrupt_type kn02_irq_type = {
void __init init_kn02_irqs(int base)
{
volatile u32 *csr = (volatile u32 *)KN02_CSR_BASE;
volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE +
KN02_CSR);
unsigned long flags;
int i;

11
arch/mips/dec/kn02xa-berr.c
View File

@ -20,6 +20,7 @@
#include <linux/kernel.h>
#include <linux/types.h>
#include <asm/addrspace.h>
#include <asm/system.h>
#include <asm/traps.h>
@ -29,8 +30,8 @@
static inline void dec_kn02xa_be_ack(void)
{
volatile u32 *mer = (void *)KN02XA_MER;
volatile u32 *mem_intr = (void *)KN02XA_MEM_INTR;
volatile u32 *mer = (void *)CKSEG1ADDR(KN02XA_MER);
volatile u32 *mem_intr = (void *)CKSEG1ADDR(KN02XA_MEM_INTR);
*mer = KN02CA_MER_INTR; /* Clear errors; keep the ARC IRQ. */
*mem_intr = 0; /* Any write clears the bus IRQ. */
@ -40,8 +41,8 @@ static inline void dec_kn02xa_be_ack(void)
static int dec_kn02xa_be_backend(struct pt_regs *regs, int is_fixup,
int invoker)
{
volatile u32 *kn02xa_mer = (void *)KN02XA_MER;
volatile u32 *kn02xa_ear = (void *)KN02XA_EAR;
volatile u32 *kn02xa_mer = (void *)CKSEG1ADDR(KN02XA_MER);
volatile u32 *kn02xa_ear = (void *)CKSEG1ADDR(KN02XA_EAR);
static const char excstr[] = "exception";
static const char intstr[] = "interrupt";
@ -126,7 +127,7 @@ irqreturn_t dec_kn02xa_be_interrupt(int irq, void *dev_id,
void __init dec_kn02xa_be_init(void)
{
volatile u32 *mbcs = (void *)(KN4K_SLOT_BASE + KN4K_MB_CSR);
volatile u32 *mbcs = (void *)CKSEG1ADDR(KN4K_SLOT_BASE + KN4K_MB_CSR);
/* For KN04 we need to make sure EE (?) is enabled in the MB. */
if (current_cpu_data.cputype == CPU_R4000SC)

28
arch/mips/dec/prom/identify.c
View File

@ -2,7 +2,7 @@
* identify.c: machine identification code.
*
* Copyright (C) 1998 Harald Koerfgen and Paul M. Antoine
* Copyright (C) 2002, 2003, 2004 Maciej W. Rozycki
* Copyright (C) 2002, 2003, 2004, 2005 Maciej W. Rozycki
*/
#include <linux/init.h>
#include <linux/kernel.h>
@ -12,6 +12,7 @@
#include <linux/types.h>
#include <asm/bootinfo.h>
#include <asm/dec/ioasic.h>
#include <asm/dec/ioasic_addrs.h>
#include <asm/dec/kn01.h>
@ -21,6 +22,7 @@
#include <asm/dec/kn03.h>
#include <asm/dec/kn230.h>
#include <asm/dec/prom.h>
#include <asm/dec/system.h>
#include "dectypes.h"
@ -68,34 +70,44 @@ EXPORT_SYMBOL(dec_rtc_base);
static inline void prom_init_kn01(void)
{
dec_rtc_base = (void *)KN01_RTC_BASE;
dec_kn_slot_base = KN01_SLOT_BASE;
dec_kn_slot_size = KN01_SLOT_SIZE;
dec_rtc_base = (void *)CKSEG1ADDR(dec_kn_slot_base + KN01_RTC);
}
static inline void prom_init_kn230(void)
{
dec_rtc_base = (void *)KN01_RTC_BASE;
dec_kn_slot_base = KN01_SLOT_BASE;
dec_kn_slot_size = KN01_SLOT_SIZE;
dec_rtc_base = (void *)CKSEG1ADDR(dec_kn_slot_base + KN01_RTC);
}
static inline void prom_init_kn02(void)
{
dec_rtc_base = (void *)KN02_RTC_BASE;
dec_kn_slot_base = KN02_SLOT_BASE;
dec_kn_slot_size = KN02_SLOT_SIZE;
dec_rtc_base = (void *)CKSEG1ADDR(dec_kn_slot_base + KN02_RTC);
}
static inline void prom_init_kn02xa(void)
{
ioasic_base = (void *)KN02XA_IOASIC_BASE;
dec_rtc_base = (void *)KN02XA_RTC_BASE;
dec_kn_slot_base = KN02XA_SLOT_BASE;
dec_kn_slot_size = IOASIC_SLOT_SIZE;
ioasic_base = (void *)CKSEG1ADDR(dec_kn_slot_base + IOASIC_IOCTL);
dec_rtc_base = (void *)CKSEG1ADDR(dec_kn_slot_base + IOASIC_TOY);
}
static inline void prom_init_kn03(void)
{
ioasic_base = (void *)KN03_IOASIC_BASE;
dec_rtc_base = (void *)KN03_RTC_BASE;
dec_kn_slot_base = KN03_SLOT_BASE;
dec_kn_slot_size = IOASIC_SLOT_SIZE;
ioasic_base = (void *)CKSEG1ADDR(dec_kn_slot_base + IOASIC_IOCTL);
dec_rtc_base = (void *)CKSEG1ADDR(dec_kn_slot_base + IOASIC_TOY);
}

16
arch/mips/dec/setup.c
View File

@ -39,6 +39,7 @@
#include <asm/dec/kn02ca.h>
#include <asm/dec/kn03.h>
#include <asm/dec/kn230.h>
#include <asm/dec/system.h>
extern void dec_machine_restart(char *command);
@ -48,10 +49,16 @@ extern irqreturn_t dec_intr_halt(int irq, void *dev_id, struct pt_regs *regs);
extern asmlinkage void decstation_handle_int(void);
unsigned long dec_kn_slot_base, dec_kn_slot_size;
EXPORT_SYMBOL(dec_kn_slot_base);
EXPORT_SYMBOL(dec_kn_slot_size);
spinlock_t ioasic_ssr_lock;
volatile u32 *ioasic_base;
unsigned long dec_kn_slot_size;
EXPORT_SYMBOL(ioasic_base);
/*
* IRQ routing and priority tables. Priorites are set as follows:
@ -78,6 +85,9 @@ unsigned long dec_kn_slot_size;
int dec_interrupt[DEC_NR_INTS] = {
[0 ... DEC_NR_INTS - 1] = -1
};
EXPORT_SYMBOL(dec_interrupt);
int_ptr cpu_mask_nr_tbl[DEC_MAX_CPU_INTS][2] = {
{ { .i = ~0 }, { .p = dec_intr_unimplemented } },
};
@ -755,7 +765,3 @@ void __init arch_init_irq(void)
if (dec_interrupt[DEC_IRQ_HALT] >= 0)
setup_irq(dec_interrupt[DEC_IRQ_HALT], &haltirq);
}
EXPORT_SYMBOL(ioasic_base);
EXPORT_SYMBOL(dec_kn_slot_size);
EXPORT_SYMBOL(dec_interrupt);

80
drivers/tc/tc.c
View File

@ -10,31 +10,29 @@
* Copyright (c) Harald Koerfgen, 1998
* Copyright (c) 2001, 2003, 2005 Maciej W. Rozycki
*/
#include <linux/string.h>
#include <linux/init.h>
#include <linux/ioport.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/string.h>
#include <linux/types.h>
#include <asm/addrspace.h>
#include <asm/bug.h>
#include <asm/errno.h>
#include <asm/io.h>
#include <asm/paccess.h>
#include <asm/dec/machtype.h>
#include <asm/dec/prom.h>
#include <asm/dec/tcinfo.h>
#include <asm/dec/tcmodule.h>
#include <asm/dec/interrupts.h>
#include <asm/paccess.h>
#include <asm/ptrace.h>
#define TC_DEBUG
MODULE_LICENSE("GPL");
slot_info tc_bus[MAX_SLOT];
static int num_tcslots;
static tcinfo *info;
unsigned long system_base;
/*
* Interface to the world. Read comment in include/asm-mips/tc.h.
*/
@ -97,13 +95,16 @@ unsigned long get_tc_speed(void)
static void __init tc_probe(unsigned long startaddr, unsigned long size,
int slots)
{
unsigned long slotaddr;
int i, slot, err;
long offset;
unsigned char pattern[4];
unsigned char *module;
u8 pattern[4];
volatile u8 *module;
for (slot = 0; slot < slots; slot++) {
module = (char *)(startaddr + slot * size);
slotaddr = startaddr + slot * size;
module = ioremap_nocache(slotaddr, size);
BUG_ON(!module);
offset = OLDCARD;
@ -112,8 +113,10 @@ static void __init tc_probe(unsigned long startaddr, unsigned long size,
err |= get_dbe(pattern[1], module + OLDCARD + TC_PATTERN1);
err |= get_dbe(pattern[2], module + OLDCARD + TC_PATTERN2);
err |= get_dbe(pattern[3], module + OLDCARD + TC_PATTERN3);
if (err)
if (err) {
iounmap(module);
continue;
}
if (pattern[0] != 0x55 || pattern[1] != 0x00 ||
pattern[2] != 0xaa || pattern[3] != 0xff) {
@ -124,16 +127,20 @@ static void __init tc_probe(unsigned long startaddr, unsigned long size,
err |= get_dbe(pattern[1], module + TC_PATTERN1);
err |= get_dbe(pattern[2], module + TC_PATTERN2);
err |= get_dbe(pattern[3], module + TC_PATTERN3);
if (err)
if (err) {
iounmap(module);
continue;
}
}
if (pattern[0] != 0x55 || pattern[1] != 0x00 ||
pattern[2] != 0xaa || pattern[3] != 0xff)
pattern[2] != 0xaa || pattern[3] != 0xff) {
iounmap(module);
continue;
}
tc_bus[slot].base_addr = (unsigned long)module;
for(i = 0; i < 8; i++) {
tc_bus[slot].base_addr = slotaddr;
for (i = 0; i < 8; i++) {
tc_bus[slot].firmware[i] =
module[TC_FIRM_VER + offset + 4 * i];
tc_bus[slot].vendor[i] =
@ -171,6 +178,8 @@ static void __init tc_probe(unsigned long startaddr, unsigned long size,
tc_bus[slot].interrupt = -1;
break;
}
iounmap(module);
}
}
@ -196,8 +205,8 @@ static int __init tc_init(void)
tc_bus[i].flags = FREE;
}
info = (tcinfo *) rex_gettcinfo();
slot0addr = (unsigned long)CKSEG1ADDR(rex_slot_address(0));
info = rex_gettcinfo();
slot0addr = CPHYSADDR((long)rex_slot_address(0));
switch (mips_machtype) {
case MACH_DS5000_200:
@ -216,35 +225,21 @@ static int __init tc_init(void)
tc_clock = 10000 / info->clk_period;
if (TURBOCHANNEL && info->slot_size && slot0addr) {
printk("TURBOchannel rev. %1d at %2d.%1d MHz ", info->revision,
tc_clock / 10, tc_clock % 10);
printk("(with%s parity)\n", info->parity ? "" : "out");
if (info->slot_size && slot0addr) {
pr_info("TURBOchannel rev. %d at %d.%d MHz (with%s parity)\n",
info->revision, tc_clock / 10, tc_clock % 10,
info->parity ? "" : "out");
slot_size = info->slot_size << 20;
tc_probe(slot0addr, slot_size, num_tcslots);
/*
* All TURBOchannel DECstations have the onboard devices
* where the (num_tcslots + 0 or 1 on DS5k/xx) Option Module
* would be.
*/
if(mips_machtype == MACH_DS5000_XX)
i = 1;
else
i = 0;
system_base = slot0addr + slot_size * (num_tcslots + i);
#ifdef TC_DEBUG
for (i = 0; i < num_tcslots; i++)
if (tc_bus[i].base_addr) {
printk(" slot %d: ", i);
printk("%s %s %s\n", tc_bus[i].vendor,
tc_bus[i].name, tc_bus[i].firmware);
}
#endif
for (i = 0; i < num_tcslots; i++) {
if (!tc_bus[i].base_addr)
continue;
pr_info(" slot %d: %s %s %s\n", i, tc_bus[i].vendor,
tc_bus[i].name, tc_bus[i].firmware);
}
}
return 0;
@ -258,4 +253,3 @@ EXPORT_SYMBOL(release_tc_card);
EXPORT_SYMBOL(get_tc_base_addr);
EXPORT_SYMBOL(get_tc_irq_nr);
EXPORT_SYMBOL(get_tc_speed);
EXPORT_SYMBOL(system_base);

22
drivers/tc/zs.c
View File

@ -65,14 +65,14 @@
#include <asm/system.h>
#include <asm/uaccess.h>
#include <asm/bootinfo.h>
#include <asm/dec/serial.h>
#ifdef CONFIG_MACH_DECSTATION
#include <asm/dec/interrupts.h>
#include <asm/dec/machtype.h>
#include <asm/dec/tc.h>
#include <asm/dec/ioasic_addrs.h>
#endif
#include <asm/dec/machtype.h>
#include <asm/dec/serial.h>
#include <asm/dec/system.h>
#include <asm/dec/tc.h>
#ifdef CONFIG_KGDB
#include <asm/kgdb.h>
#endif
@ -1616,30 +1616,22 @@ static void __init probe_sccs(void)
return;
}
/*
* When serial console is activated, tc_init has not been called yet
* and system_base is undefined. Unfortunately we have to hardcode
* system_base for this case :-(. HK
*/
switch(mips_machtype) {
#ifdef CONFIG_MACH_DECSTATION
case MACH_DS5000_2X0:
case MACH_DS5900:
system_base = CKSEG1ADDR(0x1f800000);
n_chips = 2;
zs_parms = &ds_parms;
zs_parms->irq0 = dec_interrupt[DEC_IRQ_SCC0];
zs_parms->irq1 = dec_interrupt[DEC_IRQ_SCC1];
break;
case MACH_DS5000_1XX:
system_base = CKSEG1ADDR(0x1c000000);
n_chips = 2;
zs_parms = &ds_parms;
zs_parms->irq0 = dec_interrupt[DEC_IRQ_SCC0];
zs_parms->irq1 = dec_interrupt[DEC_IRQ_SCC1];
break;
case MACH_DS5000_XX:
system_base = CKSEG1ADDR(0x1c000000);
n_chips = 1;
zs_parms = &ds_parms;
zs_parms->irq0 = dec_interrupt[DEC_IRQ_SCC0];
@ -1661,10 +1653,10 @@ static void __init probe_sccs(void)
* The sccs reside on the high byte of the 16 bit IOBUS
*/
zs_channels[n_channels].control =
(volatile unsigned char *)system_base +
(volatile void *)CKSEG1ADDR(dec_kn_slot_base +
(0 == chip ? zs_parms->scc0 : zs_parms->scc1) +
(0 == channel ? zs_parms->channel_a_offset :
zs_parms->channel_b_offset);
zs_parms->channel_b_offset));
zs_channels[n_channels].data =
zs_channels[n_channels].control + 4;

3
include/asm-mips/dec/ioasic_addrs.h
View File

@ -45,7 +45,8 @@
/*
* Offsets for I/O ASIC registers (relative to (system_base + IOASIC_IOCTL)).
* Offsets for I/O ASIC registers
* (relative to (dec_kn_slot_base + IOASIC_IOCTL)).
*/
/* all systems */
#define IO_REG_SCSI_DMA_P 0x00 /* SCSI DMA Pointer */

14
include/asm-mips/dec/kn01.h
View File

@ -13,9 +13,7 @@
#ifndef __ASM_MIPS_DEC_KN01_H
#define __ASM_MIPS_DEC_KN01_H
#include <asm/addrspace.h>
#define KN01_SLOT_BASE CKSEG1ADDR(0x10000000)
#define KN01_SLOT_BASE 0x10000000
#define KN01_SLOT_SIZE 0x01000000
/*
@ -40,18 +38,10 @@
#define KN01_SYS_ROM (15*KN01_SLOT_SIZE) /* system board ROM */
/*
* Some port addresses...
*/
#define KN01_LANCE_BASE (KN01_SLOT_BASE + KN01_LANCE) /* 0xB8000000 */
#define KN01_DZ11_BASE (KN01_SLOT_BASE + KN01_DZ11) /* 0xBC000000 */
#define KN01_RTC_BASE (KN01_SLOT_BASE + KN01_RTC) /* 0xBD000000 */
/*
* Frame buffer memory address.
*/
#define KN01_VFB_MEM CKSEG1ADDR(0x0fc00000)
#define KN01_VFB_MEM 0x0fc00000
/*
* CPU interrupt bits.

14
include/asm-mips/dec/kn02.h
View File

@ -13,11 +13,7 @@
#ifndef __ASM_MIPS_DEC_KN02_H
#define __ASM_MIPS_DEC_KN02_H
#include <asm/addrspace.h>
#include <asm/dec/ecc.h>
#define KN02_SLOT_BASE CKSEG1ADDR(0x1fc00000)
#define KN02_SLOT_BASE 0x1fc00000
#define KN02_SLOT_SIZE 0x00080000
/*
@ -33,14 +29,6 @@
#define KN02_SYS_ROM_7 (7*KN02_SLOT_SIZE) /* system board ROM (alias) */
/*
* Some port addresses...
*/
#define KN02_DZ11_BASE (KN02_SLOT_BASE + KN02_DZ11) /* DZ11 */
#define KN02_RTC_BASE (KN02_SLOT_BASE + KN02_RTC) /* RTC */
#define KN02_CSR_BASE (KN02_SLOT_BASE + KN02_CSR) /* CSR */
/*
* System Control & Status Register bits.
*/

22
include/asm-mips/dec/kn02xa.h
View File

@ -17,31 +17,23 @@
#ifndef __ASM_MIPS_DEC_KN02XA_H
#define __ASM_MIPS_DEC_KN02XA_H
#include <asm/addrspace.h>
#include <asm/dec/ioasic_addrs.h>
#define KN02XA_SLOT_BASE CKSEG1ADDR(0x1c000000)
/*
* Some port addresses...
*/
#define KN02XA_IOASIC_BASE (KN02XA_SLOT_BASE + IOASIC_IOCTL) /* I/O ASIC */
#define KN02XA_RTC_BASE (KN02XA_SLOT_BASE + IOASIC_TOY) /* RTC */
#define KN02XA_SLOT_BASE 0x1c000000
/*
* Memory control ASIC registers.
*/
#define KN02XA_MER CKSEG1ADDR(0x0c400000) /* memory error register */
#define KN02XA_MSR CKSEG1ADDR(0x0c800000) /* memory size register */
#define KN02XA_MER 0x0c400000 /* memory error register */
#define KN02XA_MSR 0x0c800000 /* memory size register */
/*
* CPU control ASIC registers.
*/
#define KN02XA_MEM_CONF CKSEG1ADDR(0x0e000000) /* write timeout config */
#define KN02XA_EAR CKSEG1ADDR(0x0e000004) /* error address register */
#define KN02XA_BOOT0 CKSEG1ADDR(0x0e000008) /* boot 0 register */
#define KN02XA_MEM_INTR CKSEG1ADDR(0x0e00000c) /* write err IRQ stat & ack */
#define KN02XA_MEM_CONF 0x0e000000 /* write timeout config */
#define KN02XA_EAR 0x0e000004 /* error address register */
#define KN02XA_BOOT0 0x0e000008 /* boot 0 register */
#define KN02XA_MEM_INTR 0x0e00000c /* write err IRQ stat & ack */
/*
* Memory Error Register bits, common definitions.

13
include/asm-mips/dec/kn03.h
View File

@ -10,24 +10,15 @@
*
* Copyright (C) 1995,1996 by Paul M. Antoine, some code and definitions
* are by courtesy of Chris Fraser.
* Copyright (C) 2000, 2002, 2003 Maciej W. Rozycki
* Copyright (C) 2000, 2002, 2003, 2005 Maciej W. Rozycki
*/
#ifndef __ASM_MIPS_DEC_KN03_H
#define __ASM_MIPS_DEC_KN03_H
#include <asm/addrspace.h>
#include <asm/dec/ecc.h>
#include <asm/dec/ioasic_addrs.h>
#define KN03_SLOT_BASE CKSEG1ADDR(0x1f800000)
/*
* Some port addresses...
*/
#define KN03_IOASIC_BASE (KN03_SLOT_BASE + IOASIC_IOCTL) /* I/O ASIC */
#define KN03_RTC_BASE (KN03_SLOT_BASE + IOASIC_TOY) /* RTC */
#define KN03_MCR_BASE (KN03_SLOT_BASE + IOASIC_MCR) /* MCR */
#define KN03_SLOT_BASE 0x1f800000
/*
* CPU interrupt bits.

3
include/asm-mips/dec/kn05.h
View File

@ -21,7 +21,6 @@
#ifndef __ASM_MIPS_DEC_KN05_H
#define __ASM_MIPS_DEC_KN05_H
#include <asm/addrspace.h>
#include <asm/dec/ioasic_addrs.h>
/*
@ -30,7 +29,7 @@
* passed to the I/O ASIC's decoder like with the KN03 or KN02-BA/CA.
* Others are handled locally. "Low" slots are always passed.
*/
#define KN4K_SLOT_BASE KSEG1ADDR(0x1fc00000)
#define KN4K_SLOT_BASE 0x1fc00000
#define KN4K_MB_ROM (0*IOASIC_SLOT_SIZE) /* KN05/KN04 card ROM */
#define KN4K_IOCTL (1*IOASIC_SLOT_SIZE) /* I/O ASIC */

18
include/asm-mips/dec/system.h Normal file
View File

@ -0,0 +1,18 @@
/*
* include/asm-mips/dec/system.h
*
* Generic DECstation/DECsystem bits.
*
* Copyright (C) 2005 Maciej W. Rozycki
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*/
#ifndef __ASM_DEC_SYSTEM_H
#define __ASM_DEC_SYSTEM_H
extern unsigned long dec_kn_slot_base, dec_kn_slot_size;
#endif /* __ASM_DEC_SYSTEM_H */

10
include/asm-mips/dec/tc.h
View File

@ -7,10 +7,8 @@
*
* Copyright (c) 1998 Harald Koerfgen
*/
#ifndef ASM_TC_H
#define ASM_TC_H
extern unsigned long system_base;
#ifndef __ASM_DEC_TC_H
#define __ASM_DEC_TC_H
/*
* Search for a TURBOchannel Option Module
@ -36,8 +34,8 @@ extern unsigned long get_tc_base_addr(int);
*/
extern unsigned long get_tc_irq_nr(int);
/*
* Return TURBOchannel clock frequency in hz
* Return TURBOchannel clock frequency in Hz
*/
extern unsigned long get_tc_speed(void);
#endif
#endif /* __ASM_DEC_TC_H */

11
include/asm-mips/mach-dec/mc146818rtc.h
View File

@ -3,7 +3,7 @@
*
* Copyright (C) 1998, 2001 by Ralf Baechle
* Copyright (C) 1998 by Harald Koerfgen
* Copyright (C) 2002 Maciej W. Rozycki
* Copyright (C) 2002, 2005 Maciej W. Rozycki
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
@ -14,23 +14,18 @@
#define __ASM_MIPS_DEC_RTC_DEC_H
#include <linux/types.h>
#include <asm/addrspace.h>
#include <asm/dec/system.h>
extern volatile u8 *dec_rtc_base;
extern unsigned long dec_kn_slot_size;
#define RTC_PORT(x) CPHYSADDR(dec_rtc_base)
#define RTC_PORT(x) CPHYSADDR((long)dec_rtc_base)
#define RTC_IO_EXTENT dec_kn_slot_size
#define RTC_IOMAPPED 0
#undef RTC_IRQ
#define RTC_DEC_YEAR 0x3f /* Where we store the real year on DECs. */
#include <linux/mc146818rtc.h>
#include <linux/module.h>
#include <linux/types.h>
static inline unsigned char CMOS_READ(unsigned long addr)
{
return dec_rtc_base[addr * 4];