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i.MX ARM device tree for 6.9:

Browse Source 
- New board support: Sielaff i.MX6 Solo, Apalis Evaluation Board v1.2.
 - A bunch of i.MX7 TQMA7/MBA7 updates from Alexander Stein that add
   various devices, improve hardware descriptions and fix dt-schema
   warnings, etc.
 - Correct touchscreen rotation for imx6sl-tolino-shine2hd board.
 - An imx53-qsb update from Dmitry Baryshkov to add HDMI expander support.
 - A couple of i.MX1 and i.MX28 device node name fixes from Fabio Estevam.
 - Enable usb3-lpm-capable for LS1021A usb3 node.
 - A couple of imx6dl-yapp4 board improvements from Michal Vokáč.
 - A series from Sebastian Reichel to improve imx6ull descriptions.
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Merge tag 'imx-dt-6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into soc/dt

i.MX ARM device tree for 6.9:

- New board support: Sielaff i.MX6 Solo, Apalis Evaluation Board v1.2.
- A bunch of i.MX7 TQMA7/MBA7 updates from Alexander Stein that add
  various devices, improve hardware descriptions and fix dt-schema
  warnings, etc.
- Correct touchscreen rotation for imx6sl-tolino-shine2hd board.
- An imx53-qsb update from Dmitry Baryshkov to add HDMI expander support.
- A couple of i.MX1 and i.MX28 device node name fixes from Fabio Estevam.
- Enable usb3-lpm-capable for LS1021A usb3 node.
- A couple of imx6dl-yapp4 board improvements from Michal Vokáč.
- A series from Sebastian Reichel to improve imx6ull descriptions.

* tag 'imx-dt-6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (43 commits)
  ARM: dts: nxp: imx: fix weim node name
  ARM: dts: nxp: imx6ul: fix touchscreen node name
  ARM: dts: nxp: imx6ul: xnur-gpio -> xnur-gpios
  ARM: dts: imx6ul: Remove fsl,anatop from usbotg1
  ARM: dts: imx6ull: fix pinctrl node name
  ARM: dts: imx1-apf9328: Fix Ethernet node name
  ARM: dts: imx28-evk: Use 'eeprom' as the node name
  ARM: dts: ls1021a: Enable usb3-lpm-capable for usb3 node
  ARM: dts: imx6dl-yapp4: Move the internal switch PHYs under the switch node
  ARM: dts: imx6dl-yapp4: Fix typo in the QCA switch register address
  ARM: dts: imx6ul: Set macaddress location in ocotp
  ARM: dts: imx53-qsb: add support for the HDMI expander
  ARM: dts: imx6ull-dhcom: Remove /omit-if-no-ref/ from node usdhc1-pwrseq
  ARM: dts: imx: Add support for Apalis Evaluation Board v1.2
  ARM: dts: imx6: skov: add aliases for all ethernet nodes
  ARM: dts: imx6qdl-hummingboard: Add rtc0 and rtc1 aliases to fix hctosys
  ARM: dts: imx6dl: Add support for Sielaff i.MX6 Solo board
  ARM: dts: imx6ul: Add missing #thermal-sensor-cells to tempmon
  ARM: dts: imx6sl-tolino-shine2hd: fix touchscreen rotation
  ARM: dts: imx6ull-dhcor: Remove 900MHz operating point
  ...

Link: https://lore.kernel.org/r/20240226034147.233993-3-shawnguo2@yeah.net
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2024-03-01 13:00:25 +01:00
commit a634daed69
33 changed files with 1333 additions and 389 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
arch/arm/boot/dts/nxp/imx/Makefile
View File

@ -45,7 +45,9 @@ dtb-$(CONFIG_SOC_IMX53) += \
imx53-mba53.dtb \
imx53-ppd.dtb \
imx53-qsb.dtb \
imx53-qsb-hdmi.dtb \
imx53-qsrb.dtb \
imx53-qsrb-hdmi.dtb \
imx53-sk-imx53.dtb \
imx53-sk-imx53-atm0700d4-lvds.dtb \
imx53-sk-imx53-atm0700d4-rgb.dtb \
@ -54,6 +56,8 @@ dtb-$(CONFIG_SOC_IMX53) += \
imx53-tx53-x13x.dtb \
imx53-usbarmory.dtb \
imx53-voipac-bsb.dtb
imx53-qsb-hdmi-dtbs := imx53-qsb.dtb imx53-qsb-hdmi.dtbo
imx53-qsrb-hdmi-dtbs := imx53-qsrb.dtb imx53-qsb-hdmi.dtbo
dtb-$(CONFIG_SOC_IMX6Q) += \
imx6dl-alti6p.dtb \
imx6dl-apf6dev.dtb \
@ -118,6 +122,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6dl-sabrelite.dtb \
imx6dl-sabresd.dtb \
imx6dl-savageboard.dtb \
imx6dl-sielaff.dtb \
imx6dl-skov-revc-lt2.dtb \
imx6dl-skov-revc-lt6.dtb \
imx6dl-solidsense.dtb \
@ -147,6 +152,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6dl-yapp4-phoenix.dtb \
imx6dl-yapp4-ursa.dtb \
imx6q-apalis-eval.dtb \
imx6q-apalis-eval-v1.2.dtb \
imx6q-apalis-ixora.dtb \
imx6q-apalis-ixora-v1.1.dtb \
imx6q-apalis-ixora-v1.2.dtb \

2
arch/arm/boot/dts/nxp/imx/imx1-apf9328.dts
View File

@ -54,7 +54,7 @@
#size-cells = <1>;
};
eth: eth@4,c00000 {
eth: ethernet@4,c00000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_eth>;
compatible = "davicom,dm9000";

2
arch/arm/boot/dts/nxp/imx/imx1.dtsi
View File

@ -251,7 +251,7 @@
};
};
weim: weim@220000 {
weim: memory-controller@220000 {
#address-cells = <2>;
#size-cells = <1>;
compatible = "fsl,imx1-weim";

2
arch/arm/boot/dts/nxp/imx/imx27.dtsi
View File

@ -568,7 +568,7 @@
status = "disabled";
};
weim: weim@d8002000 {
weim: memory-controller@d8002000 {
#address-cells = <2>;
#size-cells = <1>;
compatible = "fsl,imx27-weim";

2
arch/arm/boot/dts/nxp/imx/imx31.dtsi
View File

@ -352,7 +352,7 @@
status = "disabled";
};
weim: weim@b8002000 {
weim: memory-controller@b8002000 {
compatible = "fsl,imx31-weim", "fsl,imx27-weim";
reg = <0xb8002000 0x1000>;
clocks = <&clks 56>;

2
arch/arm/boot/dts/nxp/imx/imx35.dtsi
View File

@ -374,7 +374,7 @@
status = "disabled";
};
weim: weim@b8002000 {
weim: memory-controller@b8002000 {
#address-cells = <2>;
#size-cells = <1>;
clocks = <&clks 0>;

2
arch/arm/boot/dts/nxp/imx/imx51.dtsi
View File

@ -578,7 +578,7 @@
reg = <0x83fd8000 0x1000>;
};
weim: weim@83fda000 {
weim: memory-controller@83fda000 {
#address-cells = <2>;
#size-cells = <1>;
compatible = "fsl,imx51-weim";

87
arch/arm/boot/dts/nxp/imx/imx53-qsb-hdmi.dtso Normal file
View File

@ -0,0 +1,87 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* DT overlay for MCIMXHDMICARD as used with the iMX53 QSB or QSRB boards
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h>
/dts-v1/;
/plugin/;
&{/} {
/delete-node/ panel;
hdmi: connector-hdmi {
compatible = "hdmi-connector";
label = "hdmi";
type = "a";
port {
hdmi_connector_in: endpoint {
remote-endpoint = <&sii9022_out>;
};
};
};
reg_1p2v: regulator-1p2v {
compatible = "regulator-fixed";
regulator-name = "1P2V";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
vin-supply = <&reg_3p2v>;
};
};
&display0 {
status = "okay";
};
&display0 {
port@1 {
display0_out: endpoint {
remote-endpoint = <&sii9022_in>;
};
};
};
&i2c2 {
#address-cells = <1>;
#size-cells = <0>;
sii9022: bridge-hdmi@39 {
compatible = "sil,sii9022";
reg = <0x39>;
reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
interrupts-extended = <&gpio3 31 IRQ_TYPE_LEVEL_LOW>;
iovcc-supply = <&reg_3p2v>;
#sound-dai-cells = <0>;
sil,i2s-data-lanes = <0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
sii9022_in: endpoint {
remote-endpoint = <&display0_out>;
};
};
port@1 {
reg = <1>;
sii9022_out: endpoint {
remote-endpoint = <&hdmi_connector_in>;
};
};
};
};
};
&tve {
status = "disabled";
};

533
arch/arm/boot/dts/nxp/imx/imx6dl-sielaff.dts Normal file
View File

@ -0,0 +1,533 @@
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
* Copyright (C) 2022 Kontron Electronics GmbH
*/
/dts-v1/;
#include "imx6dl.dtsi"
#include <dt-bindings/clock/imx6qdl-clock.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ {
model = "Sielaff i.MX6 Solo";
compatible = "sielaff,imx6dl-board", "fsl,imx6dl";
chosen {
stdout-path = &uart2;
};
backlight: pwm-backlight {
compatible = "pwm-backlight";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_backlight>;
pwms = <&pwm3 0 50000 0>;
brightness-levels = <0 0 64 88 112 136 184 232 255>;
default-brightness-level = <4>;
enable-gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>;
power-supply = <&reg_backlight>;
};
cec {
compatible = "cec-gpio";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hdmi_cec>;
cec-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>;
hdmi-phandle = <&hdmi>;
};
enet_ref: clock-enet-ref {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <50000000>;
clock-output-names = "enet-ref";
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_keys>;
key-0 {
gpios = <&gpio2 16 0>;
debounce-interval = <10>;
linux,code = <1>;
};
key-1 {
gpios = <&gpio3 27 0>;
debounce-interval = <10>;
linux,code = <2>;
};
key-2 {
gpios = <&gpio5 4 0>;
debounce-interval = <10>;
linux,code = <3>;
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_leds>;
led-debug {
label = "debug-led";
gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>;
default-state = "off";
linux,default-trigger = "heartbeat";
};
};
memory@80000000 {
reg = <0x80000000 0x20000000>;
device_type = "memory";
};
osc_eth_phy: clock-osc-eth-phy {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
clock-output-names = "osc-eth-phy";
};
panel {
compatible = "lg,lb070wv8";
backlight = <&backlight>;
power-supply = <&reg_3v3>;
port {
panel_in_lvds: endpoint {
remote-endpoint = <&lvds_out>;
};
};
};
reg_3v3: regulator-3v3 {
compatible = "regulator-fixed";
regulator-name = "3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
reg_backlight: regulator-backlight {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_backlight>;
enable-active-high;
gpio = <&gpio1 23 GPIO_ACTIVE_HIGH>;
regulator-name = "backlight";
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
};
reg_usb_otg_vbus: regulator-usb-otg-vbus {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usbotg_vbus>;
enable-active-high;
gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>;
regulator-name = "usb_otg_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
};
&ecspi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi2>;
cs-gpios = <&gpio5 29 GPIO_ACTIVE_LOW>;
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <20000000>;
};
};
&fec {
/*
* Set PTP clock to external instead of internal reference, as the
* REF_CLK from the PHY is fed back into the i.MX6 and the GPR
* register needs to be set accordingly (see mach-imx6q.c).
*/
clocks = <&clks IMX6QDL_CLK_ENET>,
<&clks IMX6QDL_CLK_ENET>,
<&enet_ref>,
<&clks IMX6QDL_CLK_ENET_REF>;
clock-names = "ipg", "ahb", "ptp", "enet_out";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-connection-type = "rmii";
phy-handle = <&ethphy>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy: ethernet-phy@1 {
reg = <1>;
clocks = <&osc_eth_phy>;
clock-names = "rmii-ref";
micrel,led-mode = <1>;
reset-assert-us = <500>;
reset-deassert-us = <100>;
reset-gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
};
};
};
&gpio1 {
gpio-line-names =
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "key-out", "key-in",
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "";
};
&gpio2 {
gpio-line-names =
"", "", "", "", "", "", "", "",
"lan9500a-rst", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "";
};
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
status = "okay";
};
&hdmi {
ddc-i2c-bus = <&i2c4>;
status = "okay";
};
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
clock-frequency = <100000>;
status = "okay";
rtc@51 {
compatible = "nxp,pcf8563";
reg = <0x51>;
};
};
&i2c3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
clock-frequency = <100000>;
status = "okay";
touchscreen@55 {
compatible = "sitronix,st1633";
reg = <0x55>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_touch>;
interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
interrupt-parent = <&gpio5>;
gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
status = "disabled";
};
touchscreen@5d {
compatible = "goodix,gt928";
reg = <0x5d>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_touch>;
interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
interrupt-parent = <&gpio5>;
irq-gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
status = "disabled";
};
};
&i2c4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4>;
clock-frequency = <100000>;
status = "okay";
};
&ldb {
status = "okay";
lvds: lvds-channel@0 {
fsl,data-mapping = "spwg";
fsl,data-width = <24>;
status = "okay";
port@4 {
reg = <4>;
lvds_out: endpoint {
remote-endpoint = <&panel_in_lvds>;
};
};
};
};
&pwm3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm3>;
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
status = "okay";
};
&usbh1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbh1>;
disable-over-current;
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
usb1@1 {
compatible = "usb4b4,6570";
reg = <1>;
clocks = <&clks IMX6QDL_CLK_CKO>;
assigned-clocks = <&clks IMX6QDL_CLK_CKO>,
<&clks IMX6QDL_CLK_CKO2_SEL>;
assigned-clock-parents = <&clks IMX6QDL_CLK_CKO2>,
<&clks IMX6QDL_CLK_OSC>;
assigned-clock-rates = <12000000 0>;
};
};
&usbotg {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg>;
dr_mode = "host";
over-current-active-low;
vbus-supply = <&reg_usb_otg_vbus>;
status = "okay";
};
&usdhc3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc3>;
cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
vmmc-supply = <&reg_3v3>;
voltage-ranges = <3300 3300>;
no-1-8-v;
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
pinctrl_hog: hoggrp {
fsl,pins = <
MX6QDL_PAD_RGMII_RD0__GPIO6_IO25 0x1b0b0 /* PMIC_IRQ */
MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x1b0b0
MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x1b0b0
MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x1b0b0
MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x1b0b0
MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b0
>;
};
pinctrl_backlight: backlightgrp {
fsl,pins = <
MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x100b1
>;
};
pinctrl_ecspi2: ecspi2grp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x100b1
MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x100b1
MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK 0x100b1
MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x100b1
>;
};
pinctrl_enet: enetgrp {
fsl,pins = <
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0
MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0
MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0
MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0
MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0
MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0
MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b1
>;
};
pinctrl_gpio_keys: gpiokeysgrp {
fsl,pins = <
MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x1b080
MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x1b080
MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x1b080
>;
};
pinctrl_gpio_leds: gpioledsgrp {
fsl,pins = <
MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x1b0b0
>;
};
pinctrl_gpmi_nand: gpminandgrp {
fsl,pins = <
MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
>;
};
pinctrl_hdmi_cec: hdmicecgrp {
fsl,pins = <
MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x1b8b1
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001f8b1
MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001f8b1
>;
};
pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX6QDL_PAD_GPIO_7__I2C4_SCL 0x4001b8b1
MX6QDL_PAD_GPIO_8__I2C4_SDA 0x4001b8b1
>;
};
pinctrl_pwm3: pwm3grp {
fsl,pins = <
MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
>;
};
pinctrl_reg_backlight: regbacklightgrp {
fsl,pins = <
MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 0x1b0b1
>;
};
pinctrl_reg_usbotg_vbus: regusbotgvbusgrp {
fsl,pins = <
MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b1
>;
};
pinctrl_touch: touchgrp {
fsl,pins = <
MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x1b0b0
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b0
MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b0
>;
};
pinctrl_usbh1: usbh1grp {
fsl,pins = <
MX6QDL_PAD_GPIO_3__USB_H1_OC 0x1b0b1
MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x1b0b0
>;
};
pinctrl_usbotg: usbotggrp {
fsl,pins = <
MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b1
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x100b1
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX6QDL_PAD_GPIO_9__WDOG1_B 0x1b0b0
>;
};
};

25
arch/arm/boot/dts/nxp/imx/imx6dl-yapp4-common.dtsi
View File

@ -117,17 +117,9 @@
#address-cells = <1>;
#size-cells = <0>;
phy_port2: phy@1 {
reg = <1>;
};
phy_port3: phy@2 {
reg = <2>;
};
switch@10 {
compatible = "qca,qca8334";
reg = <10>;
reg = <0x10>;
reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
switch_ports: ports {
@ -149,15 +141,30 @@
eth2: port@2 {
reg = <2>;
label = "eth2";
phy-mode = "internal";
phy-handle = <&phy_port2>;
};
eth1: port@3 {
reg = <3>;
label = "eth1";
phy-mode = "internal";
phy-handle = <&phy_port3>;
};
};
mdio {
#address-cells = <1>;
#size-cells = <0>;
phy_port2: ethernet-phy@1 {
reg = <1>;
};
phy_port3: ethernet-phy@2 {
reg = <2>;
};
};
};
};
};

200
arch/arm/boot/dts/nxp/imx/imx6q-apalis-eval-v1.2.dts Normal file
View File

@ -0,0 +1,200 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright 2024 Toradex
*/
/dts-v1/;
#include "imx6q-apalis-eval.dtsi"
/ {
model = "Toradex Apalis iMX6Q/D Module on Apalis Evaluation Board v1.2";
compatible = "toradex,apalis_imx6q-eval-v1.2", "toradex,apalis_imx6q",
"fsl,imx6q";
reg_3v3_mmc: regulator-3v3-mmc {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio2 0 GPIO_ACTIVE_HIGH>;
off-on-delay-us = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enable_3v3_mmc>;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
regulator-name = "3.3V_MMC";
startup-delay-us = <10000>;
};
reg_3v3_sd: regulator-3v3-sd {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio2 1 GPIO_ACTIVE_HIGH>;
off-on-delay-us = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enable_3v3_sd>;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
regulator-name = "3.3V_SD";
startup-delay-us = <10000>;
};
reg_can1: regulator-can1 {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio2 3 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enable_can1_power>;
regulator-name = "5V_SW_CAN1";
startup-delay-us = <10000>;
};
reg_can2: regulator-can2 {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio2 2 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enable_can2_power>;
regulator-name = "5V_SW_CAN2";
startup-delay-us = <10000>;
};
sound-carrier {
compatible = "simple-audio-card";
simple-audio-card,bitclock-master = <&codec_dai>;
simple-audio-card,format = "i2s";
simple-audio-card,frame-master = <&codec_dai>;
simple-audio-card,name = "apalis-nau8822";
simple-audio-card,routing =
"Headphones", "LHP",
"Headphones", "RHP",
"Speaker", "LSPK",
"Speaker", "RSPK",
"Line Out", "AUXOUT1",
"Line Out", "AUXOUT2",
"LAUX", "Line In",
"RAUX", "Line In",
"LMICP", "Mic In",
"RMICP", "Mic In";
simple-audio-card,widgets =
"Headphones", "Headphones",
"Line Out", "Line Out",
"Speaker", "Speaker",
"Microphone", "Mic In",
"Line", "Line In";
codec_dai: simple-audio-card,codec {
sound-dai = <&nau8822_1a>;
system-clock-frequency = <12288000>;
};
simple-audio-card,cpu {
sound-dai = <&ssi2>;
};
};
};
&can1 {
xceiver-supply = <&reg_can1>;
status = "okay";
};
&can2 {
xceiver-supply = <&reg_can2>;
status = "okay";
};
/* I2C1_SDA/SCL on MXM3 209/211 */
&i2c1 {
/* Audio Codec */
nau8822_1a: audio-codec@1a {
compatible = "nuvoton,nau8822";
reg = <0x1a>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_nau8822>;
#sound-dai-cells = <0>;
};
/* Current measurement into module VCC */
hwmon@40 {
compatible = "ti,ina219";
reg = <0x40>;
shunt-resistor = <5000>;
};
/* Temperature Sensor */
temperature-sensor@4f {
compatible = "ti,tmp75c";
reg = <0x4f>;
};
/* EEPROM */
eeprom@57 {
compatible = "st,24c02", "atmel,24c02";
reg = <0x57>;
pagesize = <16>;
size = <256>;
};
};
&pcie {
status = "okay";
};
&ssi2 {
status = "okay";
};
/* MMC1 */
&usdhc1 {
bus-width = <4>;
pinctrl-0 = <&pinctrl_usdhc1_4bit &pinctrl_mmc_cd>;
vmmc-supply = <&reg_3v3_mmc>;
status = "okay";
};
/* SD1 */
&usdhc2 {
cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pinctrl_usdhc2 &pinctrl_sd_cd>;
vmmc-supply = <&reg_3v3_sd>;
status = "okay";
};
&iomuxc {
pinctrl_enable_3v3_mmc: enable3v3mmcgrp {
fsl,pins = <
/* MMC1_PWR_CTRL */
MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0
>;
};
pinctrl_enable_3v3_sd: enable3v3sdgrp {
fsl,pins = <
/* SD1_PWR_CTRL */
MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0
>;
};
pinctrl_enable_can1_power: enablecan1powergrp {
fsl,pins = <
/* CAN1_PWR_EN */
MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0
>;
};
pinctrl_enable_can2_power: enablecan2powergrp {
fsl,pins = <
/* CAN2_PWR_EN */
MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0
>;
};
pinctrl_nau8822: nau8822grp {
fsl,pins = <
MX6QDL_PAD_DISP0_DAT16__AUD5_TXC 0x130b0
MX6QDL_PAD_DISP0_DAT17__AUD5_TXD 0x130b0
MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS 0x130b0
MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0
>;
};
};

108
arch/arm/boot/dts/nxp/imx/imx6q-apalis-eval.dts
View File

@ -7,29 +7,13 @@
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include "imx6q.dtsi"
#include "imx6qdl-apalis.dtsi"
#include "imx6q-apalis-eval.dtsi"
/ {
model = "Toradex Apalis iMX6Q/D Module on Apalis Evaluation Board";
compatible = "toradex,apalis_imx6q-eval", "toradex,apalis_imx6q",
"fsl,imx6q";
aliases {
i2c0 = &i2c1;
i2c1 = &i2c3;
i2c2 = &i2c2;
rtc0 = &rtc_i2c;
rtc1 = &snvs_rtc;
};
chosen {
stdout-path = "serial0:115200n8";
};
reg_pcie_switch: regulator-pcie-switch {
compatible = "regulator-fixed";
enable-active-high;
@ -40,14 +24,6 @@
startup-delay-us = <100000>;
status = "okay";
};
reg_3v3_sw: regulator-3v3-sw {
compatible = "regulator-fixed";
regulator-always-on;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
regulator-name = "3.3V_SW";
};
};
&can1 {
@ -62,102 +38,22 @@
/* I2C1_SDA/SCL on MXM3 209/211 (e.g. RTC on carrier board) */
&i2c1 {
status = "okay";
/* PCIe Switch */
pcie-switch@58 {
compatible = "plx,pex8605";
reg = <0x58>;
};
/* M41T0M6 real time clock on carrier board */
rtc_i2c: rtc@68 {
compatible = "st,m41t0";
reg = <0x68>;
};
};
/*
* I2C3_SDA/SCL (CAM) on MXM3 pin 201/203 (e.g. camera sensor on carrier
* board)
*/
&i2c3 {
status = "okay";
};
&pcie {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reset_moci>;
/* active-high meaning opposite of regular PERST# active-low polarity */
reset-gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>;
reset-gpio-active-high;
vpcie-supply = <&reg_pcie_switch>;
status = "okay";
};
&pwm1 {
status = "okay";
};
&pwm2 {
status = "okay";
};
&pwm3 {
status = "okay";
};
&pwm4 {
status = "okay";
};
&reg_usb_host_vbus {
status = "okay";
};
&reg_usb_otg_vbus {
status = "okay";
};
&sata {
status = "okay";
};
&sound_spdif {
status = "okay";
};
&spdif {
status = "okay";
};
&uart1 {
status = "okay";
};
&uart2 {
status = "okay";
};
&uart4 {
status = "okay";
};
&uart5 {
status = "okay";
};
&usbh1 {
disable-over-current;
vbus-supply = <&reg_usb_host_vbus>;
status = "okay";
};
&usbotg {
disable-over-current;
vbus-supply = <&reg_usb_otg_vbus>;
status = "okay";
};
/* MMC1 */
&usdhc1 {
status = "okay";

120
arch/arm/boot/dts/nxp/imx/imx6q-apalis-eval.dtsi Normal file
View File

@ -0,0 +1,120 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright 2014-2024 Toradex
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include "imx6q.dtsi"
#include "imx6qdl-apalis.dtsi"
/ {
aliases {
i2c0 = &i2c1;
i2c1 = &i2c3;
i2c2 = &i2c2;
rtc0 = &rtc_i2c;
rtc1 = &snvs_rtc;
};
chosen {
stdout-path = "serial0:115200n8";
};
reg_3v3_sw: regulator-3v3-sw {
compatible = "regulator-fixed";
regulator-always-on;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
regulator-name = "3.3V_SW";
};
};
&i2c1 {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
/* M41T0M6 real time clock on carrier board */
rtc_i2c: rtc@68 {
compatible = "st,m41t0";
reg = <0x68>;
};
};
/*
* I2C3_SDA/SCL (CAM) on MXM3 pin 201/203 (e.g. camera sensor on carrier
* board)
*/
&i2c3 {
status = "okay";
};
&pcie {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reset_moci>;
/* active-high meaning opposite of regular PERST# active-low polarity */
reset-gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>;
reset-gpio-active-high;
};
&pwm1 {
status = "okay";
};
&pwm2 {
status = "okay";
};
&pwm3 {
status = "okay";
};
&pwm4 {
status = "okay";
};
&reg_usb_host_vbus {
status = "okay";
};
&reg_usb_otg_vbus {
status = "okay";
};
&sata {
status = "okay";
};
&spdif {
status = "okay";
};
&uart1 {
status = "okay";
};
&uart2 {
status = "okay";
};
&uart4 {
status = "okay";
};
&uart5 {
status = "okay";
};
&usbh1 {
disable-over-current;
vbus-supply = <&reg_usb_host_vbus>;
status = "okay";
};
&usbotg {
disable-over-current;
vbus-supply = <&reg_usb_otg_vbus>;
status = "okay";
};

7
arch/arm/boot/dts/nxp/imx/imx6qdl-hummingboard.dtsi
View File

@ -41,6 +41,11 @@
#include <dt-bindings/sound/fsl-imx-audmux.h>
/ {
aliases {
rtc0 = &carrier_rtc;
rtc1 = &snvs_rtc;
};
/* Will be filled by the bootloader */
memory@10000000 {
device_type = "memory";
@ -187,7 +192,7 @@
status = "okay";
/* Pro baseboard model */
rtc@68 {
carrier_rtc: rtc@68 {
compatible = "nxp,pcf8523";
reg = <0x68>;
};

5
arch/arm/boot/dts/nxp/imx/imx6qdl-hummingboard2.dtsi
View File

@ -41,6 +41,11 @@
#include <dt-bindings/sound/fsl-imx-audmux.h>
/ {
aliases {
rtc0 = &pcf8523;
rtc1 = &snvs_rtc;
};
/* Will be filled by the bootloader */
memory@10000000 {
device_type = "memory";

10
arch/arm/boot/dts/nxp/imx/imx6qdl-skov-cpu.dtsi
View File

@ -13,10 +13,14 @@
aliases {
can0 = &can1;
can1 = &can2;
ethernet0 = &fec;
ethernet1 = &lan1;
ethernet2 = &lan2;
mdio-gpio0 = &mdio;
nand = &gpmi;
rtc0 = &i2c_rtc;
rtc1 = &snvs;
switch0 = &switch;
usb0 = &usbh1;
usb1 = &usbotg;
};
@ -60,7 +64,7 @@
gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>,
<&gpio1 22 GPIO_ACTIVE_HIGH>;
switch@0 {
switch: switch@0 {
compatible = "microchip,ksz8873";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_switch>;
@ -73,13 +77,13 @@
#address-cells = <1>;
#size-cells = <0>;
ports@0 {
lan1: ports@0 {
reg = <0>;
phy-mode = "internal";
label = "lan1";
};
ports@1 {
lan2: ports@1 {
reg = <1>;
phy-mode = "internal";
label = "lan2";

2
arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi
View File

@ -1158,7 +1158,7 @@
status = "disabled";
};
weim: weim@21b8000 {
weim: memory-controller@21b8000 {
#address-cells = <2>;
#size-cells = <1>;
compatible = "fsl,imx6q-weim";

6
arch/arm/boot/dts/nxp/imx/imx6sl-tolino-shine2hd.dts
View File

@ -141,8 +141,10 @@
interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
vdd-supply = <&ldo1_reg>;
reset-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
x-size = <1072>;
y-size = <1448>;
touchscreen-size-x = <1072>;
touchscreen-size-y = <1448>;
touchscreen-swapped-x-y;
touchscreen-inverted-x;
};
/* TODO: TPS65185 PMIC for E Ink at 0x68 */

2
arch/arm/boot/dts/nxp/imx/imx6sl.dtsi
View File

@ -949,7 +949,7 @@
clocks = <&clks IMX6SL_CLK_DUMMY>;
};
weim: weim@21b8000 {
weim: memory-controller@21b8000 {
#address-cells = <2>;
#size-cells = <1>;
reg = <0x021b8000 0x4000>;

2
arch/arm/boot/dts/nxp/imx/imx6sx.dtsi
View File

@ -1107,7 +1107,7 @@
status = "disabled";
};
weim: weim@21b8000 {
weim: memory-controller@21b8000 {
#address-cells = <2>;
#size-cells = <1>;
compatible = "fsl,imx6sx-weim", "fsl,imx6q-weim";

2
arch/arm/boot/dts/nxp/imx/imx6ul-14x14-evk.dtsi
View File

@ -321,7 +321,7 @@
&tsc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_tsc>;
xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
xnur-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
measure-delay-time = <0xffff>;
pre-charge-time = <0xfff>;
status = "okay";

2
arch/arm/boot/dts/nxp/imx/imx6ul-geam.dts
View File

@ -203,7 +203,7 @@
&tsc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_tsc>;
xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
xnur-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
};
&sai2 {

2
arch/arm/boot/dts/nxp/imx/imx6ul-imx6ull-opos6uldev.dtsi
View File

@ -156,7 +156,7 @@
&tsc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_tsc>;
xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
xnur-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
measure-delay-time = <0xffff>;
pre-charge-time = <0xffff>;
status = "okay";

18
arch/arm/boot/dts/nxp/imx/imx6ul.dtsi
View File

@ -370,7 +370,7 @@
};
};
tsc: tsc@2040000 {
tsc: touchscreen@2040000 {
compatible = "fsl,imx6ul-tsc";
reg = <0x02040000 0x4000>, <0x0219c000 0x4000>;
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
@ -538,6 +538,8 @@
fsl,num-rx-queues = <1>;
fsl,stop-mode = <&gpr 0x10 4>;
fsl,magic-packet;
nvmem-cells = <&fec2_mac_addr>;
nvmem-cell-names = "mac-address";
status = "disabled";
};
@ -638,6 +640,7 @@
nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
nvmem-cell-names = "calib", "temp_grade";
clocks = <&clks IMX6UL_CLK_PLL3_USB_OTG>;
#thermal-sensor-cells = <0>;
};
};
@ -855,7 +858,6 @@
clocks = <&clks IMX6UL_CLK_USBOH3>;
fsl,usbphy = <&usbphy1>;
fsl,usbmisc = <&usbmisc 0>;
fsl,anatop = <&anatop>;
ahb-burst-config = <0x0>;
tx-burst-size-dword = <0x10>;
rx-burst-size-dword = <0x10>;
@ -897,6 +899,8 @@
fsl,num-rx-queues = <1>;
fsl,stop-mode = <&gpr 0x10 3>;
fsl,magic-packet;
nvmem-cells = <&fec1_mac_addr>;
nvmem-cell-names = "mac-address";
status = "disabled";
};
@ -975,7 +979,7 @@
clocks = <&clks IMX6UL_CLK_MMDC_P0_IPG>;
};
weim: weim@21b8000 {
weim: memory-controller@21b8000 {
#address-cells = <2>;
#size-cells = <1>;
compatible = "fsl,imx6ul-weim", "fsl,imx6q-weim";
@ -1004,6 +1008,14 @@
cpu_speed_grade: speed-grade@10 {
reg = <0x10 4>;
};
fec1_mac_addr: mac-addr@88 {
reg = <0x88 6>;
};
fec2_mac_addr: mac-addr@8e {
reg = <0x8e 6>;
};
};
csi: csi@21c4000 {

4
arch/arm/boot/dts/nxp/imx/imx6ull-dhcom-som-cfg-sdcard.dtsi
View File

@ -14,10 +14,12 @@
*/
/*
* To use usdhc1 as SD card, the WiFi node must be deleted.
* To use usdhc1 as SD card, the WiFi node must be deleted. The associated
* pwrseq node is also deleted in order to ensure that GPIO H is released.
* BT is also not available, so remove BT from the UART node.
*/
/delete-node/ &brcmf;
/delete-node/ &usdhc1_pwrseq;
/delete-node/ &bluetooth;
/ {

4
arch/arm/boot/dts/nxp/imx/imx6ull-dhcom-som.dtsi
View File

@ -52,7 +52,7 @@
};
/* SoM with WiFi/BT: WiFi pin WL_REG_ON is connected to a DHCOM GPIO */
/omit-if-no-ref/ usdhc1_pwrseq: usdhc1-pwrseq {
usdhc1_pwrseq: usdhc1-pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; /* GPIO H */
};
@ -273,7 +273,7 @@
pinctrl-names = "default";
pre-charge-time = <0xfff>;
touchscreen-average-samples = <32>;
xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
xnur-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
};
/* DHCOM UART1 */

7
arch/arm/boot/dts/nxp/imx/imx6ull-dhcor-som.dtsi
View File

@ -28,10 +28,14 @@
/*
* Due to the design as a solderable SOM, there are no capacitors
* below the SoC, therefore higher voltages are required.
* Due to CPU lifetime consideration of the SoC manufacturer and
* the preferred area of operation in the industrial related
* environment, set the maximum frequency for each DHCOM i.MX6ULL
* to 792MHz, as with the industrial type.
*/
clock-frequency = <792000000>;
operating-points = <
/* kHz uV */
900000 1275000
792000 1250000 /* Voltage increased */
528000 1175000
396000 1025000
@ -39,7 +43,6 @@
>;
fsl,soc-operating-points = <
/* KHz uV */
900000 1250000
792000 1250000 /* Voltage increased */
528000 1175000
396000 1175000

2
arch/arm/boot/dts/nxp/imx/imx6ull.dtsi
View File

@ -75,7 +75,7 @@
clocks = <&clks IMX6UL_CLK_DUMMY>;
};
iomuxc_snvs: iomuxc-snvs@2290000 {
iomuxc_snvs: pinctrl@2290000 {
compatible = "fsl,imx6ull-iomuxc-snvs";
reg = <0x02290000 0x4000>;
};

315
arch/arm/boot/dts/nxp/imx/imx7-mba7.dtsi
View File

@ -18,6 +18,8 @@
mmc0 = &usdhc3;
mmc1 = &usdhc1;
/delete-property/ mmc2;
rtc0 = &ds1339;
rtc1 = &snvs_rtc;
};
beeper {
@ -32,11 +34,18 @@
gpio_buttons: gpio-keys {
compatible = "gpio-keys";
/*
* NOTE: These buttons are attached to a GPIO-expander.
* Enabling wakeup-source, enables wakeup on all inputs.
* If PE_GPIO[3..6] are used as inputs, they cause a
* wakeup as well.
*/
button-0 {
/* #SWITCH_A */
label = "S11";
linux,code = <KEY_1>;
gpios = <&pca9555 13 GPIO_ACTIVE_LOW>;
wakeup-source;
};
button-1 {
@ -44,6 +53,7 @@
label = "S12";
linux,code = <KEY_2>;
gpios = <&pca9555 14 GPIO_ACTIVE_LOW>;
wakeup-source;
};
button-2 {
@ -51,6 +61,7 @@
label = "S13";
linux,code = <KEY_3>;
gpios = <&pca9555 15 GPIO_ACTIVE_LOW>;
wakeup-source;
};
};
@ -171,6 +182,14 @@
regulator-always-on;
};
reg_vcc_3v3: regulator-vcc-3v3 {
compatible = "regulator-fixed";
regulator-name = "VCC3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
sound {
compatible = "fsl,imx-audio-tlv320aic32x4";
model = "imx-audio-tlv320aic32x4";
@ -198,9 +217,9 @@
&ecspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
pinctrl-0 = <&pinctrl_ecspi1>, <&pinctrl_ecspi1_ss0>;
cs-gpios = <&gpio4 0 GPIO_ACTIVE_LOW>, <&gpio4 1 GPIO_ACTIVE_LOW>,
<&gpio4 2 GPIO_ACTIVE_LOW>;
<&gpio4 2 GPIO_ACTIVE_LOW>, <&gpio4 19 GPIO_ACTIVE_LOW>;
status = "okay";
};
@ -214,8 +233,6 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet1>;
phy-mode = "rgmii-id";
phy-reset-gpios = <&gpio7 15 GPIO_ACTIVE_LOW>;
phy-reset-duration = <1>;
phy-supply = <&reg_fec1_pwdn>;
phy-handle = <&ethphy1_0>;
fsl,magic-packet;
@ -228,10 +245,15 @@
ethphy1_0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet1_phy>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
reset-gpios = <&gpio7 15 GPIO_ACTIVE_LOW>;
reset-assert-us = <1000>;
reset-deassert-us = <500>;
};
};
};
@ -290,13 +312,17 @@
lm75: temperature-sensor@49 {
compatible = "national,lm75";
reg = <0x49>;
vs-supply = <&reg_vcc_3v3>;
};
};
&i2c2 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c2>;
pinctrl-1 = <&pinctrl_i2c2_recovery>;
scl-gpios = <&gpio4 10 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio4 11 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
tlv320aic32x4: audio-codec@18 {
@ -319,13 +345,17 @@
interrupts = <12 IRQ_TYPE_EDGE_FALLING>;
interrupt-controller;
#interrupt-cells = <2>;
vcc-supply = <&reg_vcc_3v3>;
};
};
&i2c3 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c3>;
pinctrl-1 = <&pinctrl_i2c3_recovery>;
scl-gpios = <&gpio4 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio4 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
};
@ -334,213 +364,213 @@
pinctrl-0 = <&pinctrl_hog_mba7_1>;
pinctrl_ecspi1: ecspi1grp {
fsl,pins =
<MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO 0x7c>,
<MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x74>,
<MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x74>,
<MX7D_PAD_UART1_RX_DATA__GPIO4_IO0 0x74>,
<MX7D_PAD_UART1_TX_DATA__GPIO4_IO1 0x74>,
<MX7D_PAD_UART2_RX_DATA__GPIO4_IO2 0x74>;
};
pinctrl_ecspi1_ss0: ecspi1ss0grp {
fsl,pins = <
MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO 0x7c
MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x74
MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x74
MX7D_PAD_UART1_RX_DATA__GPIO4_IO0 0x74
MX7D_PAD_UART1_TX_DATA__GPIO4_IO1 0x74
MX7D_PAD_UART2_RX_DATA__GPIO4_IO2 0x74
MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 0x74
>;
};
pinctrl_ecspi2: ecspi2grp {
fsl,pins = <
MX7D_PAD_ECSPI2_MISO__ECSPI2_MISO 0x7c
MX7D_PAD_ECSPI2_MOSI__ECSPI2_MOSI 0x74
MX7D_PAD_ECSPI2_SCLK__ECSPI2_SCLK 0x74
MX7D_PAD_ECSPI2_SS0__ECSPI2_SS0 0x74
>;
fsl,pins =
<MX7D_PAD_ECSPI2_MISO__ECSPI2_MISO 0x7c>,
<MX7D_PAD_ECSPI2_MOSI__ECSPI2_MOSI 0x74>,
<MX7D_PAD_ECSPI2_SCLK__ECSPI2_SCLK 0x74>,
<MX7D_PAD_ECSPI2_SS0__ECSPI2_SS0 0x74>;
};
pinctrl_enet1: enet1grp {
fsl,pins = <
MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x02
MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x00
MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x71
MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x71
MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x71
MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x71
MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x71
MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x71
MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x79
MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x79
MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x79
MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x79
MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x79
MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x79
fsl,pins =
<MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x02>,
<MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x00>,
<MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x71>,
<MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x71>,
<MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x71>,
<MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x71>,
<MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x71>,
<MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x71>,
<MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x79>,
<MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x79>,
<MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x79>,
<MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x79>,
<MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x79>,
<MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x79>;
};
pinctrl_enet1_phy: enet1phygrp {
fsl,pins =
/* Reset: SION, 100kPU, SRE_FAST, DSE_X1 */
MX7D_PAD_ENET1_COL__GPIO7_IO15 0x40000070
<MX7D_PAD_ENET1_COL__GPIO7_IO15 0x40000070>,
/* INT/PWDN: SION, 100kPU, HYS, SRE_FAST, DSE_X1 */
MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x40000078
>;
<MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x40000078>;
};
pinctrl_flexcan1: flexcan1grp {
fsl,pins = <
MX7D_PAD_GPIO1_IO12__FLEXCAN1_RX 0x5a
MX7D_PAD_GPIO1_IO13__FLEXCAN1_TX 0x52
>;
fsl,pins =
<MX7D_PAD_GPIO1_IO12__FLEXCAN1_RX 0x5a>,
<MX7D_PAD_GPIO1_IO13__FLEXCAN1_TX 0x52>;
};
pinctrl_flexcan2: flexcan2grp {
fsl,pins = <
MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x5a
MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x52
>;
fsl,pins =
<MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x5a>,
<MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x52>;
};
pinctrl_hog_mba7_1: hogmba71grp {
fsl,pins = <
fsl,pins =
/* Limitation: WDOG2_B / WDOG2_RESET not usable */
MX7D_PAD_ENET1_RX_CLK__GPIO7_IO13 0x4000007c
MX7D_PAD_ENET1_CRS__GPIO7_IO14 0x40000074
<MX7D_PAD_ENET1_RX_CLK__GPIO7_IO13 0x4000007c>,
<MX7D_PAD_ENET1_CRS__GPIO7_IO14 0x40000074>,
/* #BOOT_EN */
MX7D_PAD_UART2_TX_DATA__GPIO4_IO3 0x40000010
>;
<MX7D_PAD_UART2_TX_DATA__GPIO4_IO3 0x40000010>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX7D_PAD_I2C2_SCL__I2C2_SCL 0x40000078
MX7D_PAD_I2C2_SDA__I2C2_SDA 0x40000078
>;
fsl,pins =
<MX7D_PAD_I2C2_SCL__I2C2_SCL 0x40000078>,
<MX7D_PAD_I2C2_SDA__I2C2_SDA 0x40000078>;
};
pinctrl_i2c2_recovery: i2c2recoverygrp {
fsl,pins =
<MX7D_PAD_I2C2_SCL__GPIO4_IO10 0x40000078>,
<MX7D_PAD_I2C2_SDA__GPIO4_IO11 0x40000078>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX7D_PAD_I2C3_SCL__I2C3_SCL 0x40000078
MX7D_PAD_I2C3_SDA__I2C3_SDA 0x40000078
>;
fsl,pins =
<MX7D_PAD_I2C3_SCL__I2C3_SCL 0x40000078>,
<MX7D_PAD_I2C3_SDA__I2C3_SDA 0x40000078>;
};
pinctrl_i2c3_recovery: i2c3recoverygrp {
fsl,pins =
<MX7D_PAD_I2C3_SCL__GPIO4_IO12 0x40000078>,
<MX7D_PAD_I2C3_SDA__GPIO4_IO13 0x40000078>;
};
pinctrl_pca9555: pca95550grp {
fsl,pins = <
MX7D_PAD_ENET1_TX_CLK__GPIO7_IO12 0x78
>;
fsl,pins =
<MX7D_PAD_ENET1_TX_CLK__GPIO7_IO12 0x78>;
};
pinctrl_sai1: sai1grp {
fsl,pins = <
MX7D_PAD_SAI1_MCLK__SAI1_MCLK 0x11
MX7D_PAD_SAI1_RX_BCLK__SAI1_RX_BCLK 0x1c
MX7D_PAD_SAI1_RX_DATA__SAI1_RX_DATA0 0x1c
MX7D_PAD_SAI1_RX_SYNC__SAI2_RX_SYNC 0x1c
fsl,pins =
<MX7D_PAD_SAI1_MCLK__SAI1_MCLK 0x11>,
<MX7D_PAD_SAI1_RX_BCLK__SAI1_RX_BCLK 0x1c>,
<MX7D_PAD_SAI1_RX_DATA__SAI1_RX_DATA0 0x1c>,
<MX7D_PAD_SAI1_RX_SYNC__SAI2_RX_SYNC 0x1c>,
MX7D_PAD_SAI1_TX_BCLK__SAI1_TX_BCLK 0x1c
MX7D_PAD_SAI1_TX_DATA__SAI1_TX_DATA0 0x14
MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC 0x14
>;
<MX7D_PAD_SAI1_TX_BCLK__SAI1_TX_BCLK 0x1c>,
<MX7D_PAD_SAI1_TX_DATA__SAI1_TX_DATA0 0x14>,
<MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC 0x14>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX 0x7e
MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX 0x76
MX7D_PAD_UART3_CTS_B__UART3_DCE_CTS 0x76
MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS 0x7e
>;
fsl,pins =
<MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX 0x7e>,
<MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX 0x76>,
<MX7D_PAD_UART3_CTS_B__UART3_DCE_CTS 0x76>,
<MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS 0x7e>;
};
pinctrl_uart4: uart4grp {
fsl,pins = <
MX7D_PAD_SAI2_TX_SYNC__UART4_DCE_RX 0x7e
MX7D_PAD_SAI2_TX_BCLK__UART4_DCE_TX 0x76
MX7D_PAD_SAI2_RX_DATA__UART4_DCE_CTS 0x76
MX7D_PAD_SAI2_TX_DATA__UART4_DCE_RTS 0x7e
>;
fsl,pins =
<MX7D_PAD_SAI2_TX_SYNC__UART4_DCE_RX 0x7e>,
<MX7D_PAD_SAI2_TX_BCLK__UART4_DCE_TX 0x76>,
<MX7D_PAD_SAI2_RX_DATA__UART4_DCE_CTS 0x76>,
<MX7D_PAD_SAI2_TX_DATA__UART4_DCE_RTS 0x7e>;
};
pinctrl_uart5: uart5grp {
fsl,pins = <
MX7D_PAD_I2C4_SCL__UART5_DCE_RX 0x7e
MX7D_PAD_I2C4_SDA__UART5_DCE_TX 0x76
>;
fsl,pins =
<MX7D_PAD_I2C4_SCL__UART5_DCE_RX 0x7e>,
<MX7D_PAD_I2C4_SDA__UART5_DCE_TX 0x76>;
};
pinctrl_uart6: uart6grp {
fsl,pins = <
MX7D_PAD_EPDC_DATA08__UART6_DCE_RX 0x7d
MX7D_PAD_EPDC_DATA09__UART6_DCE_TX 0x75
MX7D_PAD_EPDC_DATA11__UART6_DCE_CTS 0x75
MX7D_PAD_EPDC_DATA10__UART6_DCE_RTS 0x7d
>;
fsl,pins =
<MX7D_PAD_EPDC_DATA08__UART6_DCE_RX 0x7d>,
<MX7D_PAD_EPDC_DATA09__UART6_DCE_TX 0x75>,
<MX7D_PAD_EPDC_DATA11__UART6_DCE_CTS 0x75>,
<MX7D_PAD_EPDC_DATA10__UART6_DCE_RTS 0x7d>;
};
pinctrl_uart7: uart7grp {
fsl,pins = <
MX7D_PAD_EPDC_DATA12__UART7_DCE_RX 0x7e
MX7D_PAD_EPDC_DATA13__UART7_DCE_TX 0x76
MX7D_PAD_EPDC_DATA15__UART7_DCE_CTS 0x76
fsl,pins =
<MX7D_PAD_EPDC_DATA12__UART7_DCE_RX 0x7e>,
<MX7D_PAD_EPDC_DATA13__UART7_DCE_TX 0x76>,
<MX7D_PAD_EPDC_DATA15__UART7_DCE_CTS 0x76>,
/* Limitation: RTS is not connected */
MX7D_PAD_EPDC_DATA14__UART7_DCE_RTS 0x7e
>;
<MX7D_PAD_EPDC_DATA14__UART7_DCE_RTS 0x7e>;
};
pinctrl_usdhc1_gpio: usdhc1grp_gpio {
fsl,pins = <
pinctrl_usdhc1_gpio: usdhc1_gpiogrp {
fsl,pins =
/* WP */
MX7D_PAD_SD1_WP__GPIO5_IO1 0x7c
<MX7D_PAD_SD1_WP__GPIO5_IO1 0x7c>,
/* CD */
MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x7c
<MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x7c>,
/* VSELECT */
MX7D_PAD_GPIO1_IO08__SD1_VSELECT 0x59
>;
<MX7D_PAD_GPIO1_IO08__SD1_VSELECT 0x59>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX7D_PAD_SD1_CMD__SD1_CMD 0x5e
MX7D_PAD_SD1_CLK__SD1_CLK 0x57
MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5e
MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5e
MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5e
MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5e
>;
fsl,pins =
<MX7D_PAD_SD1_CMD__SD1_CMD 0x5e>,
<MX7D_PAD_SD1_CLK__SD1_CLK 0x57>,
<MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5e>,
<MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5e>,
<MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5e>,
<MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5e>;
};
pinctrl_usdhc1_100mhz: usdhc1grp_100mhz {
fsl,pins = <
MX7D_PAD_SD1_CMD__SD1_CMD 0x5a
MX7D_PAD_SD1_CLK__SD1_CLK 0x57
MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a
MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a
MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a
MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a
>;
pinctrl_usdhc1_100mhz: usdhc1_100mhzgrp {
fsl,pins =
<MX7D_PAD_SD1_CMD__SD1_CMD 0x5a>,
<MX7D_PAD_SD1_CLK__SD1_CLK 0x57>,
<MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a>,
<MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a>,
<MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a>,
<MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a>;
};
pinctrl_usdhc1_200mhz: usdhc1grp_200mhz {
fsl,pins = <
MX7D_PAD_SD1_CMD__SD1_CMD 0x5b
MX7D_PAD_SD1_CLK__SD1_CLK 0x57
MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5b
MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5b
MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5b
MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5b
>;
pinctrl_usdhc1_200mhz: usdhc1_200mhzgrp {
fsl,pins =
<MX7D_PAD_SD1_CMD__SD1_CMD 0x5b>,
<MX7D_PAD_SD1_CLK__SD1_CLK 0x57>,
<MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5b>,
<MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5b>,
<MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5b>,
<MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5b>;
};
};
&iomuxc_lpsr {
pinctrl_pwm1: pwm1grp {
fsl,pins = <
fsl,pins =
/* LCD_CONTRAST */
MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x50
>;
<MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x50>;
};
pinctrl_usbotg1: usbotg1grp {
fsl,pins = <
MX7D_PAD_LPSR_GPIO1_IO04__USB_OTG1_OC 0x5c
MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x59
>;
fsl,pins =
<MX7D_PAD_LPSR_GPIO1_IO04__USB_OTG1_OC 0x5c>,
<MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x59>;
};
pinctrl_wdog1: wdog1grp {
fsl,pins = <
MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x30
>;
fsl,pins =
<MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x30>;
};
};
@ -560,6 +590,10 @@
status = "okay";
};
&snvs_pwrkey {
status = "okay";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
@ -605,6 +639,7 @@
};
&usbh {
disable-over-current;
status = "okay";
};
@ -630,6 +665,8 @@
vmmc-supply = <&reg_sd1_vmmc>;
bus-width = <4>;
no-1-8-v;
no-sdio;
no-emmc;
status = "okay";
};

144
arch/arm/boot/dts/nxp/imx/imx7-tqma7.dtsi
View File

@ -30,8 +30,11 @@
};
&i2c1 {
pinctrl-names = "default";
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1>;
pinctrl-1 = <&pinctrl_i2c1_recovery>;
scl-gpios = <&gpio4 8 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio4 9 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
clock-frequency = <100000>;
status = "okay";
@ -109,7 +112,7 @@
};
vgen4_reg: v33 {
regulator-min-microvolt = <2850000>;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
@ -135,7 +138,7 @@
};
/* NXP SE97BTP with temperature sensor + eeprom, TQMa7x 02xx */
se97b: temperature-sensor-eeprom@1e {
se97b: temperature-sensor@1e {
compatible = "nxp,se97b", "jedec,jc-42.4-temp";
reg = <0x1e>;
};
@ -143,15 +146,18 @@
/* ST M24C64 */
m24c64: eeprom@50 {
compatible = "atmel,24c64";
read-only;
reg = <0x50>;
pagesize = <32>;
vcc-supply = <&vgen4_reg>;
status = "okay";
};
at24c02: eeprom@56 {
compatible = "atmel,24c02";
compatible = "nxp,se97b", "atmel,24c02";
reg = <0x56>;
pagesize = <16>;
vcc-supply = <&vgen4_reg>;
status = "okay";
};
@ -163,91 +169,89 @@
&iomuxc {
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX7D_PAD_I2C1_SDA__I2C1_SDA 0x40000078
MX7D_PAD_I2C1_SCL__I2C1_SCL 0x40000078
>;
fsl,pins =
<MX7D_PAD_I2C1_SDA__I2C1_SDA 0x40000078>,
<MX7D_PAD_I2C1_SCL__I2C1_SCL 0x40000078>;
};
pinctrl_i2c1_recovery: i2c1recoverygrp {
fsl,pins =
<MX7D_PAD_I2C1_SDA__GPIO4_IO9 0x40000078>,
<MX7D_PAD_I2C1_SCL__GPIO4_IO8 0x40000078>;
};
pinctrl_pmic1: pmic1grp {
fsl,pins = <
MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x4000005C
>;
fsl,pins =
<MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x4000005C>;
};
pinctrl_qspi: qspigrp {
fsl,pins = <
MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 0x5A
MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1 0x5A
MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2 0x5A
MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3 0x5A
MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK 0x11
MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B 0x54
MX7D_PAD_EPDC_DATA07__QSPI_A_SS1_B 0x54
>;
fsl,pins =
<MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 0x5A>,
<MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1 0x5A>,
<MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2 0x5A>,
<MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3 0x5A>,
<MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK 0x11>,
<MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B 0x54>,
<MX7D_PAD_EPDC_DATA07__QSPI_A_SS1_B 0x54>;
};
pinctrl_qspi_reset: qspi_resetgrp {
fsl,pins = <
fsl,pins =
/* #QSPI_RESET */
MX7D_PAD_EPDC_DATA04__GPIO2_IO4 0x52
>;
<MX7D_PAD_EPDC_DATA04__GPIO2_IO4 0x52>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX7D_PAD_SD3_CMD__SD3_CMD 0x59
MX7D_PAD_SD3_CLK__SD3_CLK 0x56
MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59
MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59
MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59
MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59
MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59
MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59
MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59
MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59
MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19
>;
fsl,pins =
<MX7D_PAD_SD3_CMD__SD3_CMD 0x59>,
<MX7D_PAD_SD3_CLK__SD3_CLK 0x56>,
<MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59>,
<MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59>,
<MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59>,
<MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59>,
<MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59>,
<MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59>,
<MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59>,
<MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59>,
<MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19>;
};
pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
fsl,pins = <
MX7D_PAD_SD3_CMD__SD3_CMD 0x5a
MX7D_PAD_SD3_CLK__SD3_CLK 0x51
MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a
MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a
MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a
MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a
MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a
MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a
MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a
MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a
MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1a
>;
pinctrl_usdhc3_100mhz: usdhc3_100mhzgrp {
fsl,pins =
<MX7D_PAD_SD3_CMD__SD3_CMD 0x5a>,
<MX7D_PAD_SD3_CLK__SD3_CLK 0x51>,
<MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a>,
<MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a>,
<MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a>,
<MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a>,
<MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a>,
<MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a>,
<MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a>,
<MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a>,
<MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1a>;
};
pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
fsl,pins = <
MX7D_PAD_SD3_CMD__SD3_CMD 0x5b
MX7D_PAD_SD3_CLK__SD3_CLK 0x51
MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b
MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b
MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b
MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b
MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b
MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b
MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b
MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b
MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1b
>;
pinctrl_usdhc3_200mhz: usdhc3_200mhzgrp {
fsl,pins =
<MX7D_PAD_SD3_CMD__SD3_CMD 0x5b>,
<MX7D_PAD_SD3_CLK__SD3_CLK 0x51>,
<MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b>,
<MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b>,
<MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b>,
<MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b>,
<MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b>,
<MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b>,
<MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b>,
<MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b>,
<MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1b>;
};
};
&iomuxc_lpsr {
pinctrl_wdog1: wdog1grp {
fsl,pins = <
MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x30
>;
fsl,pins =
<MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x30>;
};
};
@ -265,10 +269,6 @@
};
};
&sdma {
status = "okay";
};
&usdhc3 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc3>;
@ -278,6 +278,8 @@
assigned-clock-rates = <400000000>;
bus-width = <8>;
non-removable;
no-sd;
no-sdio;
vmmc-supply = <&vgen4_reg>;
vqmmc-supply = <&sw2_reg>;
status = "okay";

94
arch/arm/boot/dts/nxp/imx/imx7d-mba7.dts
View File

@ -21,8 +21,6 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet2>;
phy-mode = "rgmii-id";
phy-reset-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>;
phy-reset-duration = <1>;
phy-supply = <&reg_fec2_pwdn>;
phy-handle = <&ethphy2_0>;
fsl,magic-packet;
@ -35,59 +33,85 @@
ethphy2_0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet2_phy>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
reset-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>;
reset-assert-us = <1000>;
reset-deassert-us = <500>;
};
};
};
&gpio2 {
pcie-dis-hog {
gpio-hog;
gpios = <29 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "pcie-dis";
};
pcie-rst-hog {
gpio-hog;
gpios = <12 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "pcie-rst";
};
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog_mba7_1>;
pinctrl-0 = <&pinctrl_hog_mba7_1>, <&pinctrl_hog_pcie>;
pinctrl_enet2: enet2grp {
fsl,pins = <
MX7D_PAD_SD2_CD_B__ENET2_MDIO 0x02
MX7D_PAD_SD2_WP__ENET2_MDC 0x00
MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x71
MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x71
MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x71
MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x71
MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x71
MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x71
MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x79
MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x79
MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x79
MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x79
MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x79
MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x79
fsl,pins =
<MX7D_PAD_SD2_CD_B__ENET2_MDIO 0x02>,
<MX7D_PAD_SD2_WP__ENET2_MDC 0x00>,
<MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x71>,
<MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x71>,
<MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x71>,
<MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x71>,
<MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x71>,
<MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x71>,
<MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x79>,
<MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x79>,
<MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x79>,
<MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x79>,
<MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x79>,
<MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x79>;
};
pinctrl_enet2_phy: enet2phygrp {
fsl,pins =
/* Reset: SION, 100kPU, SRE_FAST, DSE_X1 */
MX7D_PAD_EPDC_BDR0__GPIO2_IO28 0x40000070
<MX7D_PAD_EPDC_BDR0__GPIO2_IO28 0x40000070>,
/* INT/PWDN: SION, 100kPU, HYS, SRE_FAST, DSE_X1 */
MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 0x40000078
>;
<MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 0x40000078>;
};
pinctrl_hog_pcie: hogpciegrp {
fsl,pins =
/* #pcie_rst */
<MX7D_PAD_SD2_CLK__GPIO5_IO12 0x70>,
/* #pcie_dis */
<MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x70>;
};
pinctrl_pcie: pciegrp {
fsl,pins = <
fsl,pins =
/* #pcie_wake */
MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 0x70
/* #pcie_rst */
MX7D_PAD_SD2_CLK__GPIO5_IO12 0x70
/* #pcie_dis */
MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x70
>;
<MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 0x70>;
};
};
&iomuxc_lpsr {
pinctrl_usbotg2: usbotg2grp {
fsl,pins = <
MX7D_PAD_LPSR_GPIO1_IO06__USB_OTG2_OC 0x5c
MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x59
>;
fsl,pins =
<MX7D_PAD_LPSR_GPIO1_IO06__USB_OTG2_OC 0x5c>,
<MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x59>;
};
};
@ -98,16 +122,14 @@
/* probe deferral not supported */
/* pcie-bus-supply = <&reg_mpcie_1v5>; */
reset-gpio = <&gpio5 12 GPIO_ACTIVE_LOW>;
status = "okay";
status = "disabled";
};
&usbotg2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg2>;
vbus-supply = <&reg_usb_otg2_vbus>;
srp-disable;
hnp-disable;
adp-disable;
disable-over-current;
dr_mode = "host";
status = "okay";
};

1
arch/arm/boot/dts/nxp/ls/ls1021a.dtsi
View File

@ -808,6 +808,7 @@
dr_mode = "host";
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
usb3-lpm-capable;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
};

2
arch/arm/boot/dts/nxp/mxs/imx28-evk.dts
View File

@ -198,7 +198,7 @@
clocks = <&saif0>;
};
at24@51 {
eeprom@51 {
compatible = "atmel,24c32";
pagesize = <32>;
reg = <0x51>;