dt-bindings: gpio: Convert Broadcom STB GPIO to YAML
Convert the Broadcom STB GPIO Device Tree binding to YAML to help with validation. Acked-by: Gregory Fong <gregory.0xf0@gmail.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Acked-by: Bartosz Golaszewski <brgl@bgdev.pl> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20211208003727.3596577-6-f.fainelli@gmail.com Signed-off-by: Rob Herring <robh@kernel.org>
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Florian Fainelli
Rob Herring
parent
7c41161b51
commit
a6564a5538
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Broadcom STB "UPG GIO" GPIO controller
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The controller's registers are organized as sets of eight 32-bit
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registers with each set controlling a bank of up to 32 pins. A single
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interrupt is shared for all of the banks handled by the controller.
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Required properties:
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- compatible:
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Must be "brcm,brcmstb-gpio"
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- reg:
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Define the base and range of the I/O address space containing
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the brcmstb GPIO controller registers
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- #gpio-cells:
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Should be <2>. The first cell is the pin number (within the controller's
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pin space), and the second is used for the following:
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bit[0]: polarity (0 for active-high, 1 for active-low)
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- gpio-controller:
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Specifies that the node is a GPIO controller.
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- brcm,gpio-bank-widths:
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Number of GPIO lines for each bank. Number of elements must
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correspond to number of banks suggested by the 'reg' property.
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Optional properties:
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- interrupts:
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The interrupt shared by all GPIO lines for this controller.
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- interrupts-extended:
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Alternate form of specifying interrupts and parents that allows for
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multiple parents. This takes precedence over 'interrupts' and
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'interrupt-parent'. Wakeup-capable GPIO controllers often route their
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wakeup interrupt lines through a different interrupt controller than the
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primary interrupt line, making this property necessary.
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- #interrupt-cells:
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Should be <2>. The first cell is the GPIO number, the second should specify
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flags. The following subset of flags is supported:
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- bits[3:0] trigger type and level flags
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1 = low-to-high edge triggered
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2 = high-to-low edge triggered
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4 = active high level-sensitive
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8 = active low level-sensitive
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Valid combinations are 1, 2, 3, 4, 8.
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See also Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
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- interrupt-controller:
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Marks the device node as an interrupt controller
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- wakeup-source:
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GPIOs for this controller can be used as a wakeup source
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Example:
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upg_gio: gpio@f040a700 {
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#gpio-cells = <2>;
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#interrupt-cells = <2>;
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compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio";
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gpio-controller;
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interrupt-controller;
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reg = <0xf040a700 0x80>;
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interrupt-parent = <&irq0_intc>;
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interrupts = <0x6>;
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brcm,gpio-bank-widths = <32 32 32 24>;
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};
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upg_gio_aon: gpio@f04172c0 {
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#gpio-cells = <2>;
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#interrupt-cells = <2>;
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compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio";
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gpio-controller;
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interrupt-controller;
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reg = <0xf04172c0 0x40>;
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interrupt-parent = <&irq0_aon_intc>;
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interrupts = <0x6>;
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interrupts-extended = <&irq0_aon_intc 0x6>,
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<&aon_pm_l2_intc 0x5>;
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wakeup-source;
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brcm,gpio-bank-widths = <18 4>;
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};
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104
Documentation/devicetree/bindings/gpio/brcm,brcmstb-gpio.yaml
Normal file
104
Documentation/devicetree/bindings/gpio/brcm,brcmstb-gpio.yaml
Normal file
@ -0,0 +1,104 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/gpio/brcm,brcmstb-gpio.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Broadcom STB "UPG GIO" GPIO controller
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description: >
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The controller's registers are organized as sets of eight 32-bit
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registers with each set controlling a bank of up to 32 pins. A single
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interrupt is shared for all of the banks handled by the controller.
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maintainers:
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- Doug Berger <opendmb@gmail.com>
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- Florian Fainelli <f.fainelli@gmail.com>
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properties:
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compatible:
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items:
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- enum:
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- brcm,bcm7445-gpio
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- const: brcm,brcmstb-gpio
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reg:
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maxItems: 1
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description: >
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Define the base and range of the I/O address space containing
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the brcmstb GPIO controller registers
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"#gpio-cells":
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const: 2
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description: >
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The first cell is the pin number (within the controller's
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pin space), and the second is used for the following:
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bit[0]: polarity (0 for active-high, 1 for active-low)
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gpio-controller: true
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brcm,gpio-bank-widths:
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$ref: /schemas/types.yaml#/definitions/uint32-array
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description: >
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Number of GPIO lines for each bank. Number of elements must
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correspond to number of banks suggested by the 'reg' property.
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interrupts:
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maxItems: 1
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description: >
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The interrupt shared by all GPIO lines for this controller.
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"#interrupt-cells":
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const: 2
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description: |
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The first cell is the GPIO number, the second should specify
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flags. The following subset of flags is supported:
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- bits[3:0] trigger type and level flags
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1 = low-to-high edge triggered
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2 = high-to-low edge triggered
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4 = active high level-sensitive
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8 = active low level-sensitive
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Valid combinations are 1, 2, 3, 4, 8.
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interrupt-controller: true
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wakeup-source:
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type: boolean
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description: >
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GPIOs for this controller can be used as a wakeup source
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required:
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- compatible
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- reg
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- gpio-controller
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- "#gpio-cells"
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- "brcm,gpio-bank-widths"
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additionalProperties: false
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examples:
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- |
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upg_gio: gpio@f040a700 {
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#gpio-cells = <2>;
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#interrupt-cells = <2>;
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compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio";
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gpio-controller;
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interrupt-controller;
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reg = <0xf040a700 0x80>;
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interrupt-parent = <&irq0_intc>;
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interrupts = <0x6>;
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brcm,gpio-bank-widths = <32 32 32 24>;
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};
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upg_gio_aon: gpio@f04172c0 {
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#gpio-cells = <2>;
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#interrupt-cells = <2>;
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compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio";
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gpio-controller;
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interrupt-controller;
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reg = <0xf04172c0 0x40>;
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interrupt-parent = <&irq0_aon_intc>;
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interrupts = <0x6>;
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wakeup-source;
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brcm,gpio-bank-widths = <18 4>;
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};
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@ -3761,7 +3761,7 @@ BROADCOM BRCMSTB GPIO DRIVER
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M: Gregory Fong <gregory.0xf0@gmail.com>
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L: bcm-kernel-feedback-list@broadcom.com
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S: Supported
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F: Documentation/devicetree/bindings/gpio/brcm,brcmstb-gpio.txt
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F: Documentation/devicetree/bindings/gpio/brcm,brcmstb-gpio.yaml
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F: drivers/gpio/gpio-brcmstb.c
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BROADCOM BRCMSTB I2C DRIVER
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