KVM: arm64: Refactor CPACR trap bit setting/clearing to use ELx format
When setting/clearing CPACR bits for EL0 and EL1, use the ELx format of the bits, which covers both. This makes the code clearer, and reduces the chances of accidentally missing a bit. No functional change intended. Reviewed-by: Oliver Upton <oliver.upton@linux.dev> Signed-off-by: Fuad Tabba <tabba@google.com> Link: https://lore.kernel.org/r/20240603122852.3923848-9-tabba@google.com Signed-off-by: Marc Zyngier <maz@kernel.org>
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@ -146,7 +146,7 @@
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/* Coprocessor traps */
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.macro __init_el2_cptr
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__check_hvhe .LnVHE_\@, x1
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mov x0, #(CPACR_EL1_FPEN_EL1EN | CPACR_EL1_FPEN_EL0EN)
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mov x0, #CPACR_ELx_FPEN
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msr cpacr_el1, x0
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b .Lskip_set_cptr_\@
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.LnVHE_\@:
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@ -277,7 +277,7 @@
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// (h)VHE case
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mrs x0, cpacr_el1 // Disable SVE traps
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orr x0, x0, #(CPACR_EL1_ZEN_EL1EN | CPACR_EL1_ZEN_EL0EN)
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orr x0, x0, #CPACR_ELx_ZEN
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msr cpacr_el1, x0
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b .Lskip_set_cptr_\@
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@ -298,7 +298,7 @@
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// (h)VHE case
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mrs x0, cpacr_el1 // Disable SME traps
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orr x0, x0, #(CPACR_EL1_SMEN_EL0EN | CPACR_EL1_SMEN_EL1EN)
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orr x0, x0, #CPACR_ELx_SMEN
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msr cpacr_el1, x0
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b .Lskip_set_cptr_sme_\@
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@ -632,17 +632,16 @@ static __always_inline u64 kvm_get_reset_cptr_el2(struct kvm_vcpu *vcpu)
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u64 val;
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if (has_vhe()) {
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val = (CPACR_EL1_FPEN_EL0EN | CPACR_EL1_FPEN_EL1EN |
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CPACR_EL1_ZEN_EL1EN);
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val = (CPACR_ELx_FPEN | CPACR_EL1_ZEN_EL1EN);
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if (cpus_have_final_cap(ARM64_SME))
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val |= CPACR_EL1_SMEN_EL1EN;
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} else if (has_hvhe()) {
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val = (CPACR_EL1_FPEN_EL0EN | CPACR_EL1_FPEN_EL1EN);
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val = CPACR_ELx_FPEN;
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if (!vcpu_has_sve(vcpu) || !guest_owns_fp_regs())
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val |= CPACR_EL1_ZEN_EL1EN | CPACR_EL1_ZEN_EL0EN;
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val |= CPACR_ELx_ZEN;
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if (cpus_have_final_cap(ARM64_SME))
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val |= CPACR_EL1_SMEN_EL1EN | CPACR_EL1_SMEN_EL0EN;
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val |= CPACR_ELx_SMEN;
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} else {
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val = CPTR_NVHE_EL2_RES1;
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@ -161,9 +161,7 @@ void kvm_arch_vcpu_put_fp(struct kvm_vcpu *vcpu)
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if (has_vhe() && system_supports_sme()) {
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/* Also restore EL0 state seen on entry */
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if (vcpu_get_flag(vcpu, HOST_SME_ENABLED))
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sysreg_clear_set(CPACR_EL1, 0,
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CPACR_EL1_SMEN_EL0EN |
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CPACR_EL1_SMEN_EL1EN);
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sysreg_clear_set(CPACR_EL1, 0, CPACR_ELx_SMEN);
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else
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sysreg_clear_set(CPACR_EL1,
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CPACR_EL1_SMEN_EL0EN,
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@ -65,7 +65,7 @@ static void pvm_init_traps_aa64pfr0(struct kvm_vcpu *vcpu)
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/* Trap SVE */
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if (!FIELD_GET(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_SVE), feature_ids)) {
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if (has_hvhe())
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cptr_clear |= CPACR_EL1_ZEN_EL0EN | CPACR_EL1_ZEN_EL1EN;
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cptr_clear |= CPACR_ELx_ZEN;
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else
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cptr_set |= CPTR_EL2_TZ;
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}
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@ -48,15 +48,14 @@ static void __activate_traps(struct kvm_vcpu *vcpu)
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val |= has_hvhe() ? CPACR_EL1_TTA : CPTR_EL2_TTA;
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if (cpus_have_final_cap(ARM64_SME)) {
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if (has_hvhe())
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val &= ~(CPACR_EL1_SMEN_EL1EN | CPACR_EL1_SMEN_EL0EN);
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val &= ~CPACR_ELx_SMEN;
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else
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val |= CPTR_EL2_TSM;
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}
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if (!guest_owns_fp_regs()) {
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if (has_hvhe())
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val &= ~(CPACR_EL1_FPEN_EL0EN | CPACR_EL1_FPEN_EL1EN |
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CPACR_EL1_ZEN_EL0EN | CPACR_EL1_ZEN_EL1EN);
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val &= ~(CPACR_ELx_FPEN | CPACR_ELx_ZEN);
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else
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val |= CPTR_EL2_TFP | CPTR_EL2_TZ;
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@ -93,8 +93,7 @@ static void __activate_traps(struct kvm_vcpu *vcpu)
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val = read_sysreg(cpacr_el1);
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val |= CPACR_ELx_TTA;
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val &= ~(CPACR_EL1_ZEN_EL0EN | CPACR_EL1_ZEN_EL1EN |
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CPACR_EL1_SMEN_EL0EN | CPACR_EL1_SMEN_EL1EN);
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val &= ~(CPACR_ELx_ZEN | CPACR_ELx_SMEN);
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/*
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* With VHE (HCR.E2H == 1), accesses to CPACR_EL1 are routed to
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@ -109,9 +108,9 @@ static void __activate_traps(struct kvm_vcpu *vcpu)
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if (guest_owns_fp_regs()) {
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if (vcpu_has_sve(vcpu))
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val |= CPACR_EL1_ZEN_EL0EN | CPACR_EL1_ZEN_EL1EN;
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val |= CPACR_ELx_ZEN;
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} else {
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val &= ~(CPACR_EL1_FPEN_EL0EN | CPACR_EL1_FPEN_EL1EN);
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val &= ~CPACR_ELx_FPEN;
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__activate_traps_fpsimd32(vcpu);
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}
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