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ARM: SoC fixes for v6.7

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Most of the changes are devicetree fixes for NXP, Mediatek, Rockchips
 Arm machines as well as Microchip RISC-V, and most of these address
 build-time warnings for spec violations and other minor issues. One of
 the Mediatek warnings was enabled by default and prevented a clean build.
 The ones that address serious runtime issues are all on the i.MX platform:
 
  - a boot time panic on imx8qm
  - USB hanging under load on imx8
  - regressions on the imx93 ethernet phy
 
 Code fixes include a minor error handling for the i.MX PMU driver, and
 a number of firmware driver fixes:
 
  - OP-TEE fix for supplicant based device enumeration, and a new
    sysfs attribute to needed to fix a race against userspace
 
  - Arm SCMI fix for possible truncation/overflow in the frequency
    computations
 
  - Multiple FF-A fixes for the newly added notification support.
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Merge tag 'soc-fixes-6.7-1' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull ARM SoC fixes from Arnd Bergmann:
 "Most of the changes are devicetree fixes for NXP, Mediatek, Rockchips
  Arm machines as well as Microchip RISC-V, and most of these address
  build-time warnings for spec violations and other minor issues. One of
  the Mediatek warnings was enabled by default and prevented a clean
  build.

  The ones that address serious runtime issues are all on the i.MX
  platform:

   - a boot time panic on imx8qm

   - USB hanging under load on imx8

   - regressions on the imx93 ethernet phy

  Code fixes include a minor error handling for the i.MX PMU driver, and
  a number of firmware driver fixes:

   - OP-TEE fix for supplicant based device enumeration, and a new sysfs
     attribute to needed to fix a race against userspace

   - Arm SCMI fix for possible truncation/overflow in the frequency
     computations

   - Multiple FF-A fixes for the newly added notification support"

* tag 'soc-fixes-6.7-1' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (55 commits)
  MAINTAINERS: change the S32G2 maintainer's email address.
  arm64: dts: rockchip: Fix eMMC Data Strobe PD on rk3588
  ARM: dts: imx28-xea: Pass the 'model' property
  ARM: dts: imx7: Declare timers compatible with fsl,imx6dl-gpt
  MAINTAINERS: reinstate freescale ARM64 DT directory in i.MX entry
  arm64: dts: imx8-apalis: set wifi regulator to always-on
  ARM: imx: Check return value of devm_kasprintf in imx_mmdc_perf_init
  arm64: dts: imx8ulp: update gpio node name to align with register address
  arm64: dts: imx93: update gpio node name to align with register address
  arm64: dts: imx93: correct mediamix power
  arm64: dts: imx8qm: Add imx8qm's own pm to avoid panic during startup
  arm64: dts: freescale: imx8-ss-dma: Fix #pwm-cells
  arm64: dts: freescale: imx8-ss-lsio: Fix #pwm-cells
  dt-bindings: pwm: imx-pwm: Unify #pwm-cells for all compatibles
  ARM: dts: imx6ul-pico: Describe the Ethernet PHY clock
  arm64: dts: imx8mp: imx8mq: Add parkmode-disable-ss-quirk on DWC3
  arm64: dts: rockchip: Fix PCI node addresses on rk3399-gru
  arm64: dts: rockchip: drop interrupt-names property from rk3588s dfi
  firmware: arm_scmi: Fix possible frequency truncation when using level indexing mode
  firmware: arm_scmi: Fix frequency truncation by promoting multiplier type
  ...
This commit is contained in:
Linus Torvalds 2023-12-08 08:58:39 -08:00
commit a6adef8987
55 changed files with 396 additions and 328 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
Documentation/ABI/testing/sysfs-bus-optee-devices
View File

@ -6,3 +6,12 @@ Description:
OP-TEE bus provides reference to registered drivers under this directory. The <uuid>
matches Trusted Application (TA) driver and corresponding TA in secure OS. Drivers
are free to create needed API under optee-ta-<uuid> directory.
What: /sys/bus/tee/devices/optee-ta-<uuid>/need_supplicant
Date: November 2023
KernelVersion: 6.7
Contact: op-tee@lists.trustedfirmware.org
Description:
Allows to distinguish whether an OP-TEE based TA/device requires user-space
tee-supplicant to function properly or not. This attribute will be present for
devices which depend on tee-supplicant to be running.

10
Documentation/devicetree/bindings/pwm/imx-pwm.yaml
View File

@ -14,12 +14,10 @@ allOf:
properties:
"#pwm-cells":
description: |
Should be 2 for i.MX1 and 3 for i.MX27 and newer SoCs. See pwm.yaml
in this directory for a description of the cells format.
enum:
- 2
- 3
description:
The only third cell flag supported by this binding is
PWM_POLARITY_INVERTED. fsl,imx1-pwm does not support this flags.
const: 3
compatible:
oneOf:

1
Documentation/devicetree/bindings/soc/rockchip/grf.yaml
View File

@ -233,6 +233,7 @@ allOf:
- rockchip,rk3399-grf
- rockchip,rk3399-pmugrf
- rockchip,rk3568-pmugrf
- rockchip,rk3588-pmugrf
- rockchip,rv1108-grf
- rockchip,rv1108-pmugrf

3
MAINTAINERS
View File

@ -2143,6 +2143,7 @@ S: Maintained
T: git git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git
F: arch/arm/boot/dts/nxp/imx/
F: arch/arm/boot/dts/nxp/mxs/
F: arch/arm64/boot/dts/freescale/
X: arch/arm64/boot/dts/freescale/fsl-*
X: arch/arm64/boot/dts/freescale/qoriq-*
X: drivers/media/i2c/
@ -2523,7 +2524,7 @@ F: drivers/*/*/*wpcm*
F: drivers/*/*wpcm*
ARM/NXP S32G ARCHITECTURE
M: Chester Lin <clin@suse.com>
M: Chester Lin <chester62515@gmail.com>
R: Andreas Färber <afaerber@suse.de>
R: Matthias Brugger <mbrugger@suse.com>
R: NXP S32 Linux Team <s32@nxp.com>

4
arch/arm/boot/dts/broadcom/bcm2711-rpi-400.dts
View File

@ -36,9 +36,7 @@
gpios = <&gpio 42 GPIO_ACTIVE_HIGH>;
};
&leds {
/delete-node/ led_act;
};
/delete-node/ &led_act;
&pm {
/delete-property/ system-power-controller;

4
arch/arm/boot/dts/nxp/imx/imx6q-skov-reve-mi1010ait-1cp1.dts
View File

@ -37,9 +37,9 @@
&clks {
assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
<&clks IMX6QDL_CLK_LDB_DI1_SEL>;
<&clks IMX6QDL_CLK_LDB_DI1_SEL>, <&clks IMX6QDL_CLK_ENET_REF_SEL>;
assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
<&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>;
<&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>, <&clk50m_phy>;
};
&hdmi {

2
arch/arm/boot/dts/nxp/imx/imx6ul-pico.dtsi
View File

@ -121,6 +121,8 @@
max-speed = <100>;
interrupt-parent = <&gpio5>;
interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
clocks = <&clks IMX6UL_CLK_ENET_REF>;
clock-names = "rmii-ref";
};
};
};

8
arch/arm/boot/dts/nxp/imx/imx7s.dtsi
View File

@ -454,7 +454,7 @@
};
gpt1: timer@302d0000 {
compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
compatible = "fsl,imx7d-gpt", "fsl,imx6dl-gpt";
reg = <0x302d0000 0x10000>;
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7D_GPT1_ROOT_CLK>,
@ -463,7 +463,7 @@
};
gpt2: timer@302e0000 {
compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
compatible = "fsl,imx7d-gpt", "fsl,imx6dl-gpt";
reg = <0x302e0000 0x10000>;
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7D_GPT2_ROOT_CLK>,
@ -473,7 +473,7 @@
};
gpt3: timer@302f0000 {
compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
compatible = "fsl,imx7d-gpt", "fsl,imx6dl-gpt";
reg = <0x302f0000 0x10000>;
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7D_GPT3_ROOT_CLK>,
@ -483,7 +483,7 @@
};
gpt4: timer@30300000 {
compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
compatible = "fsl,imx7d-gpt", "fsl,imx6dl-gpt";
reg = <0x30300000 0x10000>;
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7D_GPT4_ROOT_CLK>,

1
arch/arm/boot/dts/nxp/mxs/imx28-xea.dts
View File

@ -8,6 +8,7 @@
#include "imx28-lwe.dtsi"
/ {
model = "Liebherr XEA board";
compatible = "lwn,imx28-xea", "fsl,imx28";
};

2
arch/arm/boot/dts/rockchip/rk3128.dtsi
View File

@ -848,7 +848,7 @@
};
sdmmc_pwren: sdmmc-pwren {
rockchip,pins = <1 RK_PB6 1 &pcfg_pull_default>;
rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_default>;
};
sdmmc_bus4: sdmmc-bus4 {

6
arch/arm/boot/dts/rockchip/rk322x.dtsi
View File

@ -215,9 +215,9 @@
power-domain@RK3228_PD_VOP {
reg = <RK3228_PD_VOP>;
clocks =<&cru ACLK_VOP>,
<&cru DCLK_VOP>,
<&cru HCLK_VOP>;
clocks = <&cru ACLK_VOP>,
<&cru DCLK_VOP>,
<&cru HCLK_VOP>;
pm_qos = <&qos_vop>;
#power-domain-cells = <0>;
};

7
arch/arm/mach-imx/mmdc.c
View File

@ -501,6 +501,10 @@ static int imx_mmdc_perf_init(struct platform_device *pdev, void __iomem *mmdc_b
name = devm_kasprintf(&pdev->dev,
GFP_KERNEL, "mmdc%d", ret);
if (!name) {
ret = -ENOMEM;
goto pmu_release_id;
}
pmu_mmdc->mmdc_ipg_clk = mmdc_ipg_clk;
pmu_mmdc->devtype_data = (struct fsl_mmdc_devtype_data *)of_id->data;
@ -523,9 +527,10 @@ static int imx_mmdc_perf_init(struct platform_device *pdev, void __iomem *mmdc_b
pmu_register_err:
pr_warn("MMDC Perf PMU failed (%d), disabled\n", ret);
ida_simple_remove(&mmdc_ida, pmu_mmdc->id);
cpuhp_state_remove_instance_nocalls(cpuhp_mmdc_state, &pmu_mmdc->node);
hrtimer_cancel(&pmu_mmdc->hrtimer);
pmu_release_id:
ida_simple_remove(&mmdc_ida, pmu_mmdc->id);
pmu_free:
kfree(pmu_mmdc);
return ret;

5
arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi
View File

@ -82,12 +82,9 @@
pinctrl-0 = <&pinctrl_wifi_pdn>;
gpio = <&lsio_gpio1 28 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-always-on;
regulator-name = "wifi_pwrdn_fake_regulator";
regulator-settling-time-us = <100>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
reg_pcie_switch: regulator-pcie-switch {

2
arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi
View File

@ -149,7 +149,7 @@ dma_subsys: bus@5a000000 {
clock-names = "ipg", "per";
assigned-clocks = <&clk IMX_SC_R_LCD_0_PWM_0 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <24000000>;
#pwm-cells = <2>;
#pwm-cells = <3>;
power-domains = <&pd IMX_SC_R_LCD_0_PWM_0>;
};

8
arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi
View File

@ -29,7 +29,7 @@ lsio_subsys: bus@5d000000 {
<&pwm0_lpcg 1>;
assigned-clocks = <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <24000000>;
#pwm-cells = <2>;
#pwm-cells = <3>;
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
@ -42,7 +42,7 @@ lsio_subsys: bus@5d000000 {
<&pwm1_lpcg 1>;
assigned-clocks = <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <24000000>;
#pwm-cells = <2>;
#pwm-cells = <3>;
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
@ -55,7 +55,7 @@ lsio_subsys: bus@5d000000 {
<&pwm2_lpcg 1>;
assigned-clocks = <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <24000000>;
#pwm-cells = <2>;
#pwm-cells = <3>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
@ -68,7 +68,7 @@ lsio_subsys: bus@5d000000 {
<&pwm3_lpcg 1>;
assigned-clocks = <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <24000000>;
#pwm-cells = <2>;
#pwm-cells = <3>;
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};

2
arch/arm64/boot/dts/freescale/imx8mp.dtsi
View File

@ -2072,6 +2072,7 @@
phys = <&usb3_phy0>, <&usb3_phy0>;
phy-names = "usb2-phy", "usb3-phy";
snps,gfladj-refclk-lpm-sel-quirk;
snps,parkmode-disable-ss-quirk;
};
};
@ -2114,6 +2115,7 @@
phys = <&usb3_phy1>, <&usb3_phy1>;
phy-names = "usb2-phy", "usb3-phy";
snps,gfladj-refclk-lpm-sel-quirk;
snps,parkmode-disable-ss-quirk;
};
};

2
arch/arm64/boot/dts/freescale/imx8mq.dtsi
View File

@ -1649,6 +1649,7 @@
phys = <&usb3_phy0>, <&usb3_phy0>;
phy-names = "usb2-phy", "usb3-phy";
power-domains = <&pgc_otg1>;
snps,parkmode-disable-ss-quirk;
status = "disabled";
};
@ -1680,6 +1681,7 @@
phys = <&usb3_phy1>, <&usb3_phy1>;
phy-names = "usb2-phy", "usb3-phy";
power-domains = <&pgc_otg2>;
snps,parkmode-disable-ss-quirk;
status = "disabled";
};

11
arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi
View File

@ -96,6 +96,17 @@
status = "okay";
};
&edma3 {
power-domains = <&pd IMX_SC_R_DMA_1_CH0>,
<&pd IMX_SC_R_DMA_1_CH1>,
<&pd IMX_SC_R_DMA_1_CH2>,
<&pd IMX_SC_R_DMA_1_CH3>,
<&pd IMX_SC_R_DMA_1_CH4>,
<&pd IMX_SC_R_DMA_1_CH5>,
<&pd IMX_SC_R_DMA_1_CH6>,
<&pd IMX_SC_R_DMA_1_CH7>;
};
&flexcan1 {
fsl,clk-source = /bits/ 8 <1>;
};

6
arch/arm64/boot/dts/freescale/imx8ulp.dtsi
View File

@ -483,7 +483,7 @@
};
};
gpioe: gpio@2d000080 {
gpioe: gpio@2d000000 {
compatible = "fsl,imx8ulp-gpio";
reg = <0x2d000000 0x1000>;
gpio-controller;
@ -498,7 +498,7 @@
gpio-ranges = <&iomuxc1 0 32 24>;
};
gpiof: gpio@2d010080 {
gpiof: gpio@2d010000 {
compatible = "fsl,imx8ulp-gpio";
reg = <0x2d010000 0x1000>;
gpio-controller;
@ -534,7 +534,7 @@
};
};
gpiod: gpio@2e200080 {
gpiod: gpio@2e200000 {
compatible = "fsl,imx8ulp-gpio";
reg = <0x2e200000 0x1000>;
gpio-controller;

2
arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla.dts
View File

@ -577,7 +577,7 @@
fsl,pins = <
MX93_PAD_UART2_TXD__LPUART2_TX 0x31e
MX93_PAD_UART2_RXD__LPUART2_RX 0x31e
MX93_PAD_SAI1_TXD0__LPUART2_RTS_B 0x31e
MX93_PAD_SAI1_TXD0__LPUART2_RTS_B 0x51e
>;
};

10
arch/arm64/boot/dts/freescale/imx93.dtsi
View File

@ -417,7 +417,7 @@
compatible = "fsl,imx93-src-slice";
reg = <0x44462400 0x400>, <0x44465800 0x400>;
#power-domain-cells = <0>;
clocks = <&clk IMX93_CLK_MEDIA_AXI>,
clocks = <&clk IMX93_CLK_NIC_MEDIA_GATE>,
<&clk IMX93_CLK_MEDIA_APB>;
};
};
@ -957,7 +957,7 @@
};
};
gpio2: gpio@43810080 {
gpio2: gpio@43810000 {
compatible = "fsl,imx93-gpio", "fsl,imx8ulp-gpio";
reg = <0x43810000 0x1000>;
gpio-controller;
@ -972,7 +972,7 @@
gpio-ranges = <&iomuxc 0 4 30>;
};
gpio3: gpio@43820080 {
gpio3: gpio@43820000 {
compatible = "fsl,imx93-gpio", "fsl,imx8ulp-gpio";
reg = <0x43820000 0x1000>;
gpio-controller;
@ -988,7 +988,7 @@
<&iomuxc 26 34 2>, <&iomuxc 28 0 4>;
};
gpio4: gpio@43830080 {
gpio4: gpio@43830000 {
compatible = "fsl,imx93-gpio", "fsl,imx8ulp-gpio";
reg = <0x43830000 0x1000>;
gpio-controller;
@ -1003,7 +1003,7 @@
gpio-ranges = <&iomuxc 0 38 28>, <&iomuxc 28 36 2>;
};
gpio1: gpio@47400080 {
gpio1: gpio@47400000 {
compatible = "fsl,imx93-gpio", "fsl,imx8ulp-gpio";
reg = <0x47400000 0x1000>;
gpio-controller;

2
arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
View File

@ -73,7 +73,7 @@
};
};
memory {
memory@40000000 {
reg = <0 0x40000000 0 0x40000000>;
};

2
arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
View File

@ -55,7 +55,7 @@
};
};
memory {
memory@40000000 {
reg = <0 0x40000000 0 0x20000000>;
};

12
arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
View File

@ -126,6 +126,7 @@
compatible = "sff,sfp";
i2c-bus = <&i2c_sfp1>;
los-gpios = <&pio 46 GPIO_ACTIVE_HIGH>;
maximum-power-milliwatt = <3000>;
mod-def0-gpios = <&pio 49 GPIO_ACTIVE_LOW>;
tx-disable-gpios = <&pio 20 GPIO_ACTIVE_HIGH>;
tx-fault-gpios = <&pio 7 GPIO_ACTIVE_HIGH>;
@ -137,6 +138,7 @@
i2c-bus = <&i2c_sfp2>;
los-gpios = <&pio 31 GPIO_ACTIVE_HIGH>;
mod-def0-gpios = <&pio 47 GPIO_ACTIVE_LOW>;
maximum-power-milliwatt = <3000>;
tx-disable-gpios = <&pio 15 GPIO_ACTIVE_HIGH>;
tx-fault-gpios = <&pio 48 GPIO_ACTIVE_HIGH>;
};
@ -150,16 +152,16 @@
trip = <&cpu_trip_active_high>;
};
cpu-active-low {
cpu-active-med {
/* active: set fan to cooling level 1 */
cooling-device = <&fan 1 1>;
trip = <&cpu_trip_active_low>;
trip = <&cpu_trip_active_med>;
};
cpu-passive {
/* passive: set fan to cooling level 0 */
cpu-active-low {
/* active: set fan to cooling level 0 */
cooling-device = <&fan 0 0>;
trip = <&cpu_trip_passive>;
trip = <&cpu_trip_active_low>;
};
};
};

24
arch/arm64/boot/dts/mediatek/mt7986a.dtsi
View File

@ -374,6 +374,10 @@
reg = <0 0x11230000 0 0x1000>,
<0 0x11c20000 0 0x1000>;
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
assigned-clocks = <&topckgen CLK_TOP_EMMC_416M_SEL>,
<&topckgen CLK_TOP_EMMC_250M_SEL>;
assigned-clock-parents = <&apmixedsys CLK_APMIXED_MPLL>,
<&topckgen CLK_TOP_NET1PLL_D5_D2>;
clocks = <&topckgen CLK_TOP_EMMC_416M_SEL>,
<&infracfg CLK_INFRA_MSDC_HCK_CK>,
<&infracfg CLK_INFRA_MSDC_CK>,
@ -610,22 +614,34 @@
thermal-sensors = <&thermal 0>;
trips {
cpu_trip_crit: crit {
temperature = <125000>;
hysteresis = <2000>;
type = "critical";
};
cpu_trip_hot: hot {
temperature = <120000>;
hysteresis = <2000>;
type = "hot";
};
cpu_trip_active_high: active-high {
temperature = <115000>;
hysteresis = <2000>;
type = "active";
};
cpu_trip_active_low: active-low {
cpu_trip_active_med: active-med {
temperature = <85000>;
hysteresis = <2000>;
type = "active";
};
cpu_trip_passive: passive {
temperature = <40000>;
cpu_trip_active_low: active-low {
temperature = <60000>;
hysteresis = <2000>;
type = "passive";
type = "active";
};
};
};

4
arch/arm64/boot/dts/mediatek/mt8173-evb.dts
View File

@ -44,7 +44,7 @@
id-gpio = <&pio 16 GPIO_ACTIVE_HIGH>;
};
usb_p1_vbus: regulator@0 {
usb_p1_vbus: regulator-usb-p1 {
compatible = "regulator-fixed";
regulator-name = "usb_vbus";
regulator-min-microvolt = <5000000>;
@ -53,7 +53,7 @@
enable-active-high;
};
usb_p0_vbus: regulator@1 {
usb_p0_vbus: regulator-usb-p0 {
compatible = "regulator-fixed";
regulator-name = "vbus";
regulator-min-microvolt = <5000000>;

4
arch/arm64/boot/dts/mediatek/mt8183-evb.dts
View File

@ -31,14 +31,14 @@
#address-cells = <2>;
#size-cells = <2>;
ranges;
scp_mem_reserved: scp_mem_region {
scp_mem_reserved: memory@50000000 {
compatible = "shared-dma-pool";
reg = <0 0x50000000 0 0x2900000>;
no-map;
};
};
ntc@0 {
thermal-sensor {
compatible = "murata,ncp03wf104";
pullup-uv = <1800000>;
pullup-ohm = <390000>;

8
arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi
View File

@ -91,6 +91,8 @@
&dsi0 {
status = "okay";
/delete-property/#size-cells;
/delete-property/#address-cells;
/delete-node/panel@0;
ports {
port {
@ -441,20 +443,20 @@
};
touchscreen_pins: touchscreen-pins {
touch_int_odl {
touch-int-odl {
pinmux = <PINMUX_GPIO155__FUNC_GPIO155>;
input-enable;
bias-pull-up;
};
touch_rst_l {
touch-rst-l {
pinmux = <PINMUX_GPIO156__FUNC_GPIO156>;
output-high;
};
};
trackpad_pins: trackpad-pins {
trackpad_int {
trackpad-int {
pinmux = <PINMUX_GPIO7__FUNC_GPIO7>;
input-enable;
bias-disable; /* pulled externally */

96
arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
View File

@ -116,7 +116,7 @@
#size-cells = <2>;
ranges;
scp_mem_reserved: scp_mem_region {
scp_mem_reserved: memory@50000000 {
compatible = "shared-dma-pool";
reg = <0 0x50000000 0 0x2900000>;
no-map;
@ -460,7 +460,7 @@
&pio {
aud_pins_default: audiopins {
pins_bus {
pins-bus {
pinmux = <PINMUX_GPIO97__FUNC_I2S2_MCK>,
<PINMUX_GPIO98__FUNC_I2S2_BCK>,
<PINMUX_GPIO101__FUNC_I2S2_LRCK>,
@ -482,7 +482,7 @@
};
aud_pins_tdm_out_on: audiotdmouton {
pins_bus {
pins-bus {
pinmux = <PINMUX_GPIO169__FUNC_TDM_BCK_2ND>,
<PINMUX_GPIO170__FUNC_TDM_LRCK_2ND>,
<PINMUX_GPIO171__FUNC_TDM_DATA0_2ND>,
@ -494,7 +494,7 @@
};
aud_pins_tdm_out_off: audiotdmoutoff {
pins_bus {
pins-bus {
pinmux = <PINMUX_GPIO169__FUNC_GPIO169>,
<PINMUX_GPIO170__FUNC_GPIO170>,
<PINMUX_GPIO171__FUNC_GPIO171>,
@ -508,13 +508,13 @@
};
bt_pins: bt-pins {
pins_bt_en {
pins-bt-en {
pinmux = <PINMUX_GPIO120__FUNC_GPIO120>;
output-low;
};
};
ec_ap_int_odl: ec_ap_int_odl {
ec_ap_int_odl: ec-ap-int-odl {
pins1 {
pinmux = <PINMUX_GPIO151__FUNC_GPIO151>;
input-enable;
@ -522,7 +522,7 @@
};
};
h1_int_od_l: h1_int_od_l {
h1_int_od_l: h1-int-od-l {
pins1 {
pinmux = <PINMUX_GPIO153__FUNC_GPIO153>;
input-enable;
@ -530,7 +530,7 @@
};
i2c0_pins: i2c0 {
pins_bus {
pins-bus {
pinmux = <PINMUX_GPIO82__FUNC_SDA0>,
<PINMUX_GPIO83__FUNC_SCL0>;
mediatek,pull-up-adv = <3>;
@ -539,7 +539,7 @@
};
i2c1_pins: i2c1 {
pins_bus {
pins-bus {
pinmux = <PINMUX_GPIO81__FUNC_SDA1>,
<PINMUX_GPIO84__FUNC_SCL1>;
mediatek,pull-up-adv = <3>;
@ -548,7 +548,7 @@
};
i2c2_pins: i2c2 {
pins_bus {
pins-bus {
pinmux = <PINMUX_GPIO103__FUNC_SCL2>,
<PINMUX_GPIO104__FUNC_SDA2>;
bias-disable;
@ -557,7 +557,7 @@
};
i2c3_pins: i2c3 {
pins_bus {
pins-bus {
pinmux = <PINMUX_GPIO50__FUNC_SCL3>,
<PINMUX_GPIO51__FUNC_SDA3>;
mediatek,pull-up-adv = <3>;
@ -566,7 +566,7 @@
};
i2c4_pins: i2c4 {
pins_bus {
pins-bus {
pinmux = <PINMUX_GPIO105__FUNC_SCL4>,
<PINMUX_GPIO106__FUNC_SDA4>;
bias-disable;
@ -575,7 +575,7 @@
};
i2c5_pins: i2c5 {
pins_bus {
pins-bus {
pinmux = <PINMUX_GPIO48__FUNC_SCL5>,
<PINMUX_GPIO49__FUNC_SDA5>;
mediatek,pull-up-adv = <3>;
@ -584,7 +584,7 @@
};
i2c6_pins: i2c6 {
pins_bus {
pins-bus {
pinmux = <PINMUX_GPIO11__FUNC_SCL6>,
<PINMUX_GPIO12__FUNC_SDA6>;
bias-disable;
@ -592,7 +592,7 @@
};
mmc0_pins_default: mmc0-pins-default {
pins_cmd_dat {
pins-cmd-dat {
pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>,
<PINMUX_GPIO128__FUNC_MSDC0_DAT1>,
<PINMUX_GPIO125__FUNC_MSDC0_DAT2>,
@ -607,13 +607,13 @@
mediatek,pull-up-adv = <01>;
};
pins_clk {
pins-clk {
pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>;
drive-strength = <MTK_DRIVE_14mA>;
mediatek,pull-down-adv = <10>;
};
pins_rst {
pins-rst {
pinmux = <PINMUX_GPIO133__FUNC_MSDC0_RSTB>;
drive-strength = <MTK_DRIVE_14mA>;
mediatek,pull-down-adv = <01>;
@ -621,7 +621,7 @@
};
mmc0_pins_uhs: mmc0-pins-uhs {
pins_cmd_dat {
pins-cmd-dat {
pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>,
<PINMUX_GPIO128__FUNC_MSDC0_DAT1>,
<PINMUX_GPIO125__FUNC_MSDC0_DAT2>,
@ -636,19 +636,19 @@
mediatek,pull-up-adv = <01>;
};
pins_clk {
pins-clk {
pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>;
drive-strength = <MTK_DRIVE_14mA>;
mediatek,pull-down-adv = <10>;
};
pins_ds {
pins-ds {
pinmux = <PINMUX_GPIO131__FUNC_MSDC0_DSL>;
drive-strength = <MTK_DRIVE_14mA>;
mediatek,pull-down-adv = <10>;
};
pins_rst {
pins-rst {
pinmux = <PINMUX_GPIO133__FUNC_MSDC0_RSTB>;
drive-strength = <MTK_DRIVE_14mA>;
mediatek,pull-up-adv = <01>;
@ -656,7 +656,7 @@
};
mmc1_pins_default: mmc1-pins-default {
pins_cmd_dat {
pins-cmd-dat {
pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>,
<PINMUX_GPIO32__FUNC_MSDC1_DAT0>,
<PINMUX_GPIO34__FUNC_MSDC1_DAT1>,
@ -666,7 +666,7 @@
mediatek,pull-up-adv = <10>;
};
pins_clk {
pins-clk {
pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>;
input-enable;
mediatek,pull-down-adv = <10>;
@ -674,7 +674,7 @@
};
mmc1_pins_uhs: mmc1-pins-uhs {
pins_cmd_dat {
pins-cmd-dat {
pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>,
<PINMUX_GPIO32__FUNC_MSDC1_DAT0>,
<PINMUX_GPIO34__FUNC_MSDC1_DAT1>,
@ -685,7 +685,7 @@
mediatek,pull-up-adv = <10>;
};
pins_clk {
pins-clk {
pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>;
drive-strength = <MTK_DRIVE_8mA>;
mediatek,pull-down-adv = <10>;
@ -693,15 +693,15 @@
};
};
panel_pins_default: panel_pins_default {
panel_reset {
panel_pins_default: panel-pins-default {
panel-reset {
pinmux = <PINMUX_GPIO45__FUNC_GPIO45>;
output-low;
bias-pull-up;
};
};
pwm0_pin_default: pwm0_pin_default {
pwm0_pin_default: pwm0-pin-default {
pins1 {
pinmux = <PINMUX_GPIO176__FUNC_GPIO176>;
output-high;
@ -713,14 +713,14 @@
};
scp_pins: scp {
pins_scp_uart {
pins-scp-uart {
pinmux = <PINMUX_GPIO110__FUNC_TP_URXD1_AO>,
<PINMUX_GPIO112__FUNC_TP_UTXD1_AO>;
};
};
spi0_pins: spi0 {
pins_spi {
pins-spi {
pinmux = <PINMUX_GPIO85__FUNC_SPI0_MI>,
<PINMUX_GPIO86__FUNC_GPIO86>,
<PINMUX_GPIO87__FUNC_SPI0_MO>,
@ -730,7 +730,7 @@
};
spi1_pins: spi1 {
pins_spi {
pins-spi {
pinmux = <PINMUX_GPIO161__FUNC_SPI1_A_MI>,
<PINMUX_GPIO162__FUNC_SPI1_A_CSB>,
<PINMUX_GPIO163__FUNC_SPI1_A_MO>,
@ -740,20 +740,20 @@
};
spi2_pins: spi2 {
pins_spi {
pins-spi {
pinmux = <PINMUX_GPIO0__FUNC_SPI2_CSB>,
<PINMUX_GPIO1__FUNC_SPI2_MO>,
<PINMUX_GPIO2__FUNC_SPI2_CLK>;
bias-disable;
};
pins_spi_mi {
pins-spi-mi {
pinmux = <PINMUX_GPIO94__FUNC_SPI2_MI>;
mediatek,pull-down-adv = <00>;
};
};
spi3_pins: spi3 {
pins_spi {
pins-spi {
pinmux = <PINMUX_GPIO21__FUNC_SPI3_MI>,
<PINMUX_GPIO22__FUNC_SPI3_CSB>,
<PINMUX_GPIO23__FUNC_SPI3_MO>,
@ -763,7 +763,7 @@
};
spi4_pins: spi4 {
pins_spi {
pins-spi {
pinmux = <PINMUX_GPIO17__FUNC_SPI4_MI>,
<PINMUX_GPIO18__FUNC_SPI4_CSB>,
<PINMUX_GPIO19__FUNC_SPI4_MO>,
@ -773,7 +773,7 @@
};
spi5_pins: spi5 {
pins_spi {
pins-spi {
pinmux = <PINMUX_GPIO13__FUNC_SPI5_MI>,
<PINMUX_GPIO14__FUNC_SPI5_CSB>,
<PINMUX_GPIO15__FUNC_SPI5_MO>,
@ -783,63 +783,63 @@
};
uart0_pins_default: uart0-pins-default {
pins_rx {
pins-rx {
pinmux = <PINMUX_GPIO95__FUNC_URXD0>;
input-enable;
bias-pull-up;
};
pins_tx {
pins-tx {
pinmux = <PINMUX_GPIO96__FUNC_UTXD0>;
};
};
uart1_pins_default: uart1-pins-default {
pins_rx {
pins-rx {
pinmux = <PINMUX_GPIO121__FUNC_URXD1>;
input-enable;
bias-pull-up;
};
pins_tx {
pins-tx {
pinmux = <PINMUX_GPIO115__FUNC_UTXD1>;
};
pins_rts {
pins-rts {
pinmux = <PINMUX_GPIO47__FUNC_URTS1>;
output-enable;
};
pins_cts {
pins-cts {
pinmux = <PINMUX_GPIO46__FUNC_UCTS1>;
input-enable;
};
};
uart1_pins_sleep: uart1-pins-sleep {
pins_rx {
pins-rx {
pinmux = <PINMUX_GPIO121__FUNC_GPIO121>;
input-enable;
bias-pull-up;
};
pins_tx {
pins-tx {
pinmux = <PINMUX_GPIO115__FUNC_UTXD1>;
};
pins_rts {
pins-rts {
pinmux = <PINMUX_GPIO47__FUNC_URTS1>;
output-enable;
};
pins_cts {
pins-cts {
pinmux = <PINMUX_GPIO46__FUNC_UCTS1>;
input-enable;
};
};
wifi_pins_pwrseq: wifi-pins-pwrseq {
pins_wifi_enable {
pins-wifi-enable {
pinmux = <PINMUX_GPIO119__FUNC_GPIO119>;
output-low;
};
};
wifi_pins_wakeup: wifi-pins-wakeup {
pins_wifi_wakeup {
pins-wifi-wakeup {
pinmux = <PINMUX_GPIO113__FUNC_GPIO113>;
input-enable;
};

242
arch/arm64/boot/dts/mediatek/mt8183.dtsi
View File

@ -1210,127 +1210,6 @@
nvmem-cell-names = "calibration-data";
};
thermal_zones: thermal-zones {
cpu_thermal: cpu-thermal {
polling-delay-passive = <100>;
polling-delay = <500>;
thermal-sensors = <&thermal 0>;
sustainable-power = <5000>;
trips {
threshold: trip-point0 {
temperature = <68000>;
hysteresis = <2000>;
type = "passive";
};
target: trip-point1 {
temperature = <80000>;
hysteresis = <2000>;
type = "passive";
};
cpu_crit: cpu-crit {
temperature = <115000>;
hysteresis = <2000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&target>;
cooling-device = <&cpu0
THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>,
<&cpu1
THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>,
<&cpu2
THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>,
<&cpu3
THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>;
contribution = <3072>;
};
map1 {
trip = <&target>;
cooling-device = <&cpu4
THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>,
<&cpu5
THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>,
<&cpu6
THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>,
<&cpu7
THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>;
contribution = <1024>;
};
};
};
/* The tzts1 ~ tzts6 don't need to polling */
/* The tzts1 ~ tzts6 don't need to thermal throttle */
tzts1: tzts1 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&thermal 1>;
sustainable-power = <5000>;
trips {};
cooling-maps {};
};
tzts2: tzts2 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&thermal 2>;
sustainable-power = <5000>;
trips {};
cooling-maps {};
};
tzts3: tzts3 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&thermal 3>;
sustainable-power = <5000>;
trips {};
cooling-maps {};
};
tzts4: tzts4 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&thermal 4>;
sustainable-power = <5000>;
trips {};
cooling-maps {};
};
tzts5: tzts5 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&thermal 5>;
sustainable-power = <5000>;
trips {};
cooling-maps {};
};
tztsABB: tztsABB {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&thermal 6>;
sustainable-power = <5000>;
trips {};
cooling-maps {};
};
};
pwm0: pwm@1100e000 {
compatible = "mediatek,mt8183-disp-pwm";
reg = <0 0x1100e000 0 0x1000>;
@ -2105,4 +1984,125 @@
power-domains = <&spm MT8183_POWER_DOMAIN_CAM>;
};
};
thermal_zones: thermal-zones {
cpu_thermal: cpu-thermal {
polling-delay-passive = <100>;
polling-delay = <500>;
thermal-sensors = <&thermal 0>;
sustainable-power = <5000>;
trips {
threshold: trip-point0 {
temperature = <68000>;
hysteresis = <2000>;
type = "passive";
};
target: trip-point1 {
temperature = <80000>;
hysteresis = <2000>;
type = "passive";
};
cpu_crit: cpu-crit {
temperature = <115000>;
hysteresis = <2000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&target>;
cooling-device = <&cpu0
THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>,
<&cpu1
THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>,
<&cpu2
THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>,
<&cpu3
THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>;
contribution = <3072>;
};
map1 {
trip = <&target>;
cooling-device = <&cpu4
THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>,
<&cpu5
THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>,
<&cpu6
THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>,
<&cpu7
THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>;
contribution = <1024>;
};
};
};
/* The tzts1 ~ tzts6 don't need to polling */
/* The tzts1 ~ tzts6 don't need to thermal throttle */
tzts1: tzts1 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&thermal 1>;
sustainable-power = <5000>;
trips {};
cooling-maps {};
};
tzts2: tzts2 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&thermal 2>;
sustainable-power = <5000>;
trips {};
cooling-maps {};
};
tzts3: tzts3 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&thermal 3>;
sustainable-power = <5000>;
trips {};
cooling-maps {};
};
tzts4: tzts4 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&thermal 4>;
sustainable-power = <5000>;
trips {};
cooling-maps {};
};
tzts5: tzts5 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&thermal 5>;
sustainable-power = <5000>;
trips {};
cooling-maps {};
};
tztsABB: tztsABB {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&thermal 6>;
sustainable-power = <5000>;
trips {};
cooling-maps {};
};
};
};

44
arch/arm64/boot/dts/mediatek/mt8186.dtsi
View File

@ -924,7 +924,8 @@
reg = <MT8186_POWER_DOMAIN_CSIRX_TOP>;
clocks = <&topckgen CLK_TOP_SENINF>,
<&topckgen CLK_TOP_SENINF1>;
clock-names = "csirx_top0", "csirx_top1";
clock-names = "subsys-csirx-top0",
"subsys-csirx-top1";
#power-domain-cells = <0>;
};
@ -942,7 +943,8 @@
reg = <MT8186_POWER_DOMAIN_ADSP_AO>;
clocks = <&topckgen CLK_TOP_AUDIODSP>,
<&topckgen CLK_TOP_ADSP_BUS>;
clock-names = "audioadsp", "adsp_bus";
clock-names = "audioadsp",
"subsys-adsp-bus";
#address-cells = <1>;
#size-cells = <0>;
#power-domain-cells = <1>;
@ -975,8 +977,11 @@
<&mmsys CLK_MM_SMI_COMMON>,
<&mmsys CLK_MM_SMI_GALS>,
<&mmsys CLK_MM_SMI_IOMMU>;
clock-names = "disp", "mdp", "smi_infra", "smi_common",
"smi_gals", "smi_iommu";
clock-names = "disp", "mdp",
"subsys-smi-infra",
"subsys-smi-common",
"subsys-smi-gals",
"subsys-smi-iommu";
mediatek,infracfg = <&infracfg_ao>;
#address-cells = <1>;
#size-cells = <0>;
@ -993,15 +998,17 @@
power-domain@MT8186_POWER_DOMAIN_CAM {
reg = <MT8186_POWER_DOMAIN_CAM>;
clocks = <&topckgen CLK_TOP_CAM>,
<&topckgen CLK_TOP_SENINF>,
clocks = <&topckgen CLK_TOP_SENINF>,
<&topckgen CLK_TOP_SENINF1>,
<&topckgen CLK_TOP_SENINF2>,
<&topckgen CLK_TOP_SENINF3>,
<&camsys CLK_CAM2MM_GALS>,
<&topckgen CLK_TOP_CAMTM>,
<&camsys CLK_CAM2MM_GALS>;
clock-names = "cam-top", "cam0", "cam1", "cam2",
"cam3", "cam-tm", "gals";
<&topckgen CLK_TOP_CAM>;
clock-names = "cam0", "cam1", "cam2",
"cam3", "gals",
"subsys-cam-tm",
"subsys-cam-top";
mediatek,infracfg = <&infracfg_ao>;
#address-cells = <1>;
#size-cells = <0>;
@ -1020,9 +1027,9 @@
power-domain@MT8186_POWER_DOMAIN_IMG {
reg = <MT8186_POWER_DOMAIN_IMG>;
clocks = <&topckgen CLK_TOP_IMG1>,
<&imgsys1 CLK_IMG1_GALS_IMG1>;
clock-names = "img-top", "gals";
clocks = <&imgsys1 CLK_IMG1_GALS_IMG1>,
<&topckgen CLK_TOP_IMG1>;
clock-names = "gals", "subsys-img-top";
mediatek,infracfg = <&infracfg_ao>;
#address-cells = <1>;
#size-cells = <0>;
@ -1041,8 +1048,11 @@
<&ipesys CLK_IPE_LARB20>,
<&ipesys CLK_IPE_SMI_SUBCOM>,
<&ipesys CLK_IPE_GALS_IPE>;
clock-names = "ipe-top", "ipe-larb0", "ipe-larb1",
"ipe-smi", "ipe-gals";
clock-names = "subsys-ipe-top",
"subsys-ipe-larb0",
"subsys-ipe-larb1",
"subsys-ipe-smi",
"subsys-ipe-gals";
mediatek,infracfg = <&infracfg_ao>;
#power-domain-cells = <0>;
};
@ -1061,7 +1071,9 @@
clocks = <&topckgen CLK_TOP_WPE>,
<&wpesys CLK_WPE_SMI_LARB8_CK_EN>,
<&wpesys CLK_WPE_SMI_LARB8_PCLK_EN>;
clock-names = "wpe0", "larb-ck", "larb-pclk";
clock-names = "wpe0",
"subsys-larb-ck",
"subsys-larb-pclk";
mediatek,infracfg = <&infracfg_ao>;
#power-domain-cells = <0>;
};
@ -1656,7 +1668,7 @@
#address-cells = <1>;
#size-cells = <1>;
gpu_speedbin: gpu-speed-bin@59c {
gpu_speedbin: gpu-speedbin@59c {
reg = <0x59c 0x4>;
bits = <0 3>;
};

2
arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
View File

@ -389,7 +389,7 @@
pinctrl-0 = <&i2c7_pins>;
pmic@34 {
#interrupt-cells = <1>;
#interrupt-cells = <2>;
compatible = "mediatek,mt6360";
reg = <0x34>;
interrupt-controller;

6
arch/arm64/boot/dts/mediatek/mt8195.dtsi
View File

@ -627,6 +627,8 @@
power-domain@MT8195_POWER_DOMAIN_VENC_CORE1 {
reg = <MT8195_POWER_DOMAIN_VENC_CORE1>;
clocks = <&vencsys_core1 CLK_VENC_CORE1_LARB>;
clock-names = "venc1-larb";
mediatek,infracfg = <&infracfg_ao>;
#power-domain-cells = <0>;
};
@ -689,6 +691,8 @@
power-domain@MT8195_POWER_DOMAIN_VENC {
reg = <MT8195_POWER_DOMAIN_VENC>;
clocks = <&vencsys CLK_VENC_LARB>;
clock-names = "venc0-larb";
mediatek,infracfg = <&infracfg_ao>;
#power-domain-cells = <0>;
};
@ -2665,7 +2669,7 @@
reg = <0 0x1b010000 0 0x1000>;
mediatek,larb-id = <20>;
mediatek,smi = <&smi_common_vpp>;
clocks = <&vencsys_core1 CLK_VENC_CORE1_LARB>,
clocks = <&vencsys_core1 CLK_VENC_CORE1_VENC>,
<&vencsys_core1 CLK_VENC_CORE1_GALS>,
<&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>;
clock-names = "apb", "smi", "gals";

2
arch/arm64/boot/dts/rockchip/px30-ringneck-haikou.dts
View File

@ -86,7 +86,7 @@
sgtl5000_clk: sgtl5000-oscillator {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24576000>;
clock-frequency = <24576000>;
};
dc_12v: dc-12v-regulator {

2
arch/arm64/boot/dts/rockchip/rk3328.dtsi
View File

@ -668,7 +668,7 @@
vdec: video-codec@ff360000 {
compatible = "rockchip,rk3328-vdec", "rockchip,rk3399-vdec";
reg = <0x0 0xff360000 0x0 0x400>;
reg = <0x0 0xff360000 0x0 0x480>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>,
<&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>;

3
arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi
View File

@ -509,8 +509,7 @@ ap_i2c_tp: &i2c5 {
&pci_rootport {
mvl_wifi: wifi@0,0 {
compatible = "pci1b4b,2b42";
reg = <0x83010000 0x0 0x00000000 0x0 0x00100000
0x83010000 0x0 0x00100000 0x0 0x00100000>;
reg = <0x0000 0x0 0x0 0x0 0x0>;
interrupt-parent = <&gpio0>;
interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";

4
arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet-dumo.dts
View File

@ -34,8 +34,8 @@
&pci_rootport {
wifi@0,0 {
compatible = "qcom,ath10k";
reg = <0x00010000 0x0 0x00000000 0x0 0x00000000>,
<0x03010010 0x0 0x00000000 0x0 0x00200000>;
reg = <0x00000000 0x0 0x00000000 0x0 0x00000000>,
<0x03000010 0x0 0x00000000 0x0 0x00200000>;
qcom,ath10k-calibration-variant = "GO_DUMO";
};
};

1
arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi
View File

@ -489,6 +489,7 @@ ap_i2c_audio: &i2c8 {
#address-cells = <3>;
#size-cells = <2>;
ranges;
device_type = "pci";
};
};

6
arch/arm64/boot/dts/rockchip/rk3399.dtsi
View File

@ -1109,7 +1109,9 @@
power-domain@RK3399_PD_VDU {
reg = <RK3399_PD_VDU>;
clocks = <&cru ACLK_VDU>,
<&cru HCLK_VDU>;
<&cru HCLK_VDU>,
<&cru SCLK_VDU_CA>,
<&cru SCLK_VDU_CORE>;
pm_qos = <&qos_video_m1_r>,
<&qos_video_m1_w>;
#power-domain-cells = <0>;
@ -1384,7 +1386,7 @@
vdec: video-codec@ff660000 {
compatible = "rockchip,rk3399-vdec";
reg = <0x0 0xff660000 0x0 0x400>;
reg = <0x0 0xff660000 0x0 0x480>;
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>,
<&cru SCLK_VDU_CA>, <&cru SCLK_VDU_CORE>;

2
arch/arm64/boot/dts/rockchip/rk356x.dtsi
View File

@ -977,7 +977,7 @@
<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "sys", "pmc", "msi", "legacy", "err";
interrupt-names = "sys", "pmc", "msg", "legacy", "err";
bus-range = <0x0 0xf>;
clocks = <&cru ACLK_PCIE20_MST>, <&cru ACLK_PCIE20_SLV>,
<&cru ACLK_PCIE20_DBI>, <&cru PCLK_PCIE20>,

4
arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi
View File

@ -235,13 +235,13 @@
&pinctrl {
fan {
fan_int: fan-int {
rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
hym8563 {
hym8563_int: hym8563-int {
rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>;
};
};

2
arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts
View File

@ -38,7 +38,7 @@
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 =<&leds_gpio>;
pinctrl-0 = <&leds_gpio>;
led-1 {
gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>;

2
arch/arm64/boot/dts/rockchip/rk3588s-pinctrl.dtsi
View File

@ -369,7 +369,7 @@
emmc_data_strobe: emmc-data-strobe {
rockchip,pins =
/* emmc_data_strobe */
<2 RK_PA2 1 &pcfg_pull_none>;
<2 RK_PA2 1 &pcfg_pull_down>;
};
};

1
arch/arm64/boot/dts/rockchip/rk3588s.dtsi
View File

@ -1362,7 +1362,6 @@
<GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "ch0", "ch1", "ch2", "ch3";
rockchip,pmu = <&pmu1grf>;
};

7
arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
View File

@ -8,9 +8,6 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
/* Clock frequency (in Hz) of the rtcclk */
#define RTCCLK_FREQ 1000000
/ {
model = "Microchip PolarFire-SoC Icicle Kit";
compatible = "microchip,mpfs-icicle-reference-rtlv2210", "microchip,mpfs-icicle-kit",
@ -29,10 +26,6 @@
stdout-path = "serial1:115200n8";
};
cpus {
timebase-frequency = <RTCCLK_FREQ>;
};
leds {
compatible = "gpio-leds";

7
arch/riscv/boot/dts/microchip/mpfs-m100pfsevp.dts
View File

@ -10,9 +10,6 @@
#include "mpfs.dtsi"
#include "mpfs-m100pfs-fabric.dtsi"
/* Clock frequency (in Hz) of the rtcclk */
#define MTIMER_FREQ 1000000
/ {
model = "Aries Embedded M100PFEVPS";
compatible = "aries,m100pfsevp", "microchip,mpfs";
@ -33,10 +30,6 @@
stdout-path = "serial1:115200n8";
};
cpus {
timebase-frequency = <MTIMER_FREQ>;
};
ddrc_cache_lo: memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 0x0 0x40000000>;

7
arch/riscv/boot/dts/microchip/mpfs-polarberry.dts
View File

@ -6,9 +6,6 @@
#include "mpfs.dtsi"
#include "mpfs-polarberry-fabric.dtsi"
/* Clock frequency (in Hz) of the rtcclk */
#define MTIMER_FREQ 1000000
/ {
model = "Sundance PolarBerry";
compatible = "sundance,polarberry", "microchip,mpfs";
@ -22,10 +19,6 @@
stdout-path = "serial0:115200n8";
};
cpus {
timebase-frequency = <MTIMER_FREQ>;
};
ddrc_cache_lo: memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 0x0 0x2e000000>;

7
arch/riscv/boot/dts/microchip/mpfs-sev-kit.dts
View File

@ -6,9 +6,6 @@
#include "mpfs.dtsi"
#include "mpfs-sev-kit-fabric.dtsi"
/* Clock frequency (in Hz) of the rtcclk */
#define MTIMER_FREQ 1000000
/ {
#address-cells = <2>;
#size-cells = <2>;
@ -28,10 +25,6 @@
stdout-path = "serial1:115200n8";
};
cpus {
timebase-frequency = <MTIMER_FREQ>;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;

7
arch/riscv/boot/dts/microchip/mpfs-tysom-m.dts
View File

@ -11,9 +11,6 @@
#include "mpfs.dtsi"
#include "mpfs-tysom-m-fabric.dtsi"
/* Clock frequency (in Hz) of the rtcclk */
#define MTIMER_FREQ 1000000
/ {
model = "Aldec TySOM-M-MPFS250T-REV2";
compatible = "aldec,tysom-m-mpfs250t-rev2", "microchip,mpfs";
@ -34,10 +31,6 @@
stdout-path = "serial1:115200n8";
};
cpus {
timebase-frequency = <MTIMER_FREQ>;
};
ddrc_cache_lo: memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 0x0 0x30000000>;

1
arch/riscv/boot/dts/microchip/mpfs.dtsi
View File

@ -13,6 +13,7 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
timebase-frequency = <1000000>;
cpu0: cpu@0 {
compatible = "sifive,e51", "sifive,rocket0", "riscv";

1
arch/riscv/boot/dts/sophgo/cv1800b.dtsi
View File

@ -34,7 +34,6 @@
cpu0_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
};
};

70
drivers/firmware/arm_ffa/driver.c
View File

@ -99,6 +99,7 @@ struct ffa_drv_info {
void *tx_buffer;
bool mem_ops_native;
bool bitmap_created;
bool notif_enabled;
unsigned int sched_recv_irq;
unsigned int cpuhp_state;
struct ffa_pcpu_irq __percpu *irq_pcpu;
@ -782,7 +783,7 @@ static void ffa_notification_info_get(void)
if (ids_processed >= max_ids - 1)
break;
part_id = packed_id_list[++ids_processed];
part_id = packed_id_list[ids_processed++];
if (!ids_count[list]) { /* Global Notification */
__do_sched_recv_cb(part_id, 0, false);
@ -794,7 +795,7 @@ static void ffa_notification_info_get(void)
if (ids_processed >= max_ids - 1)
break;
vcpu_id = packed_id_list[++ids_processed];
vcpu_id = packed_id_list[ids_processed++];
__do_sched_recv_cb(part_id, vcpu_id, true);
}
@ -889,6 +890,8 @@ static int ffa_memory_lend(struct ffa_mem_ops_args *args)
#define FFA_SECURE_PARTITION_ID_FLAG BIT(15)
#define ffa_notifications_disabled() (!drv_info->notif_enabled)
enum notify_type {
NON_SECURE_VM,
SECURE_PARTITION,
@ -908,6 +911,9 @@ static int ffa_sched_recv_cb_update(u16 part_id, ffa_sched_recv_cb callback,
struct ffa_dev_part_info *partition;
bool cb_valid;
if (ffa_notifications_disabled())
return -EOPNOTSUPP;
partition = xa_load(&drv_info->partition_info, part_id);
write_lock(&partition->rw_lock);
@ -1001,6 +1007,9 @@ static int ffa_notify_relinquish(struct ffa_device *dev, int notify_id)
int rc;
enum notify_type type = ffa_notify_type_get(dev->vm_id);
if (ffa_notifications_disabled())
return -EOPNOTSUPP;
if (notify_id >= FFA_MAX_NOTIFICATIONS)
return -EINVAL;
@ -1027,6 +1036,9 @@ static int ffa_notify_request(struct ffa_device *dev, bool is_per_vcpu,
u32 flags = 0;
enum notify_type type = ffa_notify_type_get(dev->vm_id);
if (ffa_notifications_disabled())
return -EOPNOTSUPP;
if (notify_id >= FFA_MAX_NOTIFICATIONS)
return -EINVAL;
@ -1057,6 +1069,9 @@ static int ffa_notify_send(struct ffa_device *dev, int notify_id,
{
u32 flags = 0;
if (ffa_notifications_disabled())
return -EOPNOTSUPP;
if (is_per_vcpu)
flags |= (PER_VCPU_NOTIFICATION_FLAG | vcpu << 16);
@ -1233,7 +1248,7 @@ static void ffa_partitions_cleanup(void)
if (!count)
return;
info = kcalloc(count, sizeof(**info), GFP_KERNEL);
info = kcalloc(count, sizeof(*info), GFP_KERNEL);
if (!info)
return;
@ -1311,8 +1326,10 @@ static int ffa_sched_recv_irq_map(void)
static void ffa_sched_recv_irq_unmap(void)
{
if (drv_info->sched_recv_irq)
if (drv_info->sched_recv_irq) {
irq_dispose_mapping(drv_info->sched_recv_irq);
drv_info->sched_recv_irq = 0;
}
}
static int ffa_cpuhp_pcpu_irq_enable(unsigned int cpu)
@ -1329,17 +1346,23 @@ static int ffa_cpuhp_pcpu_irq_disable(unsigned int cpu)
static void ffa_uninit_pcpu_irq(void)
{
if (drv_info->cpuhp_state)
if (drv_info->cpuhp_state) {
cpuhp_remove_state(drv_info->cpuhp_state);
drv_info->cpuhp_state = 0;
}
if (drv_info->notif_pcpu_wq)
if (drv_info->notif_pcpu_wq) {
destroy_workqueue(drv_info->notif_pcpu_wq);
drv_info->notif_pcpu_wq = NULL;
}
if (drv_info->sched_recv_irq)
free_percpu_irq(drv_info->sched_recv_irq, drv_info->irq_pcpu);
if (drv_info->irq_pcpu)
if (drv_info->irq_pcpu) {
free_percpu(drv_info->irq_pcpu);
drv_info->irq_pcpu = NULL;
}
}
static int ffa_init_pcpu_irq(unsigned int irq)
@ -1388,22 +1411,23 @@ static void ffa_notifications_cleanup(void)
ffa_notification_bitmap_destroy();
drv_info->bitmap_created = false;
}
drv_info->notif_enabled = false;
}
static int ffa_notifications_setup(void)
static void ffa_notifications_setup(void)
{
int ret, irq;
ret = ffa_features(FFA_NOTIFICATION_BITMAP_CREATE, 0, NULL, NULL);
if (ret) {
pr_err("Notifications not supported, continuing with it ..\n");
return 0;
pr_info("Notifications not supported, continuing with it ..\n");
return;
}
ret = ffa_notification_bitmap_create();
if (ret) {
pr_err("notification_bitmap_create error %d\n", ret);
return ret;
pr_info("Notification bitmap create error %d\n", ret);
return;
}
drv_info->bitmap_created = true;
@ -1422,14 +1446,11 @@ static int ffa_notifications_setup(void)
hash_init(drv_info->notifier_hash);
mutex_init(&drv_info->notify_lock);
/* Register internal scheduling callback */
ret = ffa_sched_recv_cb_update(drv_info->vm_id, ffa_self_notif_handle,
drv_info, true);
if (!ret)
return ret;
drv_info->notif_enabled = true;
return;
cleanup:
pr_info("Notification setup failed %d, not enabled\n", ret);
ffa_notifications_cleanup();
return ret;
}
static int __init ffa_init(void)
@ -1483,17 +1504,18 @@ static int __init ffa_init(void)
mutex_init(&drv_info->rx_lock);
mutex_init(&drv_info->tx_lock);
ffa_setup_partitions();
ffa_set_up_mem_ops_native_flag();
ret = ffa_notifications_setup();
ffa_notifications_setup();
ffa_setup_partitions();
ret = ffa_sched_recv_cb_update(drv_info->vm_id, ffa_self_notif_handle,
drv_info, true);
if (ret)
goto partitions_cleanup;
pr_info("Failed to register driver sched callback %d\n", ret);
return 0;
partitions_cleanup:
ffa_partitions_cleanup();
free_pages:
if (drv_info->tx_buffer)
free_pages_exact(drv_info->tx_buffer, RXTX_BUFFER_SIZE);

18
drivers/firmware/arm_scmi/perf.c
View File

@ -152,7 +152,7 @@ struct perf_dom_info {
u32 opp_count;
u32 sustained_freq_khz;
u32 sustained_perf_level;
u32 mult_factor;
unsigned long mult_factor;
struct scmi_perf_domain_info info;
struct scmi_opp opp[MAX_OPPS];
struct scmi_fc_info *fc_info;
@ -268,13 +268,14 @@ scmi_perf_domain_attributes_get(const struct scmi_protocol_handle *ph,
dom_info->sustained_perf_level =
le32_to_cpu(attr->sustained_perf_level);
if (!dom_info->sustained_freq_khz ||
!dom_info->sustained_perf_level)
!dom_info->sustained_perf_level ||
dom_info->level_indexing_mode)
/* CPUFreq converts to kHz, hence default 1000 */
dom_info->mult_factor = 1000;
else
dom_info->mult_factor =
(dom_info->sustained_freq_khz * 1000) /
dom_info->sustained_perf_level;
(dom_info->sustained_freq_khz * 1000UL)
/ dom_info->sustained_perf_level;
strscpy(dom_info->info.name, attr->name,
SCMI_SHORT_NAME_MAX_SIZE);
}
@ -798,7 +799,7 @@ static int scmi_dvfs_device_opps_add(const struct scmi_protocol_handle *ph,
if (!dom->level_indexing_mode)
freq = dom->opp[idx].perf * dom->mult_factor;
else
freq = dom->opp[idx].indicative_freq * 1000;
freq = dom->opp[idx].indicative_freq * dom->mult_factor;
data.level = dom->opp[idx].perf;
data.freq = freq;
@ -845,7 +846,8 @@ static int scmi_dvfs_freq_set(const struct scmi_protocol_handle *ph, u32 domain,
} else {
struct scmi_opp *opp;
opp = LOOKUP_BY_FREQ(dom->opps_by_freq, freq / 1000);
opp = LOOKUP_BY_FREQ(dom->opps_by_freq,
freq / dom->mult_factor);
if (!opp)
return -EIO;
@ -879,7 +881,7 @@ static int scmi_dvfs_freq_get(const struct scmi_protocol_handle *ph, u32 domain,
if (!opp)
return -EIO;
*freq = opp->indicative_freq * 1000;
*freq = opp->indicative_freq * dom->mult_factor;
}
return ret;
@ -902,7 +904,7 @@ static int scmi_dvfs_est_power_get(const struct scmi_protocol_handle *ph,
if (!dom->level_indexing_mode)
opp_freq = opp->perf * dom->mult_factor;
else
opp_freq = opp->indicative_freq * 1000;
opp_freq = opp->indicative_freq * dom->mult_factor;
if (opp_freq < *freq)
continue;

17
drivers/tee/optee/device.c
View File

@ -60,7 +60,16 @@ static void optee_release_device(struct device *dev)
kfree(optee_device);
}
static int optee_register_device(const uuid_t *device_uuid)
static ssize_t need_supplicant_show(struct device *dev,
struct device_attribute *attr,
char *buf)
{
return 0;
}
static DEVICE_ATTR_RO(need_supplicant);
static int optee_register_device(const uuid_t *device_uuid, u32 func)
{
struct tee_client_device *optee_device = NULL;
int rc;
@ -83,6 +92,10 @@ static int optee_register_device(const uuid_t *device_uuid)
put_device(&optee_device->dev);
}
if (func == PTA_CMD_GET_DEVICES_SUPP)
device_create_file(&optee_device->dev,
&dev_attr_need_supplicant);
return rc;
}
@ -142,7 +155,7 @@ static int __optee_enumerate_devices(u32 func)
num_devices = shm_size / sizeof(uuid_t);
for (idx = 0; idx < num_devices; idx++) {
rc = optee_register_device(&device_uuid[idx]);
rc = optee_register_device(&device_uuid[idx], func);
if (rc)
goto out_shm;
}

2
include/linux/arm_ffa.h
View File

@ -209,6 +209,8 @@ bool ffa_device_is_valid(struct ffa_device *ffa_dev) { return false; }
#define module_ffa_driver(__ffa_driver) \
module_driver(__ffa_driver, ffa_register, ffa_unregister)
extern struct bus_type ffa_bus_type;
/* FFA transport related */
struct ffa_partition_info {
u16 id;