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clk: mediatek: Add MT8186 imgsys clock support

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Add MT8186 imgsys clock controllers which provide clock gate
control for image IP blocks.

Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Miles Chen <miles.chen@mediatek.com>
Link: https://lore.kernel.org/r/20220409132251.31725-11-chun-jie.chen@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
Chun-Jie Chen 2022-04-09 21:22:46 +08:00 committed by Stephen Boyd
parent b6da76d6eb
commit a6c0c9b8fc
2 changed files with 70 additions and 1 deletions
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3
drivers/clk/mediatek/Makefile
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@ -73,7 +73,8 @@ obj-$(CONFIG_COMMON_CLK_MT8183_VDECSYS) += clk-mt8183-vdec.o
obj-$(CONFIG_COMMON_CLK_MT8183_VENCSYS) += clk-mt8183-venc.o
obj-$(CONFIG_COMMON_CLK_MT8186) += clk-mt8186-mcu.o clk-mt8186-topckgen.o clk-mt8186-infra_ao.o \
clk-mt8186-apmixedsys.o clk-mt8186-imp_iic_wrap.o \
clk-mt8186-mfg.o clk-mt8186-mm.o clk-mt8186-wpe.o
clk-mt8186-mfg.o clk-mt8186-mm.o clk-mt8186-wpe.o \
clk-mt8186-img.o
obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192.o
obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o

68
drivers/clk/mediatek/clk-mt8186-img.c Normal file
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@ -0,0 +1,68 @@
// SPDX-License-Identifier: GPL-2.0-only
//
// Copyright (c) 2022 MediaTek Inc.
// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
#include <dt-bindings/clock/mt8186-clk.h>
#include "clk-gate.h"
#include "clk-mtk.h"
static const struct mtk_gate_regs img_cg_regs = {
.set_ofs = 0x4,
.clr_ofs = 0x8,
.sta_ofs = 0x0,
};
#define GATE_IMG(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &img_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
static const struct mtk_gate img1_clks[] = {
GATE_IMG(CLK_IMG1_LARB9_IMG1, "img1_larb9_img1", "top_img1", 0),
GATE_IMG(CLK_IMG1_LARB10_IMG1, "img1_larb10_img1", "top_img1", 1),
GATE_IMG(CLK_IMG1_DIP, "img1_dip", "top_img1", 2),
GATE_IMG(CLK_IMG1_GALS_IMG1, "img1_gals_img1", "top_img1", 12),
};
static const struct mtk_gate img2_clks[] = {
GATE_IMG(CLK_IMG2_LARB9_IMG2, "img2_larb9_img2", "top_img1", 0),
GATE_IMG(CLK_IMG2_LARB10_IMG2, "img2_larb10_img2", "top_img1", 1),
GATE_IMG(CLK_IMG2_MFB, "img2_mfb", "top_img1", 6),
GATE_IMG(CLK_IMG2_WPE, "img2_wpe", "top_img1", 7),
GATE_IMG(CLK_IMG2_MSS, "img2_mss", "top_img1", 8),
GATE_IMG(CLK_IMG2_GALS_IMG2, "img2_gals_img2", "top_img1", 12),
};
static const struct mtk_clk_desc img1_desc = {
.clks = img1_clks,
.num_clks = ARRAY_SIZE(img1_clks),
};
static const struct mtk_clk_desc img2_desc = {
.clks = img2_clks,
.num_clks = ARRAY_SIZE(img2_clks),
};
static const struct of_device_id of_match_clk_mt8186_img[] = {
{
.compatible = "mediatek,mt8186-imgsys1",
.data = &img1_desc,
}, {
.compatible = "mediatek,mt8186-imgsys2",
.data = &img2_desc,
}, {
/* sentinel */
}
};
static struct platform_driver clk_mt8186_img_drv = {
.probe = mtk_clk_simple_probe,
.remove = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt8186-img",
.of_match_table = of_match_clk_mt8186_img,
},
};
builtin_platform_driver(clk_mt8186_img_drv);