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drm/nva3/clk: For PLL clocks always make sure the PLL is not in use

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Signed-off-by: Roy Spliet <rspliet@eclipso.eu>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Roy Spliet 2014-08-21 13:45:16 +02:00 committed by Ben Skeggs
parent 275dd6f48f
commit a749a1fb55
1 changed files with 9 additions and 0 deletions
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9
drivers/gpu/drm/nouveau/core/subdev/clock/nva3.c
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@ -305,8 +305,17 @@ prog_pll(struct nva3_clock_priv *priv, int clk, u32 pll, int idx)
const u32 src1 = 0x004160 + (clk * 4); const u32 src1 = 0x004160 + (clk * 4);
const u32 ctrl = pll + 0; const u32 ctrl = pll + 0;
const u32 coef = pll + 4; const u32 coef = pll + 4;
u32 bypass;
if (info->pll) { if (info->pll) {
/* Always start from a non-PLL clock */
bypass = nv_rd32(priv, ctrl) & 0x00000008;
if (!bypass) {
nv_mask(priv, src1, 0x00000101, 0x00000101);
nv_mask(priv, ctrl, 0x00000008, 0x00000008);
udelay(20);
}
nv_mask(priv, src0, 0x003f3141, 0x00000101 | info->clk); nv_mask(priv, src0, 0x003f3141, 0x00000101 | info->clk);
nv_wr32(priv, coef, info->pll); nv_wr32(priv, coef, info->pll);
nv_mask(priv, ctrl, 0x00000015, 0x00000015); nv_mask(priv, ctrl, 0x00000015, 0x00000015);