staging: vme_user: Fix various comment formatting issues including comment content
Fixed various issues relating to comments including:
* Lines with '*' in block comments which should be aligned and
were not
* Corrected comments where closing multiline comment identifier
ran over into second newline spuriously
* Corrected comment content to correctly reflect hexadecimal for
the offsets rather than integers
Signed-off-by: Jonathan Bergh <bergh.jonathan@gmail.com>
Link: https://lore.kernel.org/r/20230914200732.47659-1-bergh.jonathan@gmail.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Jonathan Bergh
Greg Kroah-Hartman
parent
c887e0830b
commit
a7705e54e1
@ -206,7 +206,7 @@ static const int TSI148_LCSR_OT[8] = { TSI148_LCSR_OT0, TSI148_LCSR_OT1,
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/*
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* VMEbus interrupt ack
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* offset 200
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* offset 0x200
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*/
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#define TSI148_LCSR_VIACK1 0x204
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#define TSI148_LCSR_VIACK2 0x208
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@ -223,7 +223,7 @@ static const int TSI148_LCSR_VIACK[8] = { 0, TSI148_LCSR_VIACK1,
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/*
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* RMW
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* offset 220
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* offset 0x220
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*/
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#define TSI148_LCSR_RMWAU 0x220
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#define TSI148_LCSR_RMWAL 0x224
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@ -233,7 +233,7 @@ static const int TSI148_LCSR_VIACK[8] = { 0, TSI148_LCSR_VIACK1,
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/*
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* VMEbus control
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* offset 234
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* offset 0x234
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*/
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#define TSI148_LCSR_VMCTRL 0x234
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#define TSI148_LCSR_VCTRL 0x238
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@ -241,27 +241,27 @@ static const int TSI148_LCSR_VIACK[8] = { 0, TSI148_LCSR_VIACK1,
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/*
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* PCI status
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* offset 240
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* offset 0x240
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*/
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#define TSI148_LCSR_PSTAT 0x240
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/*
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* VME filter.
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* offset 250
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* offset 0x250
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*/
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#define TSI148_LCSR_VMEFL 0x250
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/*
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/*
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* VME exception.
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* offset 260
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* offset 0x260
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*/
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#define TSI148_LCSR_VEAU 0x260
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#define TSI148_LCSR_VEAL 0x264
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#define TSI148_LCSR_VEAT 0x268
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/*
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/*
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* PCI error
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* offset 270
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* offset 0x270
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*/
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#define TSI148_LCSR_EDPAU 0x270
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#define TSI148_LCSR_EDPAL 0x274
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@ -269,9 +269,9 @@ static const int TSI148_LCSR_VIACK[8] = { 0, TSI148_LCSR_VIACK1,
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#define TSI148_LCSR_EDPXS 0x27C
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#define TSI148_LCSR_EDPAT 0x280
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/*
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/*
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* Inbound Translations
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* offset 300
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* offset 0x300
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*/
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#define TSI148_LCSR_IT0_ITSAU 0x300
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#define TSI148_LCSR_IT0_ITSAL 0x304
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@ -359,42 +359,42 @@ static const int TSI148_LCSR_IT[8] = { TSI148_LCSR_IT0, TSI148_LCSR_IT1,
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#define TSI148_LCSR_OFFSET_ITOFL 0x14
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#define TSI148_LCSR_OFFSET_ITAT 0x18
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/*
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/*
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* Inbound Translation GCSR
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* offset 400
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* offset 0x400
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*/
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#define TSI148_LCSR_GBAU 0x400
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#define TSI148_LCSR_GBAL 0x404
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#define TSI148_LCSR_GCSRAT 0x408
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/*
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/*
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* Inbound Translation CRG
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* offset 40C
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* offset 0x40C
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*/
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#define TSI148_LCSR_CBAU 0x40C
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#define TSI148_LCSR_CBAL 0x410
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#define TSI148_LCSR_CSRAT 0x414
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/*
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/*
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* Inbound Translation CR/CSR
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* CRG
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* offset 418
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* offset 0x418
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*/
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#define TSI148_LCSR_CROU 0x418
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#define TSI148_LCSR_CROL 0x41C
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#define TSI148_LCSR_CRAT 0x420
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/*
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/*
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* Inbound Translation Location Monitor
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* offset 424
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* offset 0x424
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*/
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#define TSI148_LCSR_LMBAU 0x424
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#define TSI148_LCSR_LMBAL 0x428
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#define TSI148_LCSR_LMAT 0x42C
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/*
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/*
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* VMEbus Interrupt Control.
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* offset 430
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* offset 0x430
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*/
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#define TSI148_LCSR_BCU 0x430
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#define TSI148_LCSR_BCL 0x434
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@ -402,9 +402,9 @@ static const int TSI148_LCSR_IT[8] = { TSI148_LCSR_IT0, TSI148_LCSR_IT1,
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#define TSI148_LCSR_BPCTR 0x43C
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#define TSI148_LCSR_VICR 0x440
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/*
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/*
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* Local Bus Interrupt Control.
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* offset 448
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* offset 0x448
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*/
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#define TSI148_LCSR_INTEN 0x448
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#define TSI148_LCSR_INTEO 0x44C
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@ -413,9 +413,9 @@ static const int TSI148_LCSR_IT[8] = { TSI148_LCSR_IT0, TSI148_LCSR_IT1,
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#define TSI148_LCSR_INTM1 0x458
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#define TSI148_LCSR_INTM2 0x45C
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/*
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/*
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* DMA Controllers
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* offset 500
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* offset 0x500
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*/
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#define TSI148_LCSR_DCTL0 0x500
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#define TSI148_LCSR_DSTA0 0x504
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@ -480,26 +480,26 @@ static const int TSI148_LCSR_DMA[TSI148_MAX_DMA] = { TSI148_LCSR_DMA0,
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#define TSI148_LCSR_OFFSET_DCNT 0x40
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#define TSI148_LCSR_OFFSET_DDBS 0x44
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/*
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/*
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* GCSR Register Group
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*/
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/*
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/*
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* GCSR CRG
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* offset 00 600 - DEVI/VENI
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* offset 04 604 - CTRL/GA/REVID
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* offset 08 608 - Semaphore3/2/1/0
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* offset 0C 60C - Seamphore7/6/5/4
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* offset 0x00 0x600 - DEVI/VENI
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* offset 0x04 0x604 - CTRL/GA/REVID
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* offset 0x08 0x608 - Semaphore3/2/1/0
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* offset 0x0C 0x60C - Seamphore7/6/5/4
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*/
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#define TSI148_GCSR_ID 0x600
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#define TSI148_GCSR_CSR 0x604
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#define TSI148_GCSR_SEMA0 0x608
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#define TSI148_GCSR_SEMA1 0x60C
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/*
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/*
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* Mail Box
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* GCSR CRG
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* offset 10 610 - Mailbox0
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* offset 0x10 0x610 - Mailbox0
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*/
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#define TSI148_GCSR_MBOX0 0x610
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#define TSI148_GCSR_MBOX1 0x614
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@ -511,25 +511,25 @@ static const int TSI148_GCSR_MBOX[4] = { TSI148_GCSR_MBOX0,
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TSI148_GCSR_MBOX2,
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TSI148_GCSR_MBOX3 };
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/*
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/*
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* CR/CSR
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*/
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/*
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/*
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* CR/CSR CRG
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* offset 7FFF4 FF4 - CSRBCR
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* offset 7FFF8 FF8 - CSRBSR
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* offset 7FFFC FFC - CBAR
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* offset 0x7FFF4 0xFF4 - CSRBCR
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* offset 0x7FFF8 0xFF8 - CSRBSR
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* offset 0x7FFFC 0xFFC - CBAR
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*/
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#define TSI148_CSRBCR 0xFF4
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#define TSI148_CSRBSR 0xFF8
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#define TSI148_CBAR 0xFFC
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/*
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/*
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* TSI148 Register Bit Definitions
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*/
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/*
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/*
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* PFCS Register Set
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*/
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#define TSI148_PCFS_CMMD_SERR BIT(8) /* SERR_L out pin ssys err */
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@ -603,8 +603,7 @@ static const int TSI148_GCSR_MBOX[4] = { TSI148_GCSR_MBOX0,
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*/
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#define TSI148_PCFS_PCIXSTAT_RSCEM BIT(29) /* Received Split Comp Error */
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#define TSI148_PCFS_PCIXSTAT_DMCRS_M (7<<26) /* max Cumulative Read Size */
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#define TSI148_PCFS_PCIXSTAT_DMOST_M (7<<23) /* max outstanding Split Trans
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*/
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#define TSI148_PCFS_PCIXSTAT_DMOST_M (7<<23) /* max outstanding Split Trans */
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#define TSI148_PCFS_PCIXSTAT_DMMRC_M (3<<21) /* max mem read byte count */
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#define TSI148_PCFS_PCIXSTAT_DC BIT(20) /* Device Complexity */
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#define TSI148_PCFS_PCIXSTAT_USC BIT(19) /* Unexpected Split comp */
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@ -766,8 +765,7 @@ static const int TSI148_GCSR_MBOX[4] = { TSI148_GCSR_MBOX0,
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#define TSI148_LCSR_VCTRL_ATOEN BIT(7) /* Arbiter Time-out Enable */
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#define TSI148_LCSR_VCTRL_ROBIN BIT(6) /* VMEbus Round Robin */
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#define TSI148_LCSR_VCTRL_GTO_M (7<<0) /* VMEbus Global Time-out Mask
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*/
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#define TSI148_LCSR_VCTRL_GTO_M (7<<0) /* VMEbus Global Time-out Mask*/
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#define TSI148_LCSR_VCTRL_GTO_8 (0<<0) /* 8 us */
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#define TSI148_LCSR_VCTRL_GTO_16 BIT(0) /* 16 us */
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#define TSI148_LCSR_VCTRL_GTO_32 (2<<0) /* 32 us */
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