habanalabs/gaudi: collect undefined opcode error info
when an undefined opcode error occurres, the driver collects the relevant information from the Qman and stores it inside the hdev data structure. An event fd indication is sent towards the user space. Note: another commit shall be followed which will add support to read the error info by an ioctl. Signed-off-by: Tal Cohen <talcohen@habana.ai> Reviewed-by: Oded Gabbay <ogabbay@kernel.org> Signed-off-by: Oded Gabbay <ogabbay@kernel.org>
This commit is contained in:
Tal Cohen
Oded Gabbay
parent
41021f728a
commit
a7d6c35bcd
@ -1531,10 +1531,11 @@ out_err:
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return rc;
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}
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static void hl_notifier_event_send(struct hl_notifier_event *notifier_event, u64 event)
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static void hl_notifier_event_send(struct hl_notifier_event *notifier_event, u64 event_mask)
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{
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mutex_lock(¬ifier_event->lock);
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notifier_event->events_mask |= event;
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notifier_event->events_mask |= event_mask;
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if (notifier_event->eventfd)
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eventfd_signal(notifier_event->eventfd, 1);
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@ -1545,17 +1546,17 @@ static void hl_notifier_event_send(struct hl_notifier_event *notifier_event, u64
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* hl_notifier_event_send_all - notify all user processes via eventfd
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*
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* @hdev: pointer to habanalabs device structure
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* @event: the occurred event
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* @event_mask: the occurred event/s
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* Returns 0 for success or an error on failure.
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*/
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void hl_notifier_event_send_all(struct hl_device *hdev, u64 event)
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void hl_notifier_event_send_all(struct hl_device *hdev, u64 event_mask)
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{
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struct hl_fpriv *hpriv;
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mutex_lock(&hdev->fpriv_list_lock);
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list_for_each_entry(hpriv, &hdev->fpriv_list, dev_node)
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hl_notifier_event_send(&hpriv->notifier_event, event);
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hl_notifier_event_send(&hpriv->notifier_event, event_mask);
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mutex_unlock(&hdev->fpriv_list_lock);
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@ -1563,7 +1564,7 @@ void hl_notifier_event_send_all(struct hl_device *hdev, u64 event)
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mutex_lock(&hdev->fpriv_ctrl_list_lock);
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list_for_each_entry(hpriv, &hdev->fpriv_ctrl_list, dev_node)
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hl_notifier_event_send(&hpriv->notifier_event, event);
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hl_notifier_event_send(&hpriv->notifier_event, event_mask);
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mutex_unlock(&hdev->fpriv_ctrl_list_lock);
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}
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@ -2644,14 +2644,48 @@ struct razwi_info {
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u8 type;
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};
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#define MAX_QMAN_STREAMS_INFO 4
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#define OPCODE_INFO_MAX_ADDR_SIZE 8
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/**
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* struct undefined_opcode_info - info about last undefined opcode error
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* @timestamp: timestamp of the undefined opcode error
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* @cb_addr_streams: CB addresses (per stream) that are currently exists in the PQ
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* entiers. In case all streams array entries are
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* filled with values, it means the execution was in Lower-CP.
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* @cq_addr: the address of the current handled command buffer
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* @cq_size: the size of the current handled command buffer
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* @cb_addr_streams_len: num of streams - actual len of cb_addr_streams array.
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* should be equal to 1 incase of undefined opcode
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* in Upper-CP (specific stream) and equal to 4 incase
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* of undefined opcode in Lower-CP.
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* @engine_id: engine-id that the error occurred on
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* @stream_id: the stream id the error occurred on. In case the stream equals to
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* MAX_QMAN_STREAMS_INFO it means the error occurred on a Lower-CP.
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* @write_enable: if set, writing to undefined opcode parameters in the structure
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* is enable so the first (root cause) undefined opcode will not be
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* overwritten.
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*/
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struct undefined_opcode_info {
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ktime_t timestamp;
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u64 cb_addr_streams[MAX_QMAN_STREAMS_INFO][OPCODE_INFO_MAX_ADDR_SIZE];
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u64 cq_addr;
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u32 cq_size;
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u32 cb_addr_streams_len;
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u32 engine_id;
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u32 stream_id;
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bool write_enable;
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};
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/**
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* struct last_error_session_info - info about last session errors occurred.
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* @cs_timeout: CS timeout error last information.
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* @razwi: razwi last information.
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* @undef_opcode: undefined opcode information
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*/
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struct last_error_session_info {
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struct cs_timeout_info cs_timeout;
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struct razwi_info razwi;
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struct cs_timeout_info cs_timeout;
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struct razwi_info razwi;
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struct undefined_opcode_info undef_opcode;
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};
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/**
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@ -3159,7 +3193,7 @@ int hl_device_utilization(struct hl_device *hdev, u32 *utilization);
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int hl_build_hwmon_channel_info(struct hl_device *hdev,
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struct cpucp_sensor *sensors_arr);
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void hl_notifier_event_send_all(struct hl_device *hdev, u64 event);
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void hl_notifier_event_send_all(struct hl_device *hdev, u64 event_mask);
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int hl_sysfs_init(struct hl_device *hdev);
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void hl_sysfs_fini(struct hl_device *hdev);
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@ -198,6 +198,7 @@ int hl_device_open(struct inode *inode, struct file *filp)
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atomic_set(&hdev->last_error.cs_timeout.write_enable, 1);
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atomic_set(&hdev->last_error.razwi.write_enable, 1);
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hdev->last_error.undef_opcode.write_enable = true;
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hdev->open_counter++;
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hdev->last_successful_open_jif = jiffies;
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@ -443,6 +443,38 @@ static s64 gaudi_state_dump_specs_props[] = {
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[SP_NUM_CORES] = 1,
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};
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static const int gaudi_queue_id_to_engine_id[] = {
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[GAUDI_QUEUE_ID_DMA_0_0...GAUDI_QUEUE_ID_DMA_0_3] = GAUDI_ENGINE_ID_DMA_0,
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[GAUDI_QUEUE_ID_DMA_1_0...GAUDI_QUEUE_ID_DMA_1_3] = GAUDI_ENGINE_ID_DMA_1,
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[GAUDI_QUEUE_ID_CPU_PQ] = GAUDI_ENGINE_ID_SIZE,
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[GAUDI_QUEUE_ID_DMA_2_0...GAUDI_QUEUE_ID_DMA_2_3] = GAUDI_ENGINE_ID_DMA_2,
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[GAUDI_QUEUE_ID_DMA_3_0...GAUDI_QUEUE_ID_DMA_3_3] = GAUDI_ENGINE_ID_DMA_3,
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[GAUDI_QUEUE_ID_DMA_4_0...GAUDI_QUEUE_ID_DMA_4_3] = GAUDI_ENGINE_ID_DMA_4,
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[GAUDI_QUEUE_ID_DMA_5_0...GAUDI_QUEUE_ID_DMA_5_3] = GAUDI_ENGINE_ID_DMA_5,
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[GAUDI_QUEUE_ID_DMA_6_0...GAUDI_QUEUE_ID_DMA_6_3] = GAUDI_ENGINE_ID_DMA_6,
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[GAUDI_QUEUE_ID_DMA_7_0...GAUDI_QUEUE_ID_DMA_7_3] = GAUDI_ENGINE_ID_DMA_7,
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[GAUDI_QUEUE_ID_MME_0_0...GAUDI_QUEUE_ID_MME_0_3] = GAUDI_ENGINE_ID_MME_0,
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[GAUDI_QUEUE_ID_MME_1_0...GAUDI_QUEUE_ID_MME_1_3] = GAUDI_ENGINE_ID_MME_1,
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[GAUDI_QUEUE_ID_TPC_0_0...GAUDI_QUEUE_ID_TPC_0_3] = GAUDI_ENGINE_ID_TPC_0,
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[GAUDI_QUEUE_ID_TPC_1_0...GAUDI_QUEUE_ID_TPC_1_3] = GAUDI_ENGINE_ID_TPC_1,
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[GAUDI_QUEUE_ID_TPC_2_0...GAUDI_QUEUE_ID_TPC_2_3] = GAUDI_ENGINE_ID_TPC_2,
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[GAUDI_QUEUE_ID_TPC_3_0...GAUDI_QUEUE_ID_TPC_3_3] = GAUDI_ENGINE_ID_TPC_3,
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[GAUDI_QUEUE_ID_TPC_4_0...GAUDI_QUEUE_ID_TPC_4_3] = GAUDI_ENGINE_ID_TPC_4,
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[GAUDI_QUEUE_ID_TPC_5_0...GAUDI_QUEUE_ID_TPC_5_3] = GAUDI_ENGINE_ID_TPC_5,
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[GAUDI_QUEUE_ID_TPC_6_0...GAUDI_QUEUE_ID_TPC_6_3] = GAUDI_ENGINE_ID_TPC_6,
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[GAUDI_QUEUE_ID_TPC_7_0...GAUDI_QUEUE_ID_TPC_7_3] = GAUDI_ENGINE_ID_TPC_7,
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[GAUDI_QUEUE_ID_NIC_0_0...GAUDI_QUEUE_ID_NIC_0_3] = GAUDI_ENGINE_ID_NIC_0,
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[GAUDI_QUEUE_ID_NIC_1_0...GAUDI_QUEUE_ID_NIC_1_3] = GAUDI_ENGINE_ID_NIC_1,
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[GAUDI_QUEUE_ID_NIC_2_0...GAUDI_QUEUE_ID_NIC_2_3] = GAUDI_ENGINE_ID_NIC_2,
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[GAUDI_QUEUE_ID_NIC_3_0...GAUDI_QUEUE_ID_NIC_3_3] = GAUDI_ENGINE_ID_NIC_3,
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[GAUDI_QUEUE_ID_NIC_4_0...GAUDI_QUEUE_ID_NIC_4_3] = GAUDI_ENGINE_ID_NIC_4,
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[GAUDI_QUEUE_ID_NIC_5_0...GAUDI_QUEUE_ID_NIC_5_3] = GAUDI_ENGINE_ID_NIC_5,
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[GAUDI_QUEUE_ID_NIC_6_0...GAUDI_QUEUE_ID_NIC_6_3] = GAUDI_ENGINE_ID_NIC_6,
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[GAUDI_QUEUE_ID_NIC_7_0...GAUDI_QUEUE_ID_NIC_7_3] = GAUDI_ENGINE_ID_NIC_7,
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[GAUDI_QUEUE_ID_NIC_8_0...GAUDI_QUEUE_ID_NIC_8_3] = GAUDI_ENGINE_ID_NIC_8,
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[GAUDI_QUEUE_ID_NIC_9_0...GAUDI_QUEUE_ID_NIC_9_3] = GAUDI_ENGINE_ID_NIC_9,
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};
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/* The order here is opposite to the order of the indexing in the h/w.
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* i.e. SYNC_MGR_W_S is actually 0, SYNC_MGR_E_S is 1, etc.
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*/
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@ -6989,14 +7021,15 @@ static inline u32 gaudi_queue_idx_dec(u32 idx, u32 q_len)
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}
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/**
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* gaudi_print_sw_config_stream_data - print SW config stream data
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* gaudi_handle_sw_config_stream_data - print SW config stream data
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*
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* @hdev: pointer to the habanalabs device structure
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* @stream: the QMAN's stream
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* @qman_base: base address of QMAN registers block
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* @event_mask: mask of the last events occurred
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*/
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static void gaudi_print_sw_config_stream_data(struct hl_device *hdev, u32 stream,
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u64 qman_base)
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static void gaudi_handle_sw_config_stream_data(struct hl_device *hdev, u32 stream,
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u64 qman_base, u64 event_mask)
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{
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u64 cq_ptr_lo, cq_ptr_hi, cq_tsize, cq_ptr;
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u32 cq_ptr_lo_off, size;
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@ -7014,24 +7047,32 @@ static void gaudi_print_sw_config_stream_data(struct hl_device *hdev, u32 stream
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size = RREG32(cq_tsize);
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dev_info(hdev->dev, "stop on err: stream: %u, addr: %#llx, size: %u\n",
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stream, cq_ptr, size);
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if (event_mask & HL_NOTIFIER_EVENT_UNDEFINED_OPCODE) {
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hdev->last_error.undef_opcode.cq_addr = cq_ptr;
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hdev->last_error.undef_opcode.cq_size = size;
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hdev->last_error.undef_opcode.stream_id = stream;
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}
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}
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/**
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* gaudi_print_last_pqes_on_err - print last PQEs on error
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* gaudi_handle_last_pqes_on_err - print last PQEs on error
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*
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* @hdev: pointer to the habanalabs device structure
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* @qid_base: first QID of the QMAN (out of 4 streams)
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* @stream: the QMAN's stream
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* @qman_base: base address of QMAN registers block
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* @event_mask: mask of the last events occurred
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* @pr_sw_conf: if true print the SW config stream data (CQ PTR and SIZE)
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*/
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static void gaudi_print_last_pqes_on_err(struct hl_device *hdev, u32 qid_base,
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static void gaudi_handle_last_pqes_on_err(struct hl_device *hdev, u32 qid_base,
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u32 stream, u64 qman_base,
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u64 event_mask,
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bool pr_sw_conf)
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{
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u32 ci, qm_ci_stream_off, queue_len;
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struct hl_hw_queue *q;
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u64 pq_ci;
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u64 pq_ci, addr[PQ_FETCHER_CACHE_SIZE];
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int i;
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q = &hdev->kernel_queues[qid_base + stream];
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@ -7046,16 +7087,16 @@ static void gaudi_print_last_pqes_on_err(struct hl_device *hdev, u32 qid_base,
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hdev->asic_funcs->hw_queues_lock(hdev);
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if (pr_sw_conf)
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gaudi_print_sw_config_stream_data(hdev, stream, qman_base);
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gaudi_handle_sw_config_stream_data(hdev, stream, qman_base, event_mask);
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ci = RREG32(pq_ci);
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/* we should start printing form ci -1 */
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ci = gaudi_queue_idx_dec(ci, queue_len);
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memset(addr, 0, sizeof(addr));
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for (i = 0; i < PQ_FETCHER_CACHE_SIZE; i++) {
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struct hl_bd *bd;
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u64 addr;
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u32 len;
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bd = q->kernel_address;
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@ -7066,52 +7107,68 @@ static void gaudi_print_last_pqes_on_err(struct hl_device *hdev, u32 qid_base,
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if (!len)
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break;
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addr = le64_to_cpu(bd->ptr);
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addr[i] = le64_to_cpu(bd->ptr);
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dev_info(hdev->dev, "stop on err PQE(stream %u): ci: %u, addr: %#llx, size: %u\n",
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stream, ci, addr, len);
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stream, ci, addr[i], len);
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/* get previous ci, wrap if needed */
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ci = gaudi_queue_idx_dec(ci, queue_len);
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}
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if (event_mask & HL_NOTIFIER_EVENT_UNDEFINED_OPCODE) {
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struct undefined_opcode_info *undef_opcode = &hdev->last_error.undef_opcode;
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u32 arr_idx = undef_opcode->cb_addr_streams_len;
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if (arr_idx == 0) {
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undef_opcode->timestamp = ktime_get();
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undef_opcode->engine_id = gaudi_queue_id_to_engine_id[qid_base];
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}
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memcpy(undef_opcode->cb_addr_streams[arr_idx], addr, sizeof(addr));
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undef_opcode->cb_addr_streams_len++;
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}
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hdev->asic_funcs->hw_queues_unlock(hdev);
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}
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/**
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* print_qman_data_on_err - extract QMAN data on error
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* handle_qman_data_on_err - extract QMAN data on error
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*
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* @hdev: pointer to the habanalabs device structure
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* @qid_base: first QID of the QMAN (out of 4 streams)
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* @stream: the QMAN's stream
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* @qman_base: base address of QMAN registers block
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* @event_mask: mask of the last events occurred
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*
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* This function attempt to exatract as much data as possible on QMAN error.
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* On upper CP print the SW config stream data and last 8 PQEs.
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* On lower CP print SW config data and last PQEs of ALL 4 upper CPs
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*/
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static void print_qman_data_on_err(struct hl_device *hdev, u32 qid_base,
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u32 stream, u64 qman_base)
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static void handle_qman_data_on_err(struct hl_device *hdev, u32 qid_base,
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u32 stream, u64 qman_base, u64 event_mask)
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{
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u32 i;
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if (stream != QMAN_STREAMS) {
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gaudi_print_last_pqes_on_err(hdev, qid_base, stream, qman_base,
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true);
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gaudi_handle_last_pqes_on_err(hdev, qid_base, stream,
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qman_base, event_mask, true);
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return;
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}
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gaudi_print_sw_config_stream_data(hdev, stream, qman_base);
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/* handle Lower-CP */
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gaudi_handle_sw_config_stream_data(hdev, stream, qman_base, event_mask);
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for (i = 0; i < QMAN_STREAMS; i++)
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gaudi_print_last_pqes_on_err(hdev, qid_base, i, qman_base,
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false);
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gaudi_handle_last_pqes_on_err(hdev, qid_base, i,
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qman_base, event_mask, false);
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}
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static void gaudi_handle_qman_err_generic(struct hl_device *hdev,
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const char *qm_name,
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u64 qman_base,
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u32 qid_base)
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u32 qid_base,
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u64 *event_mask)
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{
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u32 i, j, glbl_sts_val, arb_err_val, glbl_sts_clr_val;
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u64 glbl_sts_addr, arb_err_addr;
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@ -7142,12 +7199,21 @@ static void gaudi_handle_qman_err_generic(struct hl_device *hdev,
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glbl_sts_clr_val |= BIT(j);
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}
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}
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/* check for undefined opcode */
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if (glbl_sts_val & TPC0_QM_GLBL_STS1_CP_UNDEF_CMD_ERR_MASK &&
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hdev->last_error.undef_opcode.write_enable) {
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memset(&hdev->last_error.undef_opcode, 0,
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sizeof(hdev->last_error.undef_opcode));
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hdev->last_error.undef_opcode.write_enable = false;
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*event_mask |= HL_NOTIFIER_EVENT_UNDEFINED_OPCODE;
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}
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/* Write 1 clear errors */
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if (!hdev->stop_on_err)
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WREG32(glbl_sts_addr + 4 * i, glbl_sts_clr_val);
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else
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print_qman_data_on_err(hdev, qid_base, i, qman_base);
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handle_qman_data_on_err(hdev, qid_base, i, qman_base, *event_mask);
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}
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arb_err_val = RREG32(arb_err_addr);
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@ -7385,7 +7451,7 @@ static void gaudi_handle_qman_err(struct hl_device *hdev, u16 event_type, u64 *e
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return;
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}
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gaudi_handle_qman_err_generic(hdev, desc, qman_base, qid_base);
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gaudi_handle_qman_err_generic(hdev, desc, qman_base, qid_base, event_mask);
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}
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static void gaudi_print_irq_info(struct hl_device *hdev, u16 event_type,
|
||||
|
||||
@ -1402,9 +1402,13 @@ struct hl_debug_args {
|
||||
/*
|
||||
* Notifier event values - for the notification mechanism and the HL_INFO_GET_EVENTS command
|
||||
*
|
||||
* HL_NOTIFIER_EVENT_TPC_ASSERT - Indicates TPC assert event
|
||||
* HL_NOTIFIER_EVENT_TPC_ASSERT - Indicates TPC assert event
|
||||
* HL_NOTIFIER_EVENT_UNDEFINED_OPCODE - Indicates undefined operation code
|
||||
* HL_NOTIFIER_EVENT_DEVICE_RESET - Indicates device requires a reset
|
||||
*/
|
||||
#define HL_NOTIFIER_EVENT_TPC_ASSERT (1 << 0)
|
||||
#define HL_NOTIFIER_EVENT_TPC_ASSERT (1ULL << 0)
|
||||
#define HL_NOTIFIER_EVENT_UNDEFINED_OPCODE (1ULL << 1)
|
||||
#define HL_NOTIFIER_EVENT_DEVICE_RESET (1ULL << 2)
|
||||
|
||||
/*
|
||||
* Various information operations such as:
|
||||
|
||||
Loading…
Reference in New Issue
Block a user