ptp: Add clock driver for the OpenCompute TimeCard.
The OpenCompute time card is an atomic clock along with a GPS receiver that provides a Grandmaster clock source for a PTP enabled network. More information is available at http://www.timingcard.com/ Signed-off-by: Jonathan Lemon <jonathan.lemon@gmail.com> Acked-by: Richard Cochran <richardcochran@gmail.com> Link: https://lore.kernel.org/r/20201204035128.2219252-2-jonathan.lemon@gmail.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Jonathan Lemon
Jakub Kicinski
parent
bcd684aace
commit
a7e1abad13
@ -151,4 +151,18 @@ config PTP_1588_CLOCK_VMW
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To compile this driver as a module, choose M here: the module
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will be called ptp_vmw.
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config PTP_1588_CLOCK_OCP
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tristate "OpenCompute TimeCard as PTP clock"
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depends on PTP_1588_CLOCK
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depends on HAS_IOMEM && PCI
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default n
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help
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This driver adds support for an OpenCompute time card.
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The OpenCompute time card is an atomic clock along with
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a GPS receiver that provides a Grandmaster clock source
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for a PTP enabled network.
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More information is available at http://www.timingcard.com/
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endmenu
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@ -15,3 +15,4 @@ ptp-qoriq-$(CONFIG_DEBUG_FS) += ptp_qoriq_debugfs.o
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obj-$(CONFIG_PTP_1588_CLOCK_IDTCM) += ptp_clockmatrix.o
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obj-$(CONFIG_PTP_1588_CLOCK_IDT82P33) += ptp_idt82p33.o
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obj-$(CONFIG_PTP_1588_CLOCK_VMW) += ptp_vmw.o
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obj-$(CONFIG_PTP_1588_CLOCK_OCP) += ptp_ocp.o
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398
drivers/ptp/ptp_ocp.c
Normal file
398
drivers/ptp/ptp_ocp.c
Normal file
@ -0,0 +1,398 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/* Copyright (c) 2020 Facebook */
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#include <linux/err.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/pci.h>
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#include <linux/ptp_clock_kernel.h>
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static const struct pci_device_id ptp_ocp_pcidev_id[] = {
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{ PCI_DEVICE(0x1d9b, 0x0400) },
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{ 0 }
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};
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MODULE_DEVICE_TABLE(pci, ptp_ocp_pcidev_id);
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#define OCP_REGISTER_OFFSET 0x01000000
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struct ocp_reg {
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u32 ctrl;
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u32 status;
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u32 select;
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u32 version;
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u32 time_ns;
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u32 time_sec;
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u32 __pad0[2];
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u32 adjust_ns;
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u32 adjust_sec;
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u32 __pad1[2];
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u32 offset_ns;
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u32 offset_window_ns;
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};
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#define OCP_CTRL_ENABLE BIT(0)
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#define OCP_CTRL_ADJUST_TIME BIT(1)
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#define OCP_CTRL_ADJUST_OFFSET BIT(2)
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#define OCP_CTRL_READ_TIME_REQ BIT(30)
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#define OCP_CTRL_READ_TIME_DONE BIT(31)
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#define OCP_STATUS_IN_SYNC BIT(0)
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#define OCP_SELECT_CLK_NONE 0
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#define OCP_SELECT_CLK_REG 6
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struct tod_reg {
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u32 ctrl;
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u32 status;
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u32 uart_polarity;
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u32 version;
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u32 correction_sec;
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u32 __pad0[3];
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u32 uart_baud;
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u32 __pad1[3];
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u32 utc_status;
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u32 leap;
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};
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#define TOD_REGISTER_OFFSET 0x01050000
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#define TOD_CTRL_PROTOCOL BIT(28)
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#define TOD_CTRL_DISABLE_FMT_A BIT(17)
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#define TOD_CTRL_DISABLE_FMT_B BIT(16)
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#define TOD_CTRL_ENABLE BIT(0)
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#define TOD_CTRL_GNSS_MASK ((1U << 4) - 1)
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#define TOD_CTRL_GNSS_SHIFT 24
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#define TOD_STATUS_UTC_MASK 0xff
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#define TOD_STATUS_UTC_VALID BIT(8)
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#define TOD_STATUS_LEAP_VALID BIT(16)
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struct ptp_ocp {
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struct pci_dev *pdev;
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spinlock_t lock;
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void __iomem *base;
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struct ocp_reg __iomem *reg;
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struct tod_reg __iomem *tod;
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struct ptp_clock *ptp;
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struct ptp_clock_info ptp_info;
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};
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static int
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__ptp_ocp_gettime_locked(struct ptp_ocp *bp, struct timespec64 *ts,
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struct ptp_system_timestamp *sts)
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{
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u32 ctrl, time_sec, time_ns;
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int i;
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ctrl = ioread32(&bp->reg->ctrl);
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ctrl |= OCP_CTRL_READ_TIME_REQ;
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ptp_read_system_prets(sts);
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iowrite32(ctrl, &bp->reg->ctrl);
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for (i = 0; i < 100; i++) {
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ctrl = ioread32(&bp->reg->ctrl);
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if (ctrl & OCP_CTRL_READ_TIME_DONE)
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break;
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}
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ptp_read_system_postts(sts);
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time_ns = ioread32(&bp->reg->time_ns);
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time_sec = ioread32(&bp->reg->time_sec);
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ts->tv_sec = time_sec;
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ts->tv_nsec = time_ns;
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return ctrl & OCP_CTRL_READ_TIME_DONE ? 0 : -ETIMEDOUT;
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}
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static int
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ptp_ocp_gettimex(struct ptp_clock_info *ptp_info, struct timespec64 *ts,
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struct ptp_system_timestamp *sts)
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{
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struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info);
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unsigned long flags;
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int err;
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spin_lock_irqsave(&bp->lock, flags);
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err = __ptp_ocp_gettime_locked(bp, ts, sts);
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spin_unlock_irqrestore(&bp->lock, flags);
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return err;
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}
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static void
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__ptp_ocp_settime_locked(struct ptp_ocp *bp, const struct timespec64 *ts)
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{
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u32 ctrl, time_sec, time_ns;
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u32 select;
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time_ns = ts->tv_nsec;
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time_sec = ts->tv_sec;
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select = ioread32(&bp->reg->select);
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iowrite32(OCP_SELECT_CLK_REG, &bp->reg->select);
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iowrite32(time_ns, &bp->reg->adjust_ns);
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iowrite32(time_sec, &bp->reg->adjust_sec);
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ctrl = ioread32(&bp->reg->ctrl);
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ctrl |= OCP_CTRL_ADJUST_TIME;
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iowrite32(ctrl, &bp->reg->ctrl);
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/* restore clock selection */
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iowrite32(select >> 16, &bp->reg->select);
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}
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static int
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ptp_ocp_settime(struct ptp_clock_info *ptp_info, const struct timespec64 *ts)
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{
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struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info);
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unsigned long flags;
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if (ioread32(&bp->reg->status) & OCP_STATUS_IN_SYNC)
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return 0;
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spin_lock_irqsave(&bp->lock, flags);
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__ptp_ocp_settime_locked(bp, ts);
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spin_unlock_irqrestore(&bp->lock, flags);
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return 0;
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}
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static int
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ptp_ocp_adjtime(struct ptp_clock_info *ptp_info, s64 delta_ns)
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{
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struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info);
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struct timespec64 ts;
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unsigned long flags;
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int err;
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if (ioread32(&bp->reg->status) & OCP_STATUS_IN_SYNC)
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return 0;
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spin_lock_irqsave(&bp->lock, flags);
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err = __ptp_ocp_gettime_locked(bp, &ts, NULL);
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if (likely(!err)) {
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timespec64_add_ns(&ts, delta_ns);
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__ptp_ocp_settime_locked(bp, &ts);
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}
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spin_unlock_irqrestore(&bp->lock, flags);
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return err;
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}
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static int
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ptp_ocp_null_adjfine(struct ptp_clock_info *ptp_info, long scaled_ppm)
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{
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if (scaled_ppm == 0)
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return 0;
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return -EOPNOTSUPP;
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}
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static const struct ptp_clock_info ptp_ocp_clock_info = {
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.owner = THIS_MODULE,
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.name = KBUILD_MODNAME,
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.max_adj = 100000000,
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.gettimex64 = ptp_ocp_gettimex,
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.settime64 = ptp_ocp_settime,
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.adjtime = ptp_ocp_adjtime,
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.adjfine = ptp_ocp_null_adjfine,
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};
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static int
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ptp_ocp_check_clock(struct ptp_ocp *bp)
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{
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struct timespec64 ts;
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bool sync;
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u32 ctrl;
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/* make sure clock is enabled */
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ctrl = ioread32(&bp->reg->ctrl);
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ctrl |= OCP_CTRL_ENABLE;
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iowrite32(ctrl, &bp->reg->ctrl);
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if ((ioread32(&bp->reg->ctrl) & OCP_CTRL_ENABLE) == 0) {
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dev_err(&bp->pdev->dev, "clock not enabled\n");
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return -ENODEV;
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}
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sync = ioread32(&bp->reg->status) & OCP_STATUS_IN_SYNC;
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if (!sync) {
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ktime_get_real_ts64(&ts);
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ptp_ocp_settime(&bp->ptp_info, &ts);
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}
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if (!ptp_ocp_gettimex(&bp->ptp_info, &ts, NULL))
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dev_info(&bp->pdev->dev, "Time: %lld.%ld, %s\n",
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ts.tv_sec, ts.tv_nsec,
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sync ? "in-sync" : "UNSYNCED");
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return 0;
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}
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static void
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ptp_ocp_tod_info(struct ptp_ocp *bp)
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{
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static const char * const proto_name[] = {
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"NMEA", "NMEA_ZDA", "NMEA_RMC", "NMEA_none",
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"UBX", "UBX_UTC", "UBX_LS", "UBX_none"
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};
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static const char * const gnss_name[] = {
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"ALL", "COMBINED", "GPS", "GLONASS", "GALILEO", "BEIDOU",
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};
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u32 version, ctrl, reg;
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int idx;
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version = ioread32(&bp->tod->version);
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dev_info(&bp->pdev->dev, "TOD Version %d.%d.%d\n",
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version >> 24, (version >> 16) & 0xff, version & 0xffff);
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ctrl = ioread32(&bp->tod->ctrl);
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ctrl |= TOD_CTRL_PROTOCOL | TOD_CTRL_ENABLE;
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ctrl &= ~(TOD_CTRL_DISABLE_FMT_A | TOD_CTRL_DISABLE_FMT_B);
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iowrite32(ctrl, &bp->tod->ctrl);
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ctrl = ioread32(&bp->tod->ctrl);
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idx = ctrl & TOD_CTRL_PROTOCOL ? 4 : 0;
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idx += (ctrl >> 16) & 3;
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dev_info(&bp->pdev->dev, "control: %x\n", ctrl);
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dev_info(&bp->pdev->dev, "TOD Protocol %s %s\n", proto_name[idx],
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ctrl & TOD_CTRL_ENABLE ? "enabled" : "");
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idx = (ctrl >> TOD_CTRL_GNSS_SHIFT) & TOD_CTRL_GNSS_MASK;
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if (idx < ARRAY_SIZE(gnss_name))
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dev_info(&bp->pdev->dev, "GNSS %s\n", gnss_name[idx]);
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reg = ioread32(&bp->tod->status);
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dev_info(&bp->pdev->dev, "status: %x\n", reg);
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reg = ioread32(&bp->tod->correction_sec);
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dev_info(&bp->pdev->dev, "correction: %d\n", reg);
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reg = ioread32(&bp->tod->utc_status);
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dev_info(&bp->pdev->dev, "utc_status: %x\n", reg);
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dev_info(&bp->pdev->dev, "utc_offset: %d valid:%d leap_valid:%d\n",
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reg & TOD_STATUS_UTC_MASK, reg & TOD_STATUS_UTC_VALID ? 1 : 0,
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reg & TOD_STATUS_LEAP_VALID ? 1 : 0);
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}
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static void
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ptp_ocp_info(struct ptp_ocp *bp)
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{
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static const char * const clock_name[] = {
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"NO", "TOD", "IRIG", "PPS", "PTP", "RTC", "REGS", "EXT"
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};
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u32 version, select;
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version = ioread32(&bp->reg->version);
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select = ioread32(&bp->reg->select);
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dev_info(&bp->pdev->dev, "Version %d.%d.%d, clock %s, device ptp%d\n",
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version >> 24, (version >> 16) & 0xff, version & 0xffff,
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clock_name[select & 7],
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ptp_clock_index(bp->ptp));
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ptp_ocp_tod_info(bp);
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}
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static int
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ptp_ocp_probe(struct pci_dev *pdev, const struct pci_device_id *id)
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{
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struct ptp_ocp *bp;
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int err;
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bp = kzalloc(sizeof(*bp), GFP_KERNEL);
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if (!bp)
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return -ENOMEM;
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bp->pdev = pdev;
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pci_set_drvdata(pdev, bp);
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err = pci_enable_device(pdev);
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if (err) {
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dev_err(&pdev->dev, "pci_enable_device\n");
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goto out_free;
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}
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err = pci_request_regions(pdev, KBUILD_MODNAME);
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if (err) {
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dev_err(&pdev->dev, "pci_request_region\n");
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goto out_disable;
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}
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bp->base = pci_ioremap_bar(pdev, 0);
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if (!bp->base) {
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dev_err(&pdev->dev, "io_remap bar0\n");
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err = -ENOMEM;
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goto out;
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}
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bp->reg = bp->base + OCP_REGISTER_OFFSET;
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bp->tod = bp->base + TOD_REGISTER_OFFSET;
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bp->ptp_info = ptp_ocp_clock_info;
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spin_lock_init(&bp->lock);
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err = ptp_ocp_check_clock(bp);
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if (err)
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goto out;
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bp->ptp = ptp_clock_register(&bp->ptp_info, &pdev->dev);
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if (IS_ERR(bp->ptp)) {
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dev_err(&pdev->dev, "ptp_clock_register\n");
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err = PTR_ERR(bp->ptp);
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goto out;
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}
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ptp_ocp_info(bp);
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return 0;
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out:
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pci_release_regions(pdev);
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out_disable:
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pci_disable_device(pdev);
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out_free:
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kfree(bp);
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return err;
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}
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static void
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ptp_ocp_remove(struct pci_dev *pdev)
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{
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struct ptp_ocp *bp = pci_get_drvdata(pdev);
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ptp_clock_unregister(bp->ptp);
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pci_iounmap(pdev, bp->base);
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pci_release_regions(pdev);
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pci_disable_device(pdev);
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pci_set_drvdata(pdev, NULL);
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kfree(bp);
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}
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static struct pci_driver ptp_ocp_driver = {
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.name = KBUILD_MODNAME,
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.id_table = ptp_ocp_pcidev_id,
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.probe = ptp_ocp_probe,
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.remove = ptp_ocp_remove,
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};
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static int __init
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ptp_ocp_init(void)
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{
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int err;
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err = pci_register_driver(&ptp_ocp_driver);
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return err;
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}
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static void __exit
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ptp_ocp_fini(void)
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{
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pci_unregister_driver(&ptp_ocp_driver);
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}
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module_init(ptp_ocp_init);
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module_exit(ptp_ocp_fini);
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MODULE_DESCRIPTION("OpenCompute TimeCard driver");
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MODULE_LICENSE("GPL v2");
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