From 06668b6f7d5b0bdbda30673785d7540c72caae17 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 10 Feb 2023 17:38:43 +0100 Subject: [PATCH 01/28] dt-bindings: arm: qcom: add QRD8550 Add board compatible for QRD8550 - a mobile-like development board with SM8550. Signed-off-by: Krzysztof Kozlowski Acked-by: Rob Herring Reviewed-by: Abel Vesa Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230210163844.765074-1-krzysztof.kozlowski@linaro.org --- Documentation/devicetree/bindings/arm/qcom.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 1bb24d46e4ee..23c9c9ba5d52 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -913,6 +913,7 @@ properties: - items: - enum: - qcom,sm8550-mtp + - qcom,sm8550-qrd - const: qcom,sm8550 # Board compatibles go above From 131731c44f2cea44135e93bfb0a2920829910625 Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Tue, 14 Feb 2023 17:12:08 +0100 Subject: [PATCH 02/28] ARM: dts: qcom: ipq4018-ap120c-ac: setup serial console Add the required alias and stdout property so that kernel can setup the console based off DTS and not have to set it in the cmdline. Signed-off-by: Robert Marko Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230214161211.306462-1-robert.marko@sartura.hr --- arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dtsi b/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dtsi index a5a6f3ebb274..38efd45433da 100644 --- a/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dtsi @@ -8,6 +8,14 @@ model = "ALFA Network AP120C-AC"; compatible = "alfa-network,ap120c-ac", "qcom,ipq4018"; + aliases { + serial0 = &blsp1_uart1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + keys { compatible = "gpio-keys"; From a7d2715df2845560302aea9d9922b4bfdf4fe09a Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Tue, 14 Feb 2023 17:12:09 +0100 Subject: [PATCH 03/28] ARM: dts: qcom: ipq4018-ap120c-ac: align GPIO hog with DT schema Align USB power GPIO hog node to DT schema. Signed-off-by: Robert Marko Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230214161211.306462-2-robert.marko@sartura.hr --- arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dtsi b/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dtsi index 38efd45433da..cd2a32d0d554 100644 --- a/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dtsi @@ -76,7 +76,7 @@ }; }; - usb-power { + usb-power-hog { line-name = "USB-power"; gpios = <1 GPIO_ACTIVE_HIGH>; gpio-hog; From fabc476a6cff40119365014e84aa2d2bbdf7756a Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Tue, 14 Feb 2023 17:12:10 +0100 Subject: [PATCH 04/28] ARM: dts: qcom: ipq4018-ap120c-ac: align SPI-NAND with DT schema SPI-NAND node name should be flash@1 and not nand@1 according to schema. Signed-off-by: Robert Marko Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230214161211.306462-3-robert.marko@sartura.hr --- arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dtsi b/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dtsi index cd2a32d0d554..bb0c888b048e 100644 --- a/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dtsi @@ -186,7 +186,7 @@ }; }; - nand@1 { + flash@1 { compatible = "spi-nand"; reg = <1>; spi-max-frequency = <40000000>; From d64f94249c689962b895aa650a30c29ac3b41cd3 Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Tue, 14 Feb 2023 17:12:11 +0100 Subject: [PATCH 05/28] ARM: dts: qcom: ipq4018-ap120c-ac: use NVMEM for ath10k caldata Since ath10k now supports loading the pre-cal via NVMEM instead of having to use userspace scripts, lets use it. Signed-off-by: Robert Marko Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230214161211.306462-4-robert.marko@sartura.hr --- arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dtsi b/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dtsi index bb0c888b048e..d90b4f4c63af 100644 --- a/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dtsi @@ -170,6 +170,17 @@ label = "ART"; reg = <0x00170000 0x00010000>; read-only; + compatible = "nvmem-cells"; + #address-cells = <1>; + #size-cells = <1>; + + precal_art_1000: precal@1000 { + reg = <0x1000 0x2f20>; + }; + + precal_art_5000: precal@5000 { + reg = <0x5000 0x2f20>; + }; }; partition@180000 { @@ -233,10 +244,14 @@ &wifi0 { status = "okay"; + nvmem-cell-names = "pre-calibration"; + nvmem-cells = <&precal_art_1000>; }; &wifi1 { status = "okay"; + nvmem-cell-names = "pre-calibration"; + nvmem-cells = <&precal_art_5000>; qcom,ath10k-calibration-variant = "ALFA-Network-AP120C-AC"; }; From 66e4811ab3967332c52a72f04d615f0faabb145e Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Tue, 14 Feb 2023 17:23:21 +0100 Subject: [PATCH 06/28] ARM: dts: qcom: ipq4019: pass XO and sleep clocks to GCC Directly pass XO and sleep clocks to GCC via phandles. Signed-off-by: Robert Marko Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230214162325.312057-3-robert.marko@sartura.hr --- arch/arm/boot/dts/qcom-ipq4019.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi index 02e9ea78405d..6aaa6da5498d 100644 --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi @@ -190,6 +190,8 @@ #power-domain-cells = <1>; #reset-cells = <1>; reg = <0x1800000 0x60000>; + clocks = <&xo>, <&sleep_clk>; + clock-names = "xo", "sleep_clk"; }; prng: rng@22000 { From 2a41c611f21751150cf4c0132a02828700e58e2d Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Tue, 14 Feb 2023 17:23:22 +0100 Subject: [PATCH 07/28] ARM: dts: qcom: ipq4019: remove clk-output-names for sleep clock Now that sleep clock is being passed directly to GCC, there is no need for global name matching, so remove clk-output-names for sleep clock. Signed-off-by: Robert Marko Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230214162325.312057-4-robert.marko@sartura.hr --- arch/arm/boot/dts/qcom-ipq4019.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi index 6aaa6da5498d..44beeb90c306 100644 --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi @@ -143,7 +143,6 @@ sleep_clk: sleep_clk { compatible = "fixed-clock"; clock-frequency = <32000>; - clock-output-names = "gcc_sleep_clk_src"; #clock-cells = <0>; }; From b9745c275246a7e43c34d1b3be5ff9a9f3cf9305 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 20 Feb 2023 13:08:31 +0100 Subject: [PATCH 08/28] ARM: dts: qcom-apq8064: Fix opp table child name The opp-320000000 name is rather misleading with the opp-hz value of 450 MHz. Fix it! Fixes: 8db0b6c7b636 ("ARM: dts: qcom: apq8064: Convert adreno from legacy gpu-pwrlevels to opp-v2") Signed-off-by: Konrad Dybcio Reviewed-by: David Heidelberg Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230220120831.1591820-1-konrad.dybcio@linaro.org --- arch/arm/boot/dts/qcom-apq8064.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index 92aa2b081901..3aeac0cabb28 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -1260,7 +1260,7 @@ gpu_opp_table: opp-table { compatible = "operating-points-v2"; - opp-320000000 { + opp-450000000 { opp-hz = /bits/ 64 <450000000>; }; From 5d092236e0b0e154ca5f4f65d33eea504cc18578 Mon Sep 17 00:00:00 2001 From: Kathiravan T Date: Tue, 7 Mar 2023 11:52:29 +0530 Subject: [PATCH 09/28] dt-bindings: qcom: add ipq5332 boards Document the new ipq5332 SoC/board device tree bindings Reviewed-by: Krzysztof Kozlowski Signed-off-by: Kathiravan T Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230307062232.4889-7-quic_kathirav@quicinc.com --- Documentation/devicetree/bindings/arm/qcom.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 23c9c9ba5d52..014ed8d5ba18 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -30,6 +30,7 @@ description: | apq8084 apq8096 ipq4018 + ipq5332 ipq6018 ipq8074 mdm9615 @@ -80,6 +81,7 @@ description: | The 'board' element must be one of the following strings: adp + ap-mi01.2 cdp cp01-c1 dragonboard @@ -320,6 +322,11 @@ properties: - qcom,ipq4019-dk04.1-c1 - const: qcom,ipq4019 + - items: + - enum: + - qcom,ipq5332-ap-mi01.2 + - const: qcom,ipq5332 + - items: - enum: - mikrotik,rb3011 From b74ca4a0e3043af06819905306e05189f337466a Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Mon, 16 Jan 2023 21:47:48 +0100 Subject: [PATCH 10/28] ARM: dts: qcom: add per SoC compatible for qcom,kpss-gcc nodes Add per Soc compatible for qcom,kpss-gcc nodes. While currently not used by the kpss driver they can serve further customization and they are required to be defined per Documentation schema. Signed-off-by: Christian Marangi Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230116204751.23045-5-ansuelsmth@gmail.com --- arch/arm/boot/dts/qcom-apq8064.dtsi | 2 +- arch/arm/boot/dts/qcom-ipq8064.dtsi | 2 +- arch/arm/boot/dts/qcom-mdm9615.dtsi | 2 +- arch/arm/boot/dts/qcom-msm8660.dtsi | 2 +- arch/arm/boot/dts/qcom-msm8960.dtsi | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index 3aeac0cabb28..6ebf33e2e699 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -879,7 +879,7 @@ }; l2cc: clock-controller@2011000 { - compatible = "qcom,kpss-gcc", "syscon"; + compatible = "qcom,kpss-gcc-apq8064", "qcom,kpss-gcc", "syscon"; reg = <0x2011000 0x1000>; }; diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi index 52d77e105957..6e49b54f53d7 100644 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi @@ -569,7 +569,7 @@ }; l2cc: clock-controller@2011000 { - compatible = "qcom,kpss-gcc", "syscon"; + compatible = "qcom,kpss-gcc-ipq8064", "qcom,kpss-gcc", "syscon"; reg = <0x02011000 0x1000>; clocks = <&gcc PLL8_VOTE>, <&pxo_board>; clock-names = "pll8_vote", "pxo"; diff --git a/arch/arm/boot/dts/qcom-mdm9615.dtsi b/arch/arm/boot/dts/qcom-mdm9615.dtsi index 8e9ea61a1e48..b40c52ddf9b4 100644 --- a/arch/arm/boot/dts/qcom-mdm9615.dtsi +++ b/arch/arm/boot/dts/qcom-mdm9615.dtsi @@ -116,7 +116,7 @@ }; l2cc: clock-controller@2011000 { - compatible = "qcom,kpss-gcc", "syscon"; + compatible = "qcom,kpss-gcc-mdm9615", "qcom,kpss-gcc", "syscon"; reg = <0x02011000 0x1000>; }; diff --git a/arch/arm/boot/dts/qcom-msm8660.dtsi b/arch/arm/boot/dts/qcom-msm8660.dtsi index 86f76d0feff4..f601b40ebcf4 100644 --- a/arch/arm/boot/dts/qcom-msm8660.dtsi +++ b/arch/arm/boot/dts/qcom-msm8660.dtsi @@ -473,7 +473,7 @@ }; l2cc: clock-controller@2082000 { - compatible = "qcom,kpss-gcc", "syscon"; + compatible = "qcom,kpss-gcc-msm8660", "qcom,kpss-gcc", "syscon"; reg = <0x02082000 0x1000>; }; diff --git a/arch/arm/boot/dts/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom-msm8960.dtsi index a0369b38fe07..4fdbb867532c 100644 --- a/arch/arm/boot/dts/qcom-msm8960.dtsi +++ b/arch/arm/boot/dts/qcom-msm8960.dtsi @@ -182,7 +182,7 @@ }; l2cc: clock-controller@2011000 { - compatible = "qcom,kpss-gcc", "syscon"; + compatible = "qcom,kpss-gcc-msm8960", "qcom,kpss-gcc", "syscon"; reg = <0x2011000 0x1000>; }; From a9e6d16ad493529da4a48d7ae474ecdc399ee884 Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Mon, 16 Jan 2023 21:47:49 +0100 Subject: [PATCH 11/28] ARM: dts: qcom: add and fix clock configuration for kpss-gcc nodes Add missing clock configuration by adding clocks, clock-names and #clock-cells bindings for each kpss-acc-v1 clock-controller node for apq8064 and msm8960 to reflect Documentation schema. Add missing #clock-cells binding and remove useless clock-output-names for ipq806x dtsi. Signed-off-by: Christian Marangi Reviewed-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230116204751.23045-6-ansuelsmth@gmail.com --- arch/arm/boot/dts/qcom-apq8064.dtsi | 3 +++ arch/arm/boot/dts/qcom-ipq8064.dtsi | 2 +- arch/arm/boot/dts/qcom-msm8960.dtsi | 3 +++ 3 files changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index 6ebf33e2e699..70d6ed1ac62c 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -881,6 +881,9 @@ l2cc: clock-controller@2011000 { compatible = "qcom,kpss-gcc-apq8064", "qcom,kpss-gcc", "syscon"; reg = <0x2011000 0x1000>; + clocks = <&gcc PLL8_VOTE>, <&pxo_board>; + clock-names = "pll8_vote", "pxo"; + #clock-cells = <0>; }; rpm: rpm@108000 { diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi index 6e49b54f53d7..e45da8f01ba0 100644 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi @@ -573,7 +573,7 @@ reg = <0x02011000 0x1000>; clocks = <&gcc PLL8_VOTE>, <&pxo_board>; clock-names = "pll8_vote", "pxo"; - clock-output-names = "acpu_l2_aux"; + #clock-cells = <0>; }; acc0: clock-controller@2088000 { diff --git a/arch/arm/boot/dts/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom-msm8960.dtsi index 4fdbb867532c..026480efe8ec 100644 --- a/arch/arm/boot/dts/qcom-msm8960.dtsi +++ b/arch/arm/boot/dts/qcom-msm8960.dtsi @@ -184,6 +184,9 @@ l2cc: clock-controller@2011000 { compatible = "qcom,kpss-gcc-msm8960", "qcom,kpss-gcc", "syscon"; reg = <0x2011000 0x1000>; + clocks = <&gcc PLL8_VOTE>, <&pxo_board>; + clock-names = "pll8_vote", "pxo"; + #clock-cells = <0>; }; rpm: rpm@108000 { From 6b20edd72930d83e9c2c2017df883b3c5c1502fd Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Mon, 16 Jan 2023 21:47:50 +0100 Subject: [PATCH 12/28] ARM: dts: qcom: add missing clock configuration for kpss-acc-v1 Add missing clock configuration by adding clocks, clock-names, clock-output-names and #clock-cells bindings for each kpss-acc-v1 clock-controller to reflect Documentation schema. Reviewed-by: Dmitry Baryshkov Signed-off-by: Christian Marangi Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230116204751.23045-7-ansuelsmth@gmail.com --- arch/arm/boot/dts/qcom-apq8064.dtsi | 16 ++++++++++++++++ arch/arm/boot/dts/qcom-ipq8064.dtsi | 8 ++++++++ arch/arm/boot/dts/qcom-msm8960.dtsi | 8 ++++++++ 3 files changed, 32 insertions(+) diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index 70d6ed1ac62c..920d318da266 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -388,21 +388,37 @@ acc0: clock-controller@2088000 { compatible = "qcom,kpss-acc-v1"; reg = <0x02088000 0x1000>, <0x02008000 0x1000>; + clocks = <&gcc PLL8_VOTE>, <&pxo_board>; + clock-names = "pll8_vote", "pxo"; + clock-output-names = "acpu0_aux"; + #clock-cells = <0>; }; acc1: clock-controller@2098000 { compatible = "qcom,kpss-acc-v1"; reg = <0x02098000 0x1000>, <0x02008000 0x1000>; + clocks = <&gcc PLL8_VOTE>, <&pxo_board>; + clock-names = "pll8_vote", "pxo"; + clock-output-names = "acpu1_aux"; + #clock-cells = <0>; }; acc2: clock-controller@20a8000 { compatible = "qcom,kpss-acc-v1"; reg = <0x020a8000 0x1000>, <0x02008000 0x1000>; + clocks = <&gcc PLL8_VOTE>, <&pxo_board>; + clock-names = "pll8_vote", "pxo"; + clock-output-names = "acpu2_aux"; + #clock-cells = <0>; }; acc3: clock-controller@20b8000 { compatible = "qcom,kpss-acc-v1"; reg = <0x020b8000 0x1000>, <0x02008000 0x1000>; + clocks = <&gcc PLL8_VOTE>, <&pxo_board>; + clock-names = "pll8_vote", "pxo"; + clock-output-names = "acpu3_aux"; + #clock-cells = <0>; }; saw0: power-controller@2089000 { diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi index e45da8f01ba0..5a464f6de0b6 100644 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi @@ -579,6 +579,10 @@ acc0: clock-controller@2088000 { compatible = "qcom,kpss-acc-v1"; reg = <0x02088000 0x1000>, <0x02008000 0x1000>; + clocks = <&gcc PLL8_VOTE>, <&pxo_board>; + clock-names = "pll8_vote", "pxo"; + clock-output-names = "acpu0_aux"; + #clock-cells = <0>; }; saw0: regulator@2089000 { @@ -590,6 +594,10 @@ acc1: clock-controller@2098000 { compatible = "qcom,kpss-acc-v1"; reg = <0x02098000 0x1000>, <0x02008000 0x1000>; + clocks = <&gcc PLL8_VOTE>, <&pxo_board>; + clock-names = "pll8_vote", "pxo"; + clock-output-names = "acpu1_aux"; + #clock-cells = <0>; }; saw1: regulator@2099000 { diff --git a/arch/arm/boot/dts/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom-msm8960.dtsi index 026480efe8ec..2a668cd535cc 100644 --- a/arch/arm/boot/dts/qcom-msm8960.dtsi +++ b/arch/arm/boot/dts/qcom-msm8960.dtsi @@ -207,11 +207,19 @@ acc0: clock-controller@2088000 { compatible = "qcom,kpss-acc-v1"; reg = <0x02088000 0x1000>, <0x02008000 0x1000>; + clocks = <&gcc PLL8_VOTE>, <&pxo_board>; + clock-names = "pll8_vote", "pxo"; + clock-output-names = "acpu0_aux"; + #clock-cells = <0>; }; acc1: clock-controller@2098000 { compatible = "qcom,kpss-acc-v1"; reg = <0x02098000 0x1000>, <0x02008000 0x1000>; + clocks = <&gcc PLL8_VOTE>, <&pxo_board>; + clock-names = "pll8_vote", "pxo"; + clock-output-names = "acpu1_aux"; + #clock-cells = <0>; }; saw0: regulator@2089000 { From 158ce4b3e1dfcf3e38c0dbfd626aee0f1bbfa3d1 Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Mon, 16 Jan 2023 21:47:51 +0100 Subject: [PATCH 13/28] ARM: dts: qcom: rename kpss-acc-v2 nodes to power-manager nodes Change kpss-acc-v2 nodes naming to power-manager to reflect Documentation schema. Signed-off-by: Christian Marangi Reviewed-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230116204751.23045-8-ansuelsmth@gmail.com --- arch/arm/boot/dts/qcom-apq8084.dtsi | 8 ++++---- arch/arm/boot/dts/qcom-ipq4019.dtsi | 8 ++++---- arch/arm/boot/dts/qcom-msm8974.dtsi | 8 ++++---- 3 files changed, 12 insertions(+), 12 deletions(-) diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom-apq8084.dtsi index fabd7455eb8f..b653ea40c441 100644 --- a/arch/arm/boot/dts/qcom-apq8084.dtsi +++ b/arch/arm/boot/dts/qcom-apq8084.dtsi @@ -654,25 +654,25 @@ regulator; }; - acc0: clock-controller@f9088000 { + acc0: power-manager@f9088000 { compatible = "qcom,kpss-acc-v2"; reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>; }; - acc1: clock-controller@f9098000 { + acc1: power-manager@f9098000 { compatible = "qcom,kpss-acc-v2"; reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>; }; - acc2: clock-controller@f90a8000 { + acc2: power-manager@f90a8000 { compatible = "qcom,kpss-acc-v2"; reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>; }; - acc3: clock-controller@f90b8000 { + acc3: power-manager@f90b8000 { compatible = "qcom,kpss-acc-v2"; reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>; diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi index 44beeb90c306..9595229c4f0d 100644 --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi @@ -326,22 +326,22 @@ status = "disabled"; }; - acc0: clock-controller@b088000 { + acc0: power-manager@b088000 { compatible = "qcom,kpss-acc-v2"; reg = <0x0b088000 0x1000>, <0xb008000 0x1000>; }; - acc1: clock-controller@b098000 { + acc1: power-manager@b098000 { compatible = "qcom,kpss-acc-v2"; reg = <0x0b098000 0x1000>, <0xb008000 0x1000>; }; - acc2: clock-controller@b0a8000 { + acc2: power-manager@b0a8000 { compatible = "qcom,kpss-acc-v2"; reg = <0x0b0a8000 0x1000>, <0xb008000 0x1000>; }; - acc3: clock-controller@b0b8000 { + acc3: power-manager@b0b8000 { compatible = "qcom,kpss-acc-v2"; reg = <0x0b0b8000 0x1000>, <0xb008000 0x1000>; }; diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index 834ad95515b1..23104193f63a 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -418,22 +418,22 @@ regulator; }; - acc0: clock-controller@f9088000 { + acc0: power-manager@f9088000 { compatible = "qcom,kpss-acc-v2"; reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>; }; - acc1: clock-controller@f9098000 { + acc1: power-manager@f9098000 { compatible = "qcom,kpss-acc-v2"; reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>; }; - acc2: clock-controller@f90a8000 { + acc2: power-manager@f90a8000 { compatible = "qcom,kpss-acc-v2"; reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>; }; - acc3: clock-controller@f90b8000 { + acc3: power-manager@f90b8000 { compatible = "qcom,kpss-acc-v2"; reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>; }; From d4b2c596fe5cb62560ce5a1442d8f64ec1ee716e Mon Sep 17 00:00:00 2001 From: Rayyan Ansari Date: Sat, 21 Jan 2023 19:25:39 +0000 Subject: [PATCH 14/28] ARM: dts: qcom: msm8226: add clocks and clock-names to GCC node Add the XO and Sleep Clock sources to the GCC node on MSM8226. Signed-off-by: Rayyan Ansari Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230121192540.9177-3-rayyan@ansari.sh --- arch/arm/boot/dts/qcom-msm8226.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/qcom-msm8226.dtsi b/arch/arm/boot/dts/qcom-msm8226.dtsi index c373081bc21b..42acb9ddb8cc 100644 --- a/arch/arm/boot/dts/qcom-msm8226.dtsi +++ b/arch/arm/boot/dts/qcom-msm8226.dtsi @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -377,6 +378,11 @@ #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; + + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&sleep_clk>; + clock-names = "xo", + "sleep_clk"; }; mmcc: clock-controller@fd8c0000 { From 17c5ee1914dc8c4f42cab7a5beb2dc91aef0f873 Mon Sep 17 00:00:00 2001 From: Rayyan Ansari Date: Sat, 21 Jan 2023 19:25:40 +0000 Subject: [PATCH 15/28] ARM: dts: qcom: msm8974: add correct XO clock source to GCC node Change the XO clock in MSM8974's GCC node to point to RPMCC. Signed-off-by: Rayyan Ansari Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230121192540.9177-4-rayyan@ansari.sh --- arch/arm/boot/dts/qcom-msm8974.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index 23104193f63a..8208012684d4 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -1057,7 +1057,7 @@ #power-domain-cells = <1>; reg = <0xfc400000 0x4000>; - clocks = <&xo_board>, + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>; clock-names = "xo", "sleep_clk"; From 64d5c8a46890010e7cf5a72c0616d1141f84494f Mon Sep 17 00:00:00 2001 From: Devi Priya Date: Tue, 14 Feb 2023 22:01:14 +0530 Subject: [PATCH 16/28] dt-bindings: arm: qcom: Add ipq9574 compatible Document the new ipq9574 SoC/board device tree bindings Acked-by: Krzysztof Kozlowski Signed-off-by: Devi Priya Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230214163116.9924-6-quic_devipriy@quicinc.com --- Documentation/devicetree/bindings/arm/qcom.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 014ed8d5ba18..05badce5fedc 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -33,6 +33,7 @@ description: | ipq5332 ipq6018 ipq8074 + ipq9574 mdm9615 msm8226 msm8916 @@ -81,6 +82,7 @@ description: | The 'board' element must be one of the following strings: adp + ap-al02-c7 ap-mi01.2 cdp cp01-c1 @@ -340,6 +342,11 @@ properties: - qcom,ipq8074-hk10-c2 - const: qcom,ipq8074 + - items: + - enum: + - qcom,ipq9574-ap-al02-c7 + - const: qcom,ipq9574 + - description: Sierra Wireless MangOH Green with WP8548 Module items: - const: swir,mangoh-green-wp8548 From 84160da56dd0ce48dd8eed56237cc8be45bd55dc Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Tue, 28 Feb 2023 22:17:50 +0530 Subject: [PATCH 17/28] ARM: dts: qcom: apq8064: Use 0x prefix for the PCI I/O and MEM ranges To maintain the uniformity, let's use the 0x prefix for the values of ranges property. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Arnd Bergmann Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230228164752.55682-15-manivannan.sadhasivam@linaro.org --- arch/arm/boot/dts/qcom-apq8064.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index 920d318da266..672b246afbba 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -1513,8 +1513,8 @@ num-lanes = <1>; #address-cells = <3>; #size-cells = <2>; - ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000>, /* I/O */ - <0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* mem */ + ranges = <0x81000000 0x0 0x00000000 0x0fe00000 0x0 0x00100000>, /* I/O */ + <0x82000000 0x0 0x08000000 0x08000000 0x0 0x07e00000>; /* mem */ interrupts = ; interrupt-names = "msi"; #interrupt-cells = <1>; From 2540279e9a9e74fc880d1e4c83754ecfcbe290a0 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Tue, 28 Feb 2023 22:17:51 +0530 Subject: [PATCH 18/28] ARM: dts: qcom: ipq4019: Fix the PCI I/O port range For 1MiB of the I/O region, the I/O ports of the legacy PCI devices are located in the range of 0x0 to 0x100000. Hence, fix the bogus PCI address (0x40200000) specified in the ranges property for I/O region. While at it, let's use the missing 0x prefix for the addresses. Fixes: 187519403273 ("ARM: dts: ipq4019: Add a few peripheral nodes") Reported-by: Arnd Bergmann Link: https://lore.kernel.org/linux-arm-msm/7c5dfa87-41df-4ba7-b0e4-72c8386402a8@app.fastmail.com/ Signed-off-by: Manivannan Sadhasivam Reviewed-by: Arnd Bergmann Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230228164752.55682-16-manivannan.sadhasivam@linaro.org --- arch/arm/boot/dts/qcom-ipq4019.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi index 9595229c4f0d..dfcfb3339c23 100644 --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi @@ -427,8 +427,8 @@ #address-cells = <3>; #size-cells = <2>; - ranges = <0x81000000 0 0x40200000 0x40200000 0 0x00100000>, - <0x82000000 0 0x40300000 0x40300000 0 0x00d00000>; + ranges = <0x81000000 0x0 0x00000000 0x40200000 0x0 0x00100000>, + <0x82000000 0x0 0x40300000 0x40300000 0x0 0x00d00000>; interrupts = ; interrupt-names = "msi"; From 0b16b34e491629016109e56747ad64588074194b Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Tue, 28 Feb 2023 22:17:52 +0530 Subject: [PATCH 19/28] ARM: dts: qcom: ipq8064: Fix the PCI I/O port range For 64KiB of the I/O region, the I/O ports of the legacy PCI devices are located in the range of 0x0 to 0x10000. Hence, fix the bogus PCI addresses (0x0fe00000, 0x31e00000, 0x35e00000) specified in the ranges property for I/O region. While at it, let's use the missing 0x prefix for the addresses. Fixes: 93241840b664 ("ARM: dts: qcom: Add pcie nodes for ipq8064") Reported-by: Arnd Bergmann Link: https://lore.kernel.org/linux-arm-msm/7c5dfa87-41df-4ba7-b0e4-72c8386402a8@app.fastmail.com/ Signed-off-by: Manivannan Sadhasivam Reviewed-by: Arnd Bergmann Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230228164752.55682-17-manivannan.sadhasivam@linaro.org --- arch/arm/boot/dts/qcom-ipq8064.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi index 5a464f6de0b6..af6764770fd1 100644 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi @@ -1089,8 +1089,8 @@ #address-cells = <3>; #size-cells = <2>; - ranges = <0x81000000 0 0x0fe00000 0x0fe00000 0 0x00010000 /* downstream I/O */ - 0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* non-prefetchable memory */ + ranges = <0x81000000 0x0 0x00000000 0x0fe00000 0x0 0x00010000 /* I/O */ + 0x82000000 0x0 0x08000000 0x08000000 0x0 0x07e00000>; /* MEM */ interrupts = ; interrupt-names = "msi"; @@ -1140,8 +1140,8 @@ #address-cells = <3>; #size-cells = <2>; - ranges = <0x81000000 0 0x31e00000 0x31e00000 0 0x00010000 /* downstream I/O */ - 0x82000000 0 0x2e000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */ + ranges = <0x81000000 0x0 0x00000000 0x31e00000 0x0 0x00010000 /* I/O */ + 0x82000000 0x0 0x2e000000 0x2e000000 0x0 0x03e00000>; /* MEM */ interrupts = ; interrupt-names = "msi"; @@ -1191,8 +1191,8 @@ #address-cells = <3>; #size-cells = <2>; - ranges = <0x81000000 0 0x35e00000 0x35e00000 0 0x00010000 /* downstream I/O */ - 0x82000000 0 0x32000000 0x32000000 0 0x03e00000>; /* non-prefetchable memory */ + ranges = <0x81000000 0x0 0x00000000 0x35e00000 0x0 0x00010000 /* I/O */ + 0x82000000 0x0 0x32000000 0x32000000 0x0 0x03e00000>; /* MEM */ interrupts = ; interrupt-names = "msi"; From 3b76b736cd9933ff88764ffec01cbd859c1475e7 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Wed, 8 Mar 2023 13:54:16 +0530 Subject: [PATCH 20/28] ARM: dts: qcom: sdx55: Fix the unit address of PCIe EP node Unit address of PCIe EP node should be 0x1c00000 as it has to match the first address specified in the reg property. This also requires sorting the node in the ascending order. Fixes: e6b69813283f ("ARM: dts: qcom: sdx55: Add support for PCIe EP") Reviewed-by: Konrad Dybcio Signed-off-by: Manivannan Sadhasivam Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230308082424.140224-6-manivannan.sadhasivam@linaro.org --- arch/arm/boot/dts/qcom-sdx55.dtsi | 78 +++++++++++++++---------------- 1 file changed, 39 insertions(+), 39 deletions(-) diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom-sdx55.dtsi index df7303c5c843..7fa542249f1a 100644 --- a/arch/arm/boot/dts/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom-sdx55.dtsi @@ -304,6 +304,45 @@ status = "disabled"; }; + pcie_ep: pcie-ep@1c00000 { + compatible = "qcom,sdx55-pcie-ep"; + reg = <0x01c00000 0x3000>, + <0x40000000 0xf1d>, + <0x40000f20 0xc8>, + <0x40001000 0x1000>, + <0x40200000 0x100000>, + <0x01c03000 0x3000>; + reg-names = "parf", "dbi", "elbi", "atu", "addr_space", + "mmio"; + + qcom,perst-regs = <&tcsr 0xb258 0xb270>; + + clocks = <&gcc GCC_PCIE_AUX_CLK>, + <&gcc GCC_PCIE_CFG_AHB_CLK>, + <&gcc GCC_PCIE_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_SLV_AXI_CLK>, + <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>, + <&gcc GCC_PCIE_SLEEP_CLK>, + <&gcc GCC_PCIE_0_CLKREF_CLK>; + clock-names = "aux", "cfg", "bus_master", "bus_slave", + "slave_q2a", "sleep", "ref"; + + interrupts = , + ; + interrupt-names = "global", "doorbell"; + reset-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 53 GPIO_ACTIVE_LOW>; + resets = <&gcc GCC_PCIE_BCR>; + reset-names = "core"; + power-domains = <&gcc PCIE_GDSC>; + phys = <&pcie0_lane>; + phy-names = "pciephy"; + max-link-speed = <3>; + num-lanes = <2>; + + status = "disabled"; + }; + pcie0_phy: phy@1c07000 { compatible = "qcom,sdx55-qmp-pcie-phy"; reg = <0x01c07000 0x1c4>; @@ -401,45 +440,6 @@ status = "disabled"; }; - pcie_ep: pcie-ep@40000000 { - compatible = "qcom,sdx55-pcie-ep"; - reg = <0x01c00000 0x3000>, - <0x40000000 0xf1d>, - <0x40000f20 0xc8>, - <0x40001000 0x1000>, - <0x40200000 0x100000>, - <0x01c03000 0x3000>; - reg-names = "parf", "dbi", "elbi", "atu", "addr_space", - "mmio"; - - qcom,perst-regs = <&tcsr 0xb258 0xb270>; - - clocks = <&gcc GCC_PCIE_AUX_CLK>, - <&gcc GCC_PCIE_CFG_AHB_CLK>, - <&gcc GCC_PCIE_MSTR_AXI_CLK>, - <&gcc GCC_PCIE_SLV_AXI_CLK>, - <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>, - <&gcc GCC_PCIE_SLEEP_CLK>, - <&gcc GCC_PCIE_0_CLKREF_CLK>; - clock-names = "aux", "cfg", "bus_master", "bus_slave", - "slave_q2a", "sleep", "ref"; - - interrupts = , - ; - interrupt-names = "global", "doorbell"; - reset-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 53 GPIO_ACTIVE_LOW>; - resets = <&gcc GCC_PCIE_BCR>; - reset-names = "core"; - power-domains = <&gcc PCIE_GDSC>; - phys = <&pcie0_lane>; - phy-names = "pciephy"; - max-link-speed = <3>; - num-lanes = <2>; - - status = "disabled"; - }; - remoteproc_mpss: remoteproc@4080000 { compatible = "qcom,sdx55-mpss-pas"; reg = <0x04080000 0x4040>; From c9f30e3dd92ba779c9cb8bb694ed7a8e2c9f0bb3 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Wed, 8 Mar 2023 13:54:17 +0530 Subject: [PATCH 21/28] ARM: dts: qcom: sdx55: Rename pcie0_{phy/lane} to pcie_{phy/lane} There is only one PCIe PHY in this SoC, so there is no need to add an index to the suffix. This also matches the naming convention of the PCIe controller. Reviewed-by: Konrad Dybcio Signed-off-by: Manivannan Sadhasivam Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230308082424.140224-7-manivannan.sadhasivam@linaro.org --- arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts | 2 +- arch/arm/boot/dts/qcom-sdx55.dtsi | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts b/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts index ad74ecc2a196..81f33eba39e5 100644 --- a/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts +++ b/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts @@ -242,7 +242,7 @@ status = "okay"; }; -&pcie0_phy { +&pcie_phy { status = "okay"; vdda-phy-supply = <&vreg_l1e_bb_1p2>; diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom-sdx55.dtsi index 7fa542249f1a..bd4edceaa1f4 100644 --- a/arch/arm/boot/dts/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom-sdx55.dtsi @@ -335,7 +335,7 @@ resets = <&gcc GCC_PCIE_BCR>; reset-names = "core"; power-domains = <&gcc PCIE_GDSC>; - phys = <&pcie0_lane>; + phys = <&pcie_lane>; phy-names = "pciephy"; max-link-speed = <3>; num-lanes = <2>; @@ -343,7 +343,7 @@ status = "disabled"; }; - pcie0_phy: phy@1c07000 { + pcie_phy: phy@1c07000 { compatible = "qcom,sdx55-qmp-pcie-phy"; reg = <0x01c07000 0x1c4>; #address-cells = <1>; @@ -363,7 +363,7 @@ status = "disabled"; - pcie0_lane: lanes@1c06000 { + pcie_lane: lanes@1c06000 { reg = <0x01c06000 0x104>, /* tx0 */ <0x01c06200 0x328>, /* rx0 */ <0x01c07200 0x1e8>, /* pcs */ From 2b20437e67a4b74b990d19d3dbf55388e941f30f Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Wed, 8 Mar 2023 13:54:18 +0530 Subject: [PATCH 22/28] ARM: dts: qcom: sdx55: Add support for PCIe RC controller The PCIe controller in SDX55 can act as the RC controller also. Let's add support for it. Reviewed-by: Konrad Dybcio Signed-off-by: Manivannan Sadhasivam Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230308082424.140224-8-manivannan.sadhasivam@linaro.org --- arch/arm/boot/dts/qcom-sdx55.dtsi | 81 +++++++++++++++++++++++++++++++ 1 file changed, 81 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom-sdx55.dtsi index bd4edceaa1f4..9dabb94eafbc 100644 --- a/arch/arm/boot/dts/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom-sdx55.dtsi @@ -304,6 +304,87 @@ status = "disabled"; }; + pcie_rc: pcie@1c00000 { + compatible = "qcom,pcie-sdx55"; + reg = <0x01c00000 0x3000>, + <0x40000000 0xf1d>, + <0x40000f20 0xc8>, + <0x40001000 0x1000>, + <0x40100000 0x100000>; + reg-names = "parf", + "dbi", + "elbi", + "atu", + "config"; + device_type = "pci"; + linux,pci-domain = <0>; + bus-range = <0x00 0xff>; + num-lanes = <1>; + + #address-cells = <3>; + #size-cells = <2>; + + ranges = <0x01000000 0x0 0x00000000 0x40200000 0x0 0x100000>, + <0x02000000 0x0 0x40300000 0x40300000 0x0 0x3fd00000>; + + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "msi", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7", + "msi8"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 0 0 141 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 0 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 0 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 0 0 144 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + clocks = <&gcc GCC_PCIE_PIPE_CLK>, + <&gcc GCC_PCIE_AUX_CLK>, + <&gcc GCC_PCIE_CFG_AHB_CLK>, + <&gcc GCC_PCIE_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_SLV_AXI_CLK>, + <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>, + <&gcc GCC_PCIE_SLEEP_CLK>; + clock-names = "pipe", + "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "sleep"; + + assigned-clocks = <&gcc GCC_PCIE_AUX_CLK>; + assigned-clock-rates = <19200000>; + + iommu-map = <0x0 &apps_smmu 0x0200 0x1>, + <0x100 &apps_smmu 0x0201 0x1>, + <0x200 &apps_smmu 0x0202 0x1>, + <0x300 &apps_smmu 0x0203 0x1>, + <0x400 &apps_smmu 0x0204 0x1>; + + resets = <&gcc GCC_PCIE_BCR>; + reset-names = "pci"; + + power-domains = <&gcc PCIE_GDSC>; + + phys = <&pcie_lane>; + phy-names = "pciephy"; + + status = "disabled"; + }; + pcie_ep: pcie-ep@1c00000 { compatible = "qcom,sdx55-pcie-ep"; reg = <0x01c00000 0x3000>, From f9364a7ced5e6e36904c359cafe23cbf03645884 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Wed, 8 Mar 2023 13:54:19 +0530 Subject: [PATCH 23/28] ARM: dts: qcom: sdx55: List the property values vertically To align with the rest of the devicetree files and the relative properties, let's list the values of properties such as {reg/clock/interrupt}-names vertically. Suggested-by: Konrad Dybcio Reviewed-by: Konrad Dybcio Signed-off-by: Manivannan Sadhasivam Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230308082424.140224-9-manivannan.sadhasivam@linaro.org --- arch/arm/boot/dts/qcom-sdx55.dtsi | 23 ++++++++++++++++++----- 1 file changed, 18 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom-sdx55.dtsi index 9dabb94eafbc..286fa92da428 100644 --- a/arch/arm/boot/dts/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom-sdx55.dtsi @@ -393,7 +393,11 @@ <0x40001000 0x1000>, <0x40200000 0x100000>, <0x01c03000 0x3000>; - reg-names = "parf", "dbi", "elbi", "atu", "addr_space", + reg-names = "parf", + "dbi", + "elbi", + "atu", + "addr_space", "mmio"; qcom,perst-regs = <&tcsr 0xb258 0xb270>; @@ -405,12 +409,18 @@ <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>, <&gcc GCC_PCIE_SLEEP_CLK>, <&gcc GCC_PCIE_0_CLKREF_CLK>; - clock-names = "aux", "cfg", "bus_master", "bus_slave", - "slave_q2a", "sleep", "ref"; + clock-names = "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "sleep", + "ref"; interrupts = , ; - interrupt-names = "global", "doorbell"; + interrupt-names = "global", + "doorbell"; reset-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>; wake-gpios = <&tlmm 53 GPIO_ACTIVE_LOW>; resets = <&gcc GCC_PCIE_BCR>; @@ -434,7 +444,10 @@ <&gcc GCC_PCIE_CFG_AHB_CLK>, <&gcc GCC_PCIE_0_CLKREF_CLK>, <&gcc GCC_PCIE_RCHNG_PHY_CLK>; - clock-names = "aux", "cfg_ahb", "ref", "refgen"; + clock-names = "aux", + "cfg_ahb", + "ref", + "refgen"; resets = <&gcc GCC_PCIE_PHY_BCR>; reset-names = "phy"; From 046392390884c9dead1d3703fa60dff97f22857a Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Wed, 8 Mar 2023 13:54:20 +0530 Subject: [PATCH 24/28] ARM: dts: qcom: sdx55-t55: Enable PCIe RC support Enable PCIe RC support on Thundercomm T55 board. Reviewed-by: Konrad Dybcio Signed-off-by: Manivannan Sadhasivam Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230308082424.140224-10-manivannan.sadhasivam@linaro.org --- arch/arm/boot/dts/qcom-sdx55-t55.dts | 42 ++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx55-t55.dts b/arch/arm/boot/dts/qcom-sdx55-t55.dts index d5343bb0daee..5edc09af8e0d 100644 --- a/arch/arm/boot/dts/qcom-sdx55-t55.dts +++ b/arch/arm/boot/dts/qcom-sdx55-t55.dts @@ -242,6 +242,23 @@ status = "okay"; }; +&pcie_phy { + vdda-phy-supply = <&vreg_l1e_bb_1p2>; + vdda-pll-supply = <&vreg_l4e_bb_0p875>; + + status = "okay"; +}; + +&pcie_rc { + perst-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 53 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&pcie_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + &qpic_bam { status = "okay"; }; @@ -265,6 +282,31 @@ memory-region = <&mpss_adsp_mem>; }; +&tlmm { + pcie_default: pcie-default-state { + clkreq-pins { + pins = "gpio56"; + function = "pcie_clkreq"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-pins { + pins = "gpio57"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + wake-pins { + pins = "gpio53"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; +}; + &usb_hsphy { status = "okay"; vdda-pll-supply = <&vreg_l4e_bb_0p875>; From 43743bfa36daed8f31860ad889a1413f239bb2f2 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Wed, 8 Mar 2023 13:54:21 +0530 Subject: [PATCH 25/28] ARM: dts: qcom: sdx55-t55: Move "status" property down To align with rest of the devicetree files, let's move the "status" property down Suggested-by: Konrad Dybcio Reviewed-by: Konrad Dybcio Signed-off-by: Manivannan Sadhasivam Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230308082424.140224-11-manivannan.sadhasivam@linaro.org --- arch/arm/boot/dts/qcom-sdx55-t55.dts | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/qcom-sdx55-t55.dts b/arch/arm/boot/dts/qcom-sdx55-t55.dts index 5edc09af8e0d..51058b065279 100644 --- a/arch/arm/boot/dts/qcom-sdx55-t55.dts +++ b/arch/arm/boot/dts/qcom-sdx55-t55.dts @@ -278,8 +278,8 @@ }; &remoteproc_mpss { - status = "okay"; memory-region = <&mpss_adsp_mem>; + status = "okay"; }; &tlmm { @@ -308,16 +308,18 @@ }; &usb_hsphy { - status = "okay"; vdda-pll-supply = <&vreg_l4e_bb_0p875>; vdda33-supply = <&vreg_l10e_3p1>; vdda18-supply = <&vreg_l5e_bb_1p7>; + + status = "okay"; }; &usb_qmpphy { - status = "okay"; vdda-phy-supply = <&vreg_l4e_bb_0p875>; vdda-pll-supply = <&vreg_l1e_bb_1p2>; + + status = "okay"; }; &usb { From 424a4e5273bfc16b6974faff50f0d24c1df0c76e Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 6 Mar 2023 08:26:18 +0100 Subject: [PATCH 26/28] ARM: dts: qcom: sdx55: add dedicated SDX55 TCSR compatible syscon should not be used alone as compatible. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230306072618.10770-2-krzysztof.kozlowski@linaro.org --- arch/arm/boot/dts/qcom-sdx55.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom-sdx55.dtsi index 286fa92da428..9148a840b8a0 100644 --- a/arch/arm/boot/dts/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom-sdx55.dtsi @@ -518,7 +518,7 @@ }; tcsr: syscon@1fcb000 { - compatible = "syscon"; + compatible = "qcom,sdx55-tcsr", "syscon"; reg = <0x01fc0000 0x1000>; }; From d27580366db0fb6fa1f6b6ca94bc89dcbf9fd496 Mon Sep 17 00:00:00 2001 From: Yang Xiwen Date: Fri, 10 Mar 2023 22:33:28 +0800 Subject: [PATCH 27/28] dt-bindings: vendor-prefixes: Add Henan Yiming Technology Co., Ltd. Henan Yiming Technology Co., Ltd. was established in 2021. The business scope of the company includes: communication equipment (excluding radio control equipment). Link: https://gw.yimingkeji.net Signed-off-by: Yang Xiwen Acked-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/tencent_27DD0718C3FD9C5F7D6E2FBA225CAA760405@qq.com --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index ed64e06ecca4..d6ec61904d6b 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -1528,6 +1528,8 @@ patternProperties: description: Yes Optoelectronics Co.,Ltd. "^yic,.*": description: YIC System Co., Ltd. + "^yiming,.*": + description: Henan Yiming Technology Co., Ltd. "^ylm,.*": description: Shenzhen Yangliming Electronic Technology Co., Ltd. "^yna,.*": From 26c56dbddc304cf7304346df4b25b3be0c086e36 Mon Sep 17 00:00:00 2001 From: Yang Xiwen Date: Fri, 10 Mar 2023 22:33:29 +0800 Subject: [PATCH 28/28] dt-bindings: arm: qcom: Add Yiming LTE dongle uz801-v3.0 (yiming-uz801v3) Add a compatible for Yiming LTE dongle uz801-v3.0 Signed-off-by: Yang Xiwen Acked-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/tencent_61B4697855AD14BA2930AC7B21FFC75C4406@qq.com --- Documentation/devicetree/bindings/arm/qcom.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 05badce5fedc..f8d29b65f28b 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -230,6 +230,7 @@ properties: - thwc,uf896 - thwc,ufi001c - wingtech,wt88047 + - yiming,uz801-v3 - const: qcom,msm8916 - items: