drm/amd/display: Add guard for FCLK pstate message to PMFW for DCN321

[WHY?]
DCN321 does not support FCLK DPM, and thus it should not send messages to
PMFW regarding it.

Signed-off-by: Dillon Varone <dillon.varone@amd.com>
Acked-by: Jerry Zuo <jerry.zuo@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Dillon Varone 2022-03-08 15:32:06 -05:00 committed by Alex Deucher
parent 542a0f2ef9
commit a839a73b18

View File

@ -346,7 +346,8 @@ static void dcn32_update_clocks(struct clk_mgr *clk_mgr_base,
clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries - 1].memclk_mhz);
}
if (should_update_pstate_support(safe_to_lower, fclk_p_state_change_support, clk_mgr_base->clks.fclk_p_state_change_support)) {
if (should_update_pstate_support(safe_to_lower, fclk_p_state_change_support, clk_mgr_base->clks.fclk_p_state_change_support) &&
clk_mgr_base->ctx->dce_version != DCN_VERSION_3_21) {
clk_mgr_base->clks.fclk_p_state_change_support = fclk_p_state_change_support;
/* To disable FCLK P-state switching, send FCLK_PSTATE_NOTSUPPORTED message to PMFW */