drm/amd/display: Add guard for FCLK pstate message to PMFW for DCN321
[WHY?] DCN321 does not support FCLK DPM, and thus it should not send messages to PMFW regarding it. Signed-off-by: Dillon Varone <dillon.varone@amd.com> Acked-by: Jerry Zuo <jerry.zuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -346,7 +346,8 @@ static void dcn32_update_clocks(struct clk_mgr *clk_mgr_base,
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clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries - 1].memclk_mhz);
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}
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if (should_update_pstate_support(safe_to_lower, fclk_p_state_change_support, clk_mgr_base->clks.fclk_p_state_change_support)) {
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if (should_update_pstate_support(safe_to_lower, fclk_p_state_change_support, clk_mgr_base->clks.fclk_p_state_change_support) &&
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clk_mgr_base->ctx->dce_version != DCN_VERSION_3_21) {
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clk_mgr_base->clks.fclk_p_state_change_support = fclk_p_state_change_support;
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/* To disable FCLK P-state switching, send FCLK_PSTATE_NOTSUPPORTED message to PMFW */
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