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drm/nouveau/disp/sor/gf119: both links use the same training register

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It appears that, for whatever reason, both link A and B use the same
register to control the training pattern.  It's a little odd, as the
GPUs before this (Tesla/Fermi1) have per-link registers, as do newer
GPUs (Maxwell).

Fixes the third DP output on NVS 510 (GK107).

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Cc: stable@vger.kernel.org
This commit is contained in:
Ben Skeggs 2016-06-03 14:37:40 +10:00
parent 77154fd969
commit a8953c52b9
1 changed files with 1 additions and 2 deletions
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3
drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf119.c
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@ -40,8 +40,7 @@ static int
gf119_sor_dp_pattern(struct nvkm_output_dp *outp, int pattern)
{
struct nvkm_device *device = outp->base.disp->engine.subdev.device;
const u32 loff = gf119_sor_loff(outp);
nvkm_mask(device, 0x61c110 + loff, 0x0f0f0f0f, 0x01010101 * pattern);
nvkm_mask(device, 0x61c110, 0x0f0f0f0f, 0x01010101 * pattern);
return 0;
}