iv/linux
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

arm64: dts: imx8qxp: add cadence usb3 support

Browse Source 
There are cadence usb3.0 controller in 8qxp and 8qm.
Add usb3 node at common connect subsystem.

Signed-off-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
Frank Li 2023-03-27 10:55:22 -04:00 committed by Shawn Guo
parent 2858e62e5d
commit a8bd7f1551
1 changed files with 69 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

69
arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
View File

@ -138,6 +138,53 @@ conn_subsys: bus@5b000000 {
status = "disabled";
};
usbotg3: usb@5b110000 {
compatible = "fsl,imx8qm-usb3";
reg = <0x5b110000 0x10000>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
clocks = <&usb3_lpcg IMX_LPCG_CLK_1>,
<&usb3_lpcg IMX_LPCG_CLK_0>,
<&usb3_lpcg IMX_LPCG_CLK_7>,
<&usb3_lpcg IMX_LPCG_CLK_4>,
<&usb3_lpcg IMX_LPCG_CLK_5>;
clock-names = "lpm", "bus", "aclk", "ipg", "core";
assigned-clocks = <&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_MST_BUS>;
assigned-clock-rates = <250000000>;
power-domains = <&pd IMX_SC_R_USB_2>;
status = "disabled";
usbotg3_cdns3: usb@5b120000 {
compatible = "cdns,usb3";
reg = <0x5b130000 0x10000>, /* memory area for HOST registers */
<0x5b140000 0x10000>, /* memory area for DEVICE registers */
<0x5b120000 0x10000>; /* memory area for OTG/DRD registers */
reg-names = "xhci", "dev", "otg";
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "host", "peripheral", "otg", "wakeup";
phys = <&usb3_phy>;
phy-names = "cdns3,usb3-phy";
status = "disabled";
};
};
usb3_phy: usb-phy@5b160000 {
compatible = "nxp,salvo-phy";
reg = <0x5b160000 0x40000>;
clocks = <&usb3_lpcg IMX_LPCG_CLK_6>;
clock-names = "salvo_phy_clk";
power-domains = <&pd IMX_SC_R_USB_2_PHY>;
#phy-cells = <0>;
status = "disabled";
};
/* LPCG clocks */
sdhc0_lpcg: clock-controller@5b200000 {
compatible = "fsl,imx8qxp-lpcg";
@ -234,4 +281,26 @@ conn_subsys: bus@5b000000 {
clock-output-names = "usboh3_ahb_clk", "usboh3_phy_ipg_clk";
power-domains = <&pd IMX_SC_R_USB_0_PHY>;
};
usb3_lpcg: clock-controller@5b280000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x5b280000 0x10000>;
#clock-cells = <1>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
<IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
<IMX_LPCG_CLK_6>, <IMX_LPCG_CLK_7>;
clocks = <&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_PER>,
<&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_MISC>,
<&conn_ipg_clk>,
<&conn_ipg_clk>,
<&conn_ipg_clk>,
<&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_MST_BUS>;
clock-output-names = "usb3_app_clk",
"usb3_lpm_clk",
"usb3_ipg_clk",
"usb3_core_pclk",
"usb3_phy_clk",
"usb3_aclk";
power-domains = <&pd IMX_SC_R_USB_2_PHY>;
};
};