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Merge branch 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm

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* 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm: (44 commits)
  [ARM] 3541/2: workaround for PXA27x erratum E7
  [ARM] nommu: provide a way for correct control register value selection
  [ARM] 3705/1: add supersection support to ioremap()
  [ARM] 3707/1: iwmmxt: use the generic thread notifier infrastructure
  [ARM] 3706/2: ep93xx: add cirrus logic edb9315a support
  [ARM] 3704/1: format IOP Kconfig with tabs, create more consistency
  [ARM] 3703/1: Add help description for ARCH_EP80219
  [ARM] 3678/1: MMC: Make OMAP MMC work
  [ARM] 3677/1: OMAP: Update H2 defconfig
  [ARM] 3676/1: ARM: OMAP: Fix dmtimers and timer32k to compile on OMAP1
  [ARM] Add section support to ioremap
  [ARM] Fix sa11x0 SDRAM selection
  [ARM] Set bit 4 on section mappings correctly depending on CPU
  [ARM] 3666/1: TRIZEPS4 [1/5] core
  ARM: OMAP: Multiplexing for 24xx GPMC wait pin monitoring
  ARM: OMAP: Fix SRAM to use MT_MEMORY instead of MT_DEVICE
  ARM: OMAP: Update dmtimers
  ARM: OMAP: Make clock variables static
  ARM: OMAP: Fix GPMC compilation when DEBUG is defined
  ARM: OMAP: Mux updates for external DMA and GPIO
  ...
This commit is contained in:
Linus Torvalds 2006-07-02 15:04:12 -07:00
commit a8c4c20dfa
106 changed files with 5705 additions and 951 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
arch/arm/Kconfig
View File

@ -121,11 +121,11 @@ config ARCH_VERSATILE
help help
This enables support for ARM Ltd Versatile board. This enables support for ARM Ltd Versatile board.
config ARCH_AT91RM9200 config ARCH_AT91
bool "Atmel AT91RM9200" bool "Atmel AT91"
help help
Say Y here if you intend to run this kernel on an Atmel This enables support for systems based on the Atmel AT91RM9200
AT91RM9200-based board. and AT91SAM9xxx processors.
config ARCH_CLPS7500 config ARCH_CLPS7500
bool "Cirrus CL-PS7500FE" bool "Cirrus CL-PS7500FE"
@ -547,7 +547,7 @@ config LEDS
ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \ ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \ ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \ ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
ARCH_AT91RM9200 ARCH_AT91RM9200 || MACH_TRIZEPS4
help help
If you say Y here, the LEDs on your machine will be used If you say Y here, the LEDs on your machine will be used
to provide useful information about your current system status. to provide useful information about your current system status.
@ -678,7 +678,7 @@ config XIP_PHYS_ADDR
endmenu endmenu
if (ARCH_SA1100 || ARCH_INTEGRATOR || ARCH_OMAP1) if (ARCH_SA1100 || ARCH_INTEGRATOR || ARCH_OMAP)
menu "CPU Frequency scaling" menu "CPU Frequency scaling"

2
arch/arm/Makefile
View File

@ -114,7 +114,7 @@ endif
machine-$(CONFIG_ARCH_H720X) := h720x machine-$(CONFIG_ARCH_H720X) := h720x
machine-$(CONFIG_ARCH_AAEC2000) := aaec2000 machine-$(CONFIG_ARCH_AAEC2000) := aaec2000
machine-$(CONFIG_ARCH_REALVIEW) := realview machine-$(CONFIG_ARCH_REALVIEW) := realview
machine-$(CONFIG_ARCH_AT91RM9200) := at91rm9200 machine-$(CONFIG_ARCH_AT91) := at91rm9200
machine-$(CONFIG_ARCH_EP93XX) := ep93xx machine-$(CONFIG_ARCH_EP93XX) := ep93xx
machine-$(CONFIG_ARCH_PNX4008) := pnx4008 machine-$(CONFIG_ARCH_PNX4008) := pnx4008
machine-$(CONFIG_ARCH_NETX) := netx machine-$(CONFIG_ARCH_NETX) := netx

7
arch/arm/boot/compressed/head.S
View File

@ -447,8 +447,11 @@ __common_mmu_cache_on:
mov r1, #-1 mov r1, #-1
mcr p15, 0, r3, c2, c0, 0 @ load page table pointer mcr p15, 0, r3, c2, c0, 0 @ load page table pointer
mcr p15, 0, r1, c3, c0, 0 @ load domain access control mcr p15, 0, r1, c3, c0, 0 @ load domain access control
mcr p15, 0, r0, c1, c0, 0 @ load control register b 1f
mov pc, lr .align 5 @ cache line aligned
1: mcr p15, 0, r0, c1, c0, 0 @ load control register
mrc p15, 0, r0, c1, c0, 0 @ and read it back to
sub pc, lr, r0, lsr #32 @ properly flush pipeline
/* /*
* All code following this line is relocatable. It is relocated by * All code following this line is relocatable. It is relocated by

1
arch/arm/configs/at91rm9200dk_defconfig
View File

@ -103,6 +103,7 @@ CONFIG_DEFAULT_IOSCHED="anticipatory"
# CONFIG_ARCH_IMX is not set # CONFIG_ARCH_IMX is not set
# CONFIG_ARCH_H720X is not set # CONFIG_ARCH_H720X is not set
# CONFIG_ARCH_AAEC2000 is not set # CONFIG_ARCH_AAEC2000 is not set
CONFIG_ARCH_AT91=y
CONFIG_ARCH_AT91RM9200=y CONFIG_ARCH_AT91RM9200=y
# #

1
arch/arm/configs/at91rm9200ek_defconfig
View File

@ -103,6 +103,7 @@ CONFIG_DEFAULT_IOSCHED="anticipatory"
# CONFIG_ARCH_IMX is not set # CONFIG_ARCH_IMX is not set
# CONFIG_ARCH_H720X is not set # CONFIG_ARCH_H720X is not set
# CONFIG_ARCH_AAEC2000 is not set # CONFIG_ARCH_AAEC2000 is not set
CONFIG_ARCH_AT91=y
CONFIG_ARCH_AT91RM9200=y CONFIG_ARCH_AT91RM9200=y
# #

1
arch/arm/configs/ateb9200_defconfig
View File

@ -105,6 +105,7 @@ CONFIG_DEFAULT_IOSCHED="anticipatory"
# CONFIG_ARCH_IMX is not set # CONFIG_ARCH_IMX is not set
# CONFIG_ARCH_H720X is not set # CONFIG_ARCH_H720X is not set
# CONFIG_ARCH_AAEC2000 is not set # CONFIG_ARCH_AAEC2000 is not set
CONFIG_ARCH_AT91=y
CONFIG_ARCH_AT91RM9200=y CONFIG_ARCH_AT91RM9200=y
# #

1
arch/arm/configs/carmeva_defconfig
View File

@ -82,6 +82,7 @@ CONFIG_OBSOLETE_MODPARM=y
# CONFIG_ARCH_VERSATILE is not set # CONFIG_ARCH_VERSATILE is not set
# CONFIG_ARCH_IMX is not set # CONFIG_ARCH_IMX is not set
# CONFIG_ARCH_H720X is not set # CONFIG_ARCH_H720X is not set
CONFIG_ARCH_AT91=y
CONFIG_ARCH_AT91RM9200=y CONFIG_ARCH_AT91RM9200=y
# #

1
arch/arm/configs/csb337_defconfig
View File

@ -103,6 +103,7 @@ CONFIG_DEFAULT_IOSCHED="anticipatory"
# CONFIG_ARCH_IMX is not set # CONFIG_ARCH_IMX is not set
# CONFIG_ARCH_H720X is not set # CONFIG_ARCH_H720X is not set
# CONFIG_ARCH_AAEC2000 is not set # CONFIG_ARCH_AAEC2000 is not set
CONFIG_ARCH_AT91=y
CONFIG_ARCH_AT91RM9200=y CONFIG_ARCH_AT91RM9200=y
# #

1
arch/arm/configs/csb637_defconfig
View File

@ -103,6 +103,7 @@ CONFIG_DEFAULT_IOSCHED="anticipatory"
# CONFIG_ARCH_IMX is not set # CONFIG_ARCH_IMX is not set
# CONFIG_ARCH_H720X is not set # CONFIG_ARCH_H720X is not set
# CONFIG_ARCH_AAEC2000 is not set # CONFIG_ARCH_AAEC2000 is not set
CONFIG_ARCH_AT91=y
CONFIG_ARCH_AT91RM9200=y CONFIG_ARCH_AT91RM9200=y
# #

1
arch/arm/configs/kafa_defconfig
View File

@ -105,6 +105,7 @@ CONFIG_DEFAULT_IOSCHED="deadline"
# CONFIG_ARCH_IMX is not set # CONFIG_ARCH_IMX is not set
# CONFIG_ARCH_H720X is not set # CONFIG_ARCH_H720X is not set
# CONFIG_ARCH_AAEC2000 is not set # CONFIG_ARCH_AAEC2000 is not set
CONFIG_ARCH_AT91=y
CONFIG_ARCH_AT91RM9200=y CONFIG_ARCH_AT91RM9200=y
# #

1
arch/arm/configs/kb9202_defconfig
View File

@ -80,6 +80,7 @@ CONFIG_KMOD=y
# CONFIG_ARCH_IMX is not set # CONFIG_ARCH_IMX is not set
# CONFIG_ARCH_H720X is not set # CONFIG_ARCH_H720X is not set
# CONFIG_ARCH_AAEC2000 is not set # CONFIG_ARCH_AAEC2000 is not set
CONFIG_ARCH_AT91=y
CONFIG_ARCH_AT91RM9200=y CONFIG_ARCH_AT91RM9200=y
# #

129
arch/arm/configs/omap_h2_1610_defconfig
View File

@ -1,19 +1,20 @@
# #
# Automatically generated make config: don't edit # Automatically generated make config: don't edit
# Linux kernel version: 2.6.14 # Linux kernel version: 2.6.17
# Wed Nov 9 18:53:40 2005 # Thu Jun 29 15:25:18 2006
# #
CONFIG_ARM=y CONFIG_ARM=y
CONFIG_MMU=y CONFIG_MMU=y
CONFIG_UID16=y
CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_RWSEM_GENERIC_SPINLOCK=y
CONFIG_GENERIC_HWEIGHT=y
CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_GENERIC_CALIBRATE_DELAY=y
CONFIG_VECTORS_BASE=0xffff0000
CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
# #
# Code maturity level options # Code maturity level options
# #
CONFIG_EXPERIMENTAL=y CONFIG_EXPERIMENTAL=y
CONFIG_CLEAN_COMPILE=y
CONFIG_BROKEN_ON_SMP=y CONFIG_BROKEN_ON_SMP=y
CONFIG_LOCK_KERNEL=y CONFIG_LOCK_KERNEL=y
CONFIG_INIT_ENV_ARG_LIMIT=32 CONFIG_INIT_ENV_ARG_LIMIT=32
@ -29,26 +30,26 @@ CONFIG_SYSVIPC=y
# CONFIG_BSD_PROCESS_ACCT is not set # CONFIG_BSD_PROCESS_ACCT is not set
CONFIG_SYSCTL=y CONFIG_SYSCTL=y
# CONFIG_AUDIT is not set # CONFIG_AUDIT is not set
# CONFIG_HOTPLUG is not set
CONFIG_KOBJECT_UEVENT=y
# CONFIG_IKCONFIG is not set # CONFIG_IKCONFIG is not set
# CONFIG_RELAY is not set
CONFIG_INITRAMFS_SOURCE="" CONFIG_INITRAMFS_SOURCE=""
CONFIG_UID16=y
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
# CONFIG_EMBEDDED is not set # CONFIG_EMBEDDED is not set
CONFIG_KALLSYMS=y CONFIG_KALLSYMS=y
# CONFIG_KALLSYMS_EXTRA_PASS is not set # CONFIG_KALLSYMS_EXTRA_PASS is not set
CONFIG_HOTPLUG=y
CONFIG_PRINTK=y CONFIG_PRINTK=y
CONFIG_BUG=y CONFIG_BUG=y
CONFIG_ELF_CORE=y
CONFIG_BASE_FULL=y CONFIG_BASE_FULL=y
CONFIG_FUTEX=y CONFIG_FUTEX=y
CONFIG_EPOLL=y CONFIG_EPOLL=y
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_SHMEM=y CONFIG_SHMEM=y
CONFIG_CC_ALIGN_FUNCTIONS=0 CONFIG_SLAB=y
CONFIG_CC_ALIGN_LABELS=0
CONFIG_CC_ALIGN_LOOPS=0
CONFIG_CC_ALIGN_JUMPS=0
# CONFIG_TINY_SHMEM is not set # CONFIG_TINY_SHMEM is not set
CONFIG_BASE_SMALL=0 CONFIG_BASE_SMALL=0
# CONFIG_SLOB is not set
# #
# Loadable module support # Loadable module support
@ -56,7 +57,6 @@ CONFIG_BASE_SMALL=0
CONFIG_MODULES=y CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y CONFIG_MODULE_UNLOAD=y
# CONFIG_MODULE_FORCE_UNLOAD is not set # CONFIG_MODULE_FORCE_UNLOAD is not set
CONFIG_OBSOLETE_MODPARM=y
# CONFIG_MODVERSIONS is not set # CONFIG_MODVERSIONS is not set
# CONFIG_MODULE_SRCVERSION_ALL is not set # CONFIG_MODULE_SRCVERSION_ALL is not set
# CONFIG_KMOD is not set # CONFIG_KMOD is not set
@ -64,6 +64,7 @@ CONFIG_OBSOLETE_MODPARM=y
# #
# Block layer # Block layer
# #
# CONFIG_BLK_DEV_IO_TRACE is not set
# #
# IO Schedulers # IO Schedulers
@ -81,16 +82,26 @@ CONFIG_DEFAULT_IOSCHED="anticipatory"
# #
# System Type # System Type
# #
# CONFIG_ARCH_AAEC2000 is not set
# CONFIG_ARCH_INTEGRATOR is not set
# CONFIG_ARCH_REALVIEW is not set
# CONFIG_ARCH_VERSATILE is not set
# CONFIG_ARCH_AT91RM9200 is not set
# CONFIG_ARCH_CLPS7500 is not set # CONFIG_ARCH_CLPS7500 is not set
# CONFIG_ARCH_CLPS711X is not set # CONFIG_ARCH_CLPS711X is not set
# CONFIG_ARCH_CO285 is not set # CONFIG_ARCH_CO285 is not set
# CONFIG_ARCH_EBSA110 is not set # CONFIG_ARCH_EBSA110 is not set
# CONFIG_ARCH_EP93XX is not set
# CONFIG_ARCH_FOOTBRIDGE is not set # CONFIG_ARCH_FOOTBRIDGE is not set
# CONFIG_ARCH_INTEGRATOR is not set # CONFIG_ARCH_NETX is not set
# CONFIG_ARCH_H720X is not set
# CONFIG_ARCH_IMX is not set
# CONFIG_ARCH_IOP3XX is not set # CONFIG_ARCH_IOP3XX is not set
# CONFIG_ARCH_IXP4XX is not set # CONFIG_ARCH_IXP4XX is not set
# CONFIG_ARCH_IXP2000 is not set # CONFIG_ARCH_IXP2000 is not set
# CONFIG_ARCH_IXP23XX is not set
# CONFIG_ARCH_L7200 is not set # CONFIG_ARCH_L7200 is not set
# CONFIG_ARCH_PNX4008 is not set
# CONFIG_ARCH_PXA is not set # CONFIG_ARCH_PXA is not set
# CONFIG_ARCH_RPC is not set # CONFIG_ARCH_RPC is not set
# CONFIG_ARCH_SA1100 is not set # CONFIG_ARCH_SA1100 is not set
@ -98,11 +109,6 @@ CONFIG_DEFAULT_IOSCHED="anticipatory"
# CONFIG_ARCH_SHARK is not set # CONFIG_ARCH_SHARK is not set
# CONFIG_ARCH_LH7A40X is not set # CONFIG_ARCH_LH7A40X is not set
CONFIG_ARCH_OMAP=y CONFIG_ARCH_OMAP=y
# CONFIG_ARCH_VERSATILE is not set
# CONFIG_ARCH_REALVIEW is not set
# CONFIG_ARCH_IMX is not set
# CONFIG_ARCH_H720X is not set
# CONFIG_ARCH_AAEC2000 is not set
# #
# TI OMAP Implementations # TI OMAP Implementations
@ -141,6 +147,7 @@ CONFIG_ARCH_OMAP16XX=y
CONFIG_MACH_OMAP_H2=y CONFIG_MACH_OMAP_H2=y
# CONFIG_MACH_OMAP_H3 is not set # CONFIG_MACH_OMAP_H3 is not set
# CONFIG_MACH_OMAP_OSK is not set # CONFIG_MACH_OMAP_OSK is not set
# CONFIG_MACH_NOKIA770 is not set
# CONFIG_MACH_OMAP_GENERIC is not set # CONFIG_MACH_OMAP_GENERIC is not set
# #
@ -177,7 +184,6 @@ CONFIG_ARM_THUMB=y
# #
# Bus support # Bus support
# #
CONFIG_ISA_DMA_API=y
# #
# PCCARD (PCMCIA/CardBus) support # PCCARD (PCMCIA/CardBus) support
@ -189,6 +195,8 @@ CONFIG_ISA_DMA_API=y
# #
CONFIG_PREEMPT=y CONFIG_PREEMPT=y
CONFIG_NO_IDLE_HZ=y CONFIG_NO_IDLE_HZ=y
CONFIG_HZ=128
# CONFIG_AEABI is not set
# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set # CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
CONFIG_SELECT_MEMORY_MODEL=y CONFIG_SELECT_MEMORY_MODEL=y
CONFIG_FLATMEM_MANUAL=y CONFIG_FLATMEM_MANUAL=y
@ -249,6 +257,8 @@ CONFIG_BINFMT_AOUT=y
# Power management options # Power management options
# #
CONFIG_PM=y CONFIG_PM=y
CONFIG_PM_LEGACY=y
# CONFIG_PM_DEBUG is not set
# CONFIG_APM is not set # CONFIG_APM is not set
# #
@ -259,9 +269,12 @@ CONFIG_NET=y
# #
# Networking options # Networking options
# #
# CONFIG_NETDEBUG is not set
CONFIG_PACKET=y CONFIG_PACKET=y
# CONFIG_PACKET_MMAP is not set # CONFIG_PACKET_MMAP is not set
CONFIG_UNIX=y CONFIG_UNIX=y
CONFIG_XFRM=y
# CONFIG_XFRM_USER is not set
# CONFIG_NET_KEY is not set # CONFIG_NET_KEY is not set
CONFIG_INET=y CONFIG_INET=y
# CONFIG_IP_MULTICAST is not set # CONFIG_IP_MULTICAST is not set
@ -278,12 +291,18 @@ CONFIG_IP_PNP_BOOTP=y
# CONFIG_INET_AH is not set # CONFIG_INET_AH is not set
# CONFIG_INET_ESP is not set # CONFIG_INET_ESP is not set
# CONFIG_INET_IPCOMP is not set # CONFIG_INET_IPCOMP is not set
# CONFIG_INET_XFRM_TUNNEL is not set
# CONFIG_INET_TUNNEL is not set # CONFIG_INET_TUNNEL is not set
CONFIG_INET_XFRM_MODE_TRANSPORT=y
CONFIG_INET_XFRM_MODE_TUNNEL=y
CONFIG_INET_DIAG=y CONFIG_INET_DIAG=y
CONFIG_INET_TCP_DIAG=y CONFIG_INET_TCP_DIAG=y
# CONFIG_TCP_CONG_ADVANCED is not set # CONFIG_TCP_CONG_ADVANCED is not set
CONFIG_TCP_CONG_BIC=y CONFIG_TCP_CONG_BIC=y
# CONFIG_IPV6 is not set # CONFIG_IPV6 is not set
# CONFIG_INET6_XFRM_TUNNEL is not set
# CONFIG_INET6_TUNNEL is not set
# CONFIG_NETWORK_SECMARK is not set
# CONFIG_NETFILTER is not set # CONFIG_NETFILTER is not set
# #
@ -295,6 +314,11 @@ CONFIG_TCP_CONG_BIC=y
# SCTP Configuration (EXPERIMENTAL) # SCTP Configuration (EXPERIMENTAL)
# #
# CONFIG_IP_SCTP is not set # CONFIG_IP_SCTP is not set
#
# TIPC Configuration (EXPERIMENTAL)
#
# CONFIG_TIPC is not set
# CONFIG_ATM is not set # CONFIG_ATM is not set
# CONFIG_BRIDGE is not set # CONFIG_BRIDGE is not set
# CONFIG_VLAN_8021Q is not set # CONFIG_VLAN_8021Q is not set
@ -312,7 +336,6 @@ CONFIG_TCP_CONG_BIC=y
# QoS and/or fair queueing # QoS and/or fair queueing
# #
# CONFIG_NET_SCHED is not set # CONFIG_NET_SCHED is not set
# CONFIG_NET_CLS_ROUTE is not set
# #
# Network testing # Network testing
@ -333,6 +356,12 @@ CONFIG_TCP_CONG_BIC=y
CONFIG_STANDALONE=y CONFIG_STANDALONE=y
CONFIG_PREVENT_FIRMWARE_BUILD=y CONFIG_PREVENT_FIRMWARE_BUILD=y
# CONFIG_FW_LOADER is not set # CONFIG_FW_LOADER is not set
# CONFIG_SYS_HYPERVISOR is not set
#
# Connector - unified userspace <-> kernelspace linker
#
# CONFIG_CONNECTOR is not set
# #
# Memory Technology Devices (MTD) # Memory Technology Devices (MTD)
@ -526,6 +555,7 @@ CONFIG_SERIO_SERPORT=y
CONFIG_VT=y CONFIG_VT=y
CONFIG_VT_CONSOLE=y CONFIG_VT_CONSOLE=y
CONFIG_HW_CONSOLE=y CONFIG_HW_CONSOLE=y
# CONFIG_VT_HW_CONSOLE_BINDING is not set
# CONFIG_SERIAL_NONSTANDARD is not set # CONFIG_SERIAL_NONSTANDARD is not set
# #
@ -534,6 +564,7 @@ CONFIG_HW_CONSOLE=y
CONFIG_SERIAL_8250=y CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_NR_UARTS=4 CONFIG_SERIAL_8250_NR_UARTS=4
CONFIG_SERIAL_8250_RUNTIME_UARTS=4
# CONFIG_SERIAL_8250_EXTENDED is not set # CONFIG_SERIAL_8250_EXTENDED is not set
# #
@ -559,8 +590,8 @@ CONFIG_WATCHDOG_NOWAYOUT=y
# Watchdog Device Drivers # Watchdog Device Drivers
# #
# CONFIG_SOFT_WATCHDOG is not set # CONFIG_SOFT_WATCHDOG is not set
# CONFIG_HW_RANDOM is not set
# CONFIG_NVRAM is not set # CONFIG_NVRAM is not set
# CONFIG_RTC is not set
# CONFIG_DTLK is not set # CONFIG_DTLK is not set
# CONFIG_R3964 is not set # CONFIG_R3964 is not set
@ -572,6 +603,7 @@ CONFIG_WATCHDOG_NOWAYOUT=y
# #
# TPM devices # TPM devices
# #
# CONFIG_TCG_TPM is not set
# CONFIG_TELCLOCK is not set # CONFIG_TELCLOCK is not set
# #
@ -579,11 +611,23 @@ CONFIG_WATCHDOG_NOWAYOUT=y
# #
# CONFIG_I2C is not set # CONFIG_I2C is not set
#
# SPI support
#
# CONFIG_SPI is not set
# CONFIG_SPI_MASTER is not set
#
# Dallas's 1-wire bus
#
# #
# Hardware Monitoring support # Hardware Monitoring support
# #
CONFIG_HWMON=y CONFIG_HWMON=y
# CONFIG_HWMON_VID is not set # CONFIG_HWMON_VID is not set
# CONFIG_SENSORS_ABITUGURU is not set
# CONFIG_SENSORS_F71805F is not set
# CONFIG_HWMON_DEBUG_CHIP is not set # CONFIG_HWMON_DEBUG_CHIP is not set
# #
@ -591,13 +635,23 @@ CONFIG_HWMON=y
# #
# #
# Multimedia Capabilities Port drivers # LED devices
#
# CONFIG_NEW_LEDS is not set
#
# LED drivers
#
#
# LED Triggers
# #
# #
# Multimedia devices # Multimedia devices
# #
# CONFIG_VIDEO_DEV is not set # CONFIG_VIDEO_DEV is not set
CONFIG_VIDEO_V4L2=y
# #
# Digital Video Broadcasting Devices # Digital Video Broadcasting Devices
@ -607,11 +661,13 @@ CONFIG_HWMON=y
# #
# Graphics support # Graphics support
# #
CONFIG_FIRMWARE_EDID=y
CONFIG_FB=y CONFIG_FB=y
# CONFIG_FB_CFB_FILLRECT is not set # CONFIG_FB_CFB_FILLRECT is not set
# CONFIG_FB_CFB_COPYAREA is not set # CONFIG_FB_CFB_COPYAREA is not set
# CONFIG_FB_CFB_IMAGEBLIT is not set # CONFIG_FB_CFB_IMAGEBLIT is not set
# CONFIG_FB_MACMODES is not set # CONFIG_FB_MACMODES is not set
# CONFIG_FB_BACKLIGHT is not set
CONFIG_FB_MODE_HELPERS=y CONFIG_FB_MODE_HELPERS=y
# CONFIG_FB_TILEBLITTING is not set # CONFIG_FB_TILEBLITTING is not set
# CONFIG_FB_S1D13XXX is not set # CONFIG_FB_S1D13XXX is not set
@ -635,7 +691,6 @@ CONFIG_FONT_8x16=y
# CONFIG_FONT_SUN8x16 is not set # CONFIG_FONT_SUN8x16 is not set
# CONFIG_FONT_SUN12x22 is not set # CONFIG_FONT_SUN12x22 is not set
# CONFIG_FONT_10x18 is not set # CONFIG_FONT_10x18 is not set
# CONFIG_FONT_RL is not set
# #
# Logo configuration # Logo configuration
@ -660,16 +715,15 @@ CONFIG_SOUND=y
# Open Sound System # Open Sound System
# #
CONFIG_SOUND_PRIME=y CONFIG_SOUND_PRIME=y
# CONFIG_OBSOLETE_OSS_DRIVER is not set
# CONFIG_SOUND_MSNDCLAS is not set # CONFIG_SOUND_MSNDCLAS is not set
# CONFIG_SOUND_MSNDPIN is not set # CONFIG_SOUND_MSNDPIN is not set
# CONFIG_SOUND_OSS is not set
# #
# USB support # USB support
# #
CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_HCD=y
CONFIG_USB_ARCH_HAS_OHCI=y CONFIG_USB_ARCH_HAS_OHCI=y
# CONFIG_USB_ARCH_HAS_EHCI is not set
# CONFIG_USB is not set # CONFIG_USB is not set
# #
@ -680,23 +734,18 @@ CONFIG_USB_ARCH_HAS_OHCI=y
# USB Gadget Support # USB Gadget Support
# #
# CONFIG_USB_GADGET is not set # CONFIG_USB_GADGET is not set
# CONFIG_USB_GADGET_NET2280 is not set
# CONFIG_USB_GADGET_PXA2XX is not set
# CONFIG_USB_GADGET_GOKU is not set
# CONFIG_USB_GADGET_LH7A40X is not set
# CONFIG_USB_GADGET_OMAP is not set
# CONFIG_USB_GADGET_DUMMY_HCD is not set
# CONFIG_USB_ZERO is not set
# CONFIG_USB_ETH is not set
# CONFIG_USB_GADGETFS is not set
# CONFIG_USB_FILE_STORAGE is not set
# CONFIG_USB_G_SERIAL is not set
# #
# MMC/SD Card support # MMC/SD Card support
# #
# CONFIG_MMC is not set # CONFIG_MMC is not set
#
# Real Time Clock
#
CONFIG_RTC_LIB=y
# CONFIG_RTC_CLASS is not set
# #
# File systems # File systems
# #
@ -704,14 +753,15 @@ CONFIG_EXT2_FS=y
# CONFIG_EXT2_FS_XATTR is not set # CONFIG_EXT2_FS_XATTR is not set
# CONFIG_EXT2_FS_XIP is not set # CONFIG_EXT2_FS_XIP is not set
# CONFIG_EXT3_FS is not set # CONFIG_EXT3_FS is not set
# CONFIG_JBD is not set
# CONFIG_REISERFS_FS is not set # CONFIG_REISERFS_FS is not set
# CONFIG_JFS_FS is not set # CONFIG_JFS_FS is not set
# CONFIG_FS_POSIX_ACL is not set # CONFIG_FS_POSIX_ACL is not set
# CONFIG_XFS_FS is not set # CONFIG_XFS_FS is not set
# CONFIG_OCFS2_FS is not set
# CONFIG_MINIX_FS is not set # CONFIG_MINIX_FS is not set
CONFIG_ROMFS_FS=y CONFIG_ROMFS_FS=y
CONFIG_INOTIFY=y CONFIG_INOTIFY=y
CONFIG_INOTIFY_USER=y
# CONFIG_QUOTA is not set # CONFIG_QUOTA is not set
CONFIG_DNOTIFY=y CONFIG_DNOTIFY=y
# CONFIG_AUTOFS_FS is not set # CONFIG_AUTOFS_FS is not set
@ -741,7 +791,7 @@ CONFIG_SYSFS=y
# CONFIG_TMPFS is not set # CONFIG_TMPFS is not set
# CONFIG_HUGETLB_PAGE is not set # CONFIG_HUGETLB_PAGE is not set
CONFIG_RAMFS=y CONFIG_RAMFS=y
# CONFIG_RELAYFS_FS is not set # CONFIG_CONFIGFS_FS is not set
# #
# Miscellaneous filesystems # Miscellaneous filesystems
@ -843,10 +893,13 @@ CONFIG_NLS_DEFAULT="iso8859-1"
# Kernel hacking # Kernel hacking
# #
# CONFIG_PRINTK_TIME is not set # CONFIG_PRINTK_TIME is not set
# CONFIG_MAGIC_SYSRQ is not set
# CONFIG_DEBUG_KERNEL is not set # CONFIG_DEBUG_KERNEL is not set
CONFIG_LOG_BUF_SHIFT=14 CONFIG_LOG_BUF_SHIFT=14
CONFIG_DEBUG_BUGVERBOSE=y CONFIG_DEBUG_BUGVERBOSE=y
# CONFIG_DEBUG_FS is not set
CONFIG_FRAME_POINTER=y CONFIG_FRAME_POINTER=y
# CONFIG_UNWIND_INFO is not set
# CONFIG_DEBUG_USER is not set # CONFIG_DEBUG_USER is not set
# #

1
arch/arm/configs/onearm_defconfig
View File

@ -85,6 +85,7 @@ CONFIG_DEFAULT_IOSCHED="anticipatory"
# CONFIG_ARCH_INTEGRATOR is not set # CONFIG_ARCH_INTEGRATOR is not set
# CONFIG_ARCH_REALVIEW is not set # CONFIG_ARCH_REALVIEW is not set
# CONFIG_ARCH_VERSATILE is not set # CONFIG_ARCH_VERSATILE is not set
CONFIG_ARCH_AT91=y
CONFIG_ARCH_AT91RM9200=y CONFIG_ARCH_AT91RM9200=y
# CONFIG_ARCH_CLPS7500 is not set # CONFIG_ARCH_CLPS7500 is not set
# CONFIG_ARCH_CLPS711X is not set # CONFIG_ARCH_CLPS711X is not set

1579
arch/arm/configs/trizeps4_defconfig Normal file
View File

File diff suppressed because it is too large Load Diff

2
arch/arm/kernel/Makefile
View File

@ -25,7 +25,7 @@ obj-$(CONFIG_OABI_COMPAT) += sys_oabi-compat.o
obj-$(CONFIG_CRUNCH) += crunch.o crunch-bits.o obj-$(CONFIG_CRUNCH) += crunch.o crunch-bits.o
AFLAGS_crunch-bits.o := -Wa,-mcpu=ep9312 AFLAGS_crunch-bits.o := -Wa,-mcpu=ep9312
obj-$(CONFIG_IWMMXT) += iwmmxt.o obj-$(CONFIG_IWMMXT) += iwmmxt.o iwmmxt-notifier.o
AFLAGS_iwmmxt.o := -Wa,-mcpu=iwmmxt AFLAGS_iwmmxt.o := -Wa,-mcpu=iwmmxt
ifneq ($(CONFIG_ARCH_EBSA110),y) ifneq ($(CONFIG_ARCH_EBSA110),y)

3
arch/arm/kernel/asm-offsets.c
View File

@ -105,6 +105,7 @@ int main(void)
BLANK(); BLANK();
DEFINE(PROC_INFO_SZ, sizeof(struct proc_info_list)); DEFINE(PROC_INFO_SZ, sizeof(struct proc_info_list));
DEFINE(PROCINFO_INITFUNC, offsetof(struct proc_info_list, __cpu_flush)); DEFINE(PROCINFO_INITFUNC, offsetof(struct proc_info_list, __cpu_flush));
DEFINE(PROCINFO_MMUFLAGS, offsetof(struct proc_info_list, __cpu_mmu_flags)); DEFINE(PROCINFO_MM_MMUFLAGS, offsetof(struct proc_info_list, __cpu_mm_mmu_flags));
DEFINE(PROCINFO_IO_MMUFLAGS, offsetof(struct proc_info_list, __cpu_io_mmu_flags));
return 0; return 0;
} }

4
arch/arm/kernel/entry-armv.S
View File

@ -589,9 +589,7 @@ ENTRY(__switch_to)
#ifdef CONFIG_MMU #ifdef CONFIG_MMU
mcr p15, 0, r6, c3, c0, 0 @ Set domain register mcr p15, 0, r6, c3, c0, 0 @ Set domain register
#endif #endif
#if defined(CONFIG_IWMMXT) #if defined(CONFIG_CPU_XSCALE) && !defined(CONFIG_IWMMXT)
bl iwmmxt_task_switch
#elif defined(CONFIG_CPU_XSCALE)
add r4, r2, #TI_CPU_DOMAIN + 40 @ cpu_context_save->extra add r4, r2, #TI_CPU_DOMAIN + 40 @ cpu_context_save->extra
ldmib r4, {r4, r5} ldmib r4, {r4, r5}
mar acc0, r4, r5 mar acc0, r4, r5

5
arch/arm/kernel/head.S
View File

@ -220,7 +220,7 @@ __create_page_tables:
teq r0, r6 teq r0, r6
bne 1b bne 1b
ldr r7, [r10, #PROCINFO_MMUFLAGS] @ mmuflags ldr r7, [r10, #PROCINFO_MM_MMUFLAGS] @ mm_mmuflags
/* /*
* Create identity mapping for first MB of kernel to * Create identity mapping for first MB of kernel to
@ -271,8 +271,7 @@ __create_page_tables:
#endif #endif
#ifdef CONFIG_DEBUG_LL #ifdef CONFIG_DEBUG_LL
bic r7, r7, #0x0c @ turn off cacheable ldr r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags
@ and bufferable bits
/* /*
* Map in IO space for serial debugging. * Map in IO space for serial debugging.
* This allows debug messages to be output * This allows debug messages to be output

64
arch/arm/kernel/iwmmxt-notifier.c Normal file
View File

@ -0,0 +1,64 @@
/*
* linux/arch/arm/kernel/iwmmxt-notifier.c
*
* XScale iWMMXt (Concan) context switching and handling
*
* Initial code:
* Copyright (c) 2003, Intel Corporation
*
* Full lazy switching support, optimizations and more, by Nicolas Pitre
* Copyright (c) 2003-2004, MontaVista Software, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/module.h>
#include <linux/config.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/signal.h>
#include <linux/sched.h>
#include <linux/init.h>
#include <asm/thread_notify.h>
#include <asm/io.h>
static int iwmmxt_do(struct notifier_block *self, unsigned long cmd, void *t)
{
struct thread_info *thread = t;
switch (cmd) {
case THREAD_NOTIFY_FLUSH:
/*
* flush_thread() zeroes thread->fpstate, so no need
* to do anything here.
*
* FALLTHROUGH: Ensure we don't try to overwrite our newly
* initialised state information on the first fault.
*/
case THREAD_NOTIFY_RELEASE:
iwmmxt_task_release(thread);
break;
case THREAD_NOTIFY_SWITCH:
iwmmxt_task_switch(thread);
break;
}
return NOTIFY_DONE;
}
static struct notifier_block iwmmxt_notifier_block = {
.notifier_call = iwmmxt_do,
};
static int __init iwmmxt_init(void)
{
thread_register_notifier(&iwmmxt_notifier_block);
return 0;
}
late_initcall(iwmmxt_init);

27
arch/arm/kernel/iwmmxt.S
View File

@ -271,30 +271,27 @@ ENTRY(iwmmxt_task_restore)
/* /*
* Concan handling on task switch * Concan handling on task switch
* *
* r0 = previous task_struct pointer (must be preserved) * r0 = next thread_info pointer
* r1 = previous thread_info pointer
* r2 = next thread_info pointer (must be preserved)
* *
* Called only from __switch_to with task preemption disabled. * Called only from the iwmmxt notifier with task preemption disabled.
* No need to care about preserving r4 and above.
*/ */
ENTRY(iwmmxt_task_switch) ENTRY(iwmmxt_task_switch)
mrc p15, 0, r4, c15, c1, 0 mrc p15, 0, r1, c15, c1, 0
tst r4, #0x3 @ CP0 and CP1 accessible? tst r1, #0x3 @ CP0 and CP1 accessible?
bne 1f @ yes: block them for next task bne 1f @ yes: block them for next task
ldr r5, =concan_owner ldr r2, =concan_owner
add r6, r2, #TI_IWMMXT_STATE @ get next task Concan save area add r3, r0, #TI_IWMMXT_STATE @ get next task Concan save area
ldr r5, [r5] @ get current Concan owner ldr r2, [r2] @ get current Concan owner
teq r5, r6 @ next task owns it? teq r2, r3 @ next task owns it?
movne pc, lr @ no: leave Concan disabled movne pc, lr @ no: leave Concan disabled
1: eor r4, r4, #3 @ flip Concan access 1: eor r1, r1, #3 @ flip Concan access
mcr p15, 0, r4, c15, c1, 0 mcr p15, 0, r1, c15, c1, 0
mrc p15, 0, r4, c2, c0, 0 mrc p15, 0, r1, c2, c0, 0
sub pc, lr, r4, lsr #32 @ cpwait and return sub pc, lr, r1, lsr #32 @ cpwait and return
/* /*
* Remove Concan ownership of given task * Remove Concan ownership of given task

6
arch/arm/kernel/process.c
View File

@ -352,9 +352,6 @@ void flush_thread(void)
memset(&thread->fpstate, 0, sizeof(union fp_state)); memset(&thread->fpstate, 0, sizeof(union fp_state));
thread_notify(THREAD_NOTIFY_FLUSH, thread); thread_notify(THREAD_NOTIFY_FLUSH, thread);
#if defined(CONFIG_IWMMXT)
iwmmxt_task_release(thread);
#endif
} }
void release_thread(struct task_struct *dead_task) void release_thread(struct task_struct *dead_task)
@ -362,9 +359,6 @@ void release_thread(struct task_struct *dead_task)
struct thread_info *thread = task_thread_info(dead_task); struct thread_info *thread = task_thread_info(dead_task);
thread_notify(THREAD_NOTIFY_RELEASE, thread); thread_notify(THREAD_NOTIFY_RELEASE, thread);
#if defined(CONFIG_IWMMXT)
iwmmxt_task_release(thread);
#endif
} }
asmlinkage void ret_from_fork(void) __asm__("ret_from_fork"); asmlinkage void ret_from_fork(void) __asm__("ret_from_fork");

4
arch/arm/kernel/setup.c
View File

@ -344,9 +344,9 @@ static void __init setup_processor(void)
cpu_cache = *list->cache; cpu_cache = *list->cache;
#endif #endif
printk("CPU: %s [%08x] revision %d (ARMv%s)\n", printk("CPU: %s [%08x] revision %d (ARMv%s), cr=%08x\n",
cpu_name, processor_id, (int)processor_id & 15, cpu_name, processor_id, (int)processor_id & 15,
proc_arch[cpu_architecture()]); proc_arch[cpu_architecture()], cr_alignment);
sprintf(system_utsname.machine, "%s%c", list->arch_name, ENDIANNESS); sprintf(system_utsname.machine, "%s%c", list->arch_name, ENDIANNESS);
sprintf(elf_platform, "%s%c", list->elf_name, ENDIANNESS); sprintf(elf_platform, "%s%c", list->elf_name, ENDIANNESS);

86
arch/arm/mach-at91rm9200/Kconfig
View File

@ -1,6 +1,21 @@
if ARCH_AT91RM9200 if ARCH_AT91
menu "AT91RM9200 Implementations" menu "Atmel AT91 System-on-Chip"
comment "Atmel AT91 Processors"
config ARCH_AT91RM9200
bool "AT91RM9200"
config ARCH_AT91SAM9260
bool "AT91SAM9260"
config ARCH_AT91SAM9261
bool "AT91SAM9261"
# ----------------------------------------------------------
if ARCH_AT91RM9200
comment "AT91RM9200 Board Type" comment "AT91RM9200 Board Type"
@ -8,58 +23,87 @@ config MACH_ONEARM
bool "Ajeco 1ARM Single Board Computer" bool "Ajeco 1ARM Single Board Computer"
depends on ARCH_AT91RM9200 depends on ARCH_AT91RM9200
help help
Select this if you are using Ajeco's 1ARM Single Board Computer Select this if you are using Ajeco's 1ARM Single Board Computer.
<http://www.ajeco.fi/products.htm>
config ARCH_AT91RM9200DK config ARCH_AT91RM9200DK
bool "Atmel AT91RM9200-DK Development board" bool "Atmel AT91RM9200-DK Development board"
depends on ARCH_AT91RM9200 depends on ARCH_AT91RM9200
help help
Select this if you are using Atmel's AT91RM9200-DK Development board Select this if you are using Atmel's AT91RM9200-DK Development board.
(Discontinued)
config MACH_AT91RM9200EK config MACH_AT91RM9200EK
bool "Atmel AT91RM9200-EK Evaluation Kit" bool "Atmel AT91RM9200-EK Evaluation Kit"
depends on ARCH_AT91RM9200 depends on ARCH_AT91RM9200
help help
Select this if you are using Atmel's AT91RM9200-EK Evaluation Kit Select this if you are using Atmel's AT91RM9200-EK Evaluation Kit.
<http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3507>
config MACH_CSB337 config MACH_CSB337
bool "Cogent CSB337 board" bool "Cogent CSB337"
depends on ARCH_AT91RM9200 depends on ARCH_AT91RM9200
help help
Select this if you are using Cogent's CSB337 board Select this if you are using Cogent's CSB337 board.
<http://www.cogcomp.com/csb_csb337.htm>
config MACH_CSB637 config MACH_CSB637
bool "Cogent CSB637 board" bool "Cogent CSB637"
depends on ARCH_AT91RM9200 depends on ARCH_AT91RM9200
help help
Select this if you are using Cogent's CSB637 board Select this if you are using Cogent's CSB637 board.
<http://www.cogcomp.com/csb_csb637.htm>
config MACH_CARMEVA config MACH_CARMEVA
bool "Conitec's ARM&EVA" bool "Conitec ARM&EVA"
depends on ARCH_AT91RM9200 depends on ARCH_AT91RM9200
help help
Select this if you are using Conitec's AT91RM9200-MCU-Module Select this if you are using Conitec's AT91RM9200-MCU-Module.
<http://www.conitec.net/english/linuxboard.htm>
config MACH_KB9200
bool "KwikByte's KB920x"
depends on ARCH_AT91RM9200
help
Select this if you are using KwikByte's KB920x board
config MACH_ATEB9200 config MACH_ATEB9200
bool "Embest's ATEB9200" bool "Embest ATEB9200"
depends on ARCH_AT91RM9200 depends on ARCH_AT91RM9200
help help
Select this if you are using Embest's ATEB9200 board Select this if you are using Embest's ATEB9200 board.
<http://www.embedinfo.com/english/product/ATEB9200.asp>
config MACH_KB9200
bool "KwikByte KB920x"
depends on ARCH_AT91RM9200
help
Select this if you are using KwikByte's KB920x board.
<http://kwikbyte.com/KB9202_description_new.htm>
config MACH_KAFA config MACH_KAFA
bool "Sperry-Sun KAFA board" bool "Sperry-Sun KAFA board"
depends on ARCH_AT91RM9200 depends on ARCH_AT91RM9200
help help
Select this if you are using Sperry-Sun's KAFA board Select this if you are using Sperry-Sun's KAFA board.
endif
# ----------------------------------------------------------
if ARCH_AT91SAM9260
comment "AT91SAM9260 Board Type"
endif
# ----------------------------------------------------------
if ARCH_AT91SAM9261
comment "AT91SAM9261 Board Type"
endif
comment "AT91RM9200 Feature Selections" # ----------------------------------------------------------
comment "AT91 Feature Selections"
config AT91_PROGRAMMABLE_CLOCKS config AT91_PROGRAMMABLE_CLOCKS
bool "Programmable Clocks" bool "Programmable Clocks"

13
arch/arm/mach-at91rm9200/Makefile
View File

@ -2,14 +2,19 @@
# Makefile for the linux kernel. # Makefile for the linux kernel.
# #
obj-y := clock.o irq.o time.o gpio.o common.o devices.o obj-y := clock.o irq.o gpio.o devices.o
obj-m := obj-m :=
obj-n := obj-n :=
obj- := obj- :=
obj-$(CONFIG_PM) += pm.o obj-$(CONFIG_PM) += pm.o
# Board-specific support # CPU-specific support
obj-$(CONFIG_ARCH_AT91RM9200) += at91rm9200.o at91rm9200_time.o
obj-$(CONFIG_ARCH_AT91SAM9260) +=
obj-$(CONFIG_ARCH_AT91SAM9261) +=
# AT91RM9200 Board-specific support
obj-$(CONFIG_MACH_ONEARM) += board-1arm.o obj-$(CONFIG_MACH_ONEARM) += board-1arm.o
obj-$(CONFIG_ARCH_AT91RM9200DK) += board-dk.o obj-$(CONFIG_ARCH_AT91RM9200DK) += board-dk.o
obj-$(CONFIG_MACH_AT91RM9200EK) += board-ek.o obj-$(CONFIG_MACH_AT91RM9200EK) += board-ek.o
@ -20,6 +25,10 @@ obj-$(CONFIG_MACH_KB9200) += board-kb9202.o
obj-$(CONFIG_MACH_ATEB9200) += board-eb9200.o obj-$(CONFIG_MACH_ATEB9200) += board-eb9200.o
obj-$(CONFIG_MACH_KAFA) += board-kafa.o obj-$(CONFIG_MACH_KAFA) += board-kafa.o
# AT91SAM9260 board-specific support
# AT91SAM9261 board-specific support
# LEDs support # LEDs support
led-$(CONFIG_ARCH_AT91RM9200DK) += leds.o led-$(CONFIG_ARCH_AT91RM9200DK) += leds.o
led-$(CONFIG_MACH_AT91RM9200EK) += leds.o led-$(CONFIG_MACH_AT91RM9200EK) += leds.o

2
arch/arm/mach-at91rm9200/common.c → arch/arm/mach-at91rm9200/at91rm9200.c
View File

@ -1,5 +1,5 @@
/* /*
* arch/arm/mach-at91rm9200/common.c * arch/arm/mach-at91rm9200/at91rm9200.c
* *
* Copyright (C) 2005 SAN People * Copyright (C) 2005 SAN People
* *

2
arch/arm/mach-at91rm9200/time.c → arch/arm/mach-at91rm9200/at91rm9200_time.c
View File

@ -1,5 +1,5 @@
/* /*
* linux/arch/arm/mach-at91rm9200/time.c * linux/arch/arm/mach-at91rm9200/at91rm9200_time.c
* *
* Copyright (C) 2003 SAN People * Copyright (C) 2003 SAN People
* Copyright (C) 2003 ATMEL * Copyright (C) 2003 ATMEL

12
arch/arm/mach-ep93xx/Kconfig
View File

@ -9,12 +9,24 @@ config CRUNCH
comment "EP93xx Platforms" comment "EP93xx Platforms"
config MACH_EDB9302
bool "Support Cirrus Logic EDB9302"
help
Say 'Y' here if you want your kernel to support the Cirrus
Logic EDB9302 Evaluation Board.
config MACH_EDB9315 config MACH_EDB9315
bool "Support Cirrus Logic EDB9315" bool "Support Cirrus Logic EDB9315"
help help
Say 'Y' here if you want your kernel to support the Cirrus Say 'Y' here if you want your kernel to support the Cirrus
Logic EDB9315 Evaluation Board. Logic EDB9315 Evaluation Board.
config MACH_EDB9315A
bool "Support Cirrus Logic EDB9315A"
help
Say 'Y' here if you want your kernel to support the Cirrus
Logic EDB9315A Evaluation Board.
config MACH_GESBC9312 config MACH_GESBC9312
bool "Support Glomation GESBC-9312-sx" bool "Support Glomation GESBC-9312-sx"
help help

2
arch/arm/mach-ep93xx/Makefile
View File

@ -6,6 +6,8 @@ obj-m :=
obj-n := obj-n :=
obj- := obj- :=
obj-$(CONFIG_MACH_EDB9302) += edb9302.o
obj-$(CONFIG_MACH_EDB9315) += edb9315.o obj-$(CONFIG_MACH_EDB9315) += edb9315.o
obj-$(CONFIG_MACH_EDB9315A) += edb9315a.o
obj-$(CONFIG_MACH_GESBC9312) += gesbc9312.o obj-$(CONFIG_MACH_GESBC9312) += gesbc9312.o
obj-$(CONFIG_MACH_TS72XX) += ts72xx.o obj-$(CONFIG_MACH_TS72XX) += ts72xx.o

62
arch/arm/mach-ep93xx/edb9302.c Normal file
View File

@ -0,0 +1,62 @@
/*
* arch/arm/mach-ep93xx/edb9302.c
* Cirrus Logic EDB9302 support.
*
* Copyright (C) 2006 George Kashperko <george@chas.com.ua>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or (at
* your option) any later version.
*/
#include <linux/config.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/mm.h>
#include <linux/sched.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/mtd/physmap.h>
#include <linux/platform_device.h>
#include <asm/io.h>
#include <asm/hardware.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
static struct physmap_flash_data edb9302_flash_data = {
.width = 2,
};
static struct resource edb9302_flash_resource = {
.start = 0x60000000,
.end = 0x60ffffff,
.flags = IORESOURCE_MEM,
};
static struct platform_device edb9302_flash = {
.name = "physmap-flash",
.id = 0,
.dev = {
.platform_data = &edb9302_flash_data,
},
.num_resources = 1,
.resource = &edb9302_flash_resource,
};
static void __init edb9302_init_machine(void)
{
ep93xx_init_devices();
platform_device_register(&edb9302_flash);
}
MACHINE_START(EDB9302, "Cirrus Logic EDB9302 Evaluation Board")
/* Maintainer: George Kashperko <george@chas.com.ua> */
.phys_io = EP93XX_APB_PHYS_BASE,
.io_pg_offst = ((EP93XX_APB_VIRT_BASE) >> 18) & 0xfffc,
.boot_params = 0x00000100,
.map_io = ep93xx_map_io,
.init_irq = ep93xx_init_irq,
.timer = &ep93xx_timer,
.init_machine = edb9302_init_machine,
MACHINE_END

62
arch/arm/mach-ep93xx/edb9315a.c Normal file
View File

@ -0,0 +1,62 @@
/*
* arch/arm/mach-ep93xx/edb9315a.c
* Cirrus Logic EDB9315A support.
*
* Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or (at
* your option) any later version.
*/
#include <linux/config.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/mm.h>
#include <linux/sched.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/mtd/physmap.h>
#include <linux/platform_device.h>
#include <asm/io.h>
#include <asm/hardware.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
static struct physmap_flash_data edb9315a_flash_data = {
.width = 2,
};
static struct resource edb9315a_flash_resource = {
.start = 0x60000000,
.end = 0x60ffffff,
.flags = IORESOURCE_MEM,
};
static struct platform_device edb9315a_flash = {
.name = "physmap-flash",
.id = 0,
.dev = {
.platform_data = &edb9315a_flash_data,
},
.num_resources = 1,
.resource = &edb9315a_flash_resource,
};
static void __init edb9315a_init_machine(void)
{
ep93xx_init_devices();
platform_device_register(&edb9315a_flash);
}
MACHINE_START(EDB9315A, "Cirrus Logic EDB9315A Evaluation Board")
/* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */
.phys_io = EP93XX_APB_PHYS_BASE,
.io_pg_offst = ((EP93XX_APB_VIRT_BASE) >> 18) & 0xfffc,
.boot_params = 0xc0000100,
.map_io = ep93xx_map_io,
.init_irq = ep93xx_init_irq,
.timer = &ep93xx_timer,
.init_machine = edb9315a_init_machine,
MACHINE_END

15
arch/arm/mach-iop3xx/Kconfig
View File

@ -30,12 +30,15 @@ config MACH_IQ80332
select ARCH_IOP331 select ARCH_IOP331
help help
Say Y here if you want to run your kernel on the Intel IQ80332 Say Y here if you want to run your kernel on the Intel IQ80332
evaluation kit for the IOP332 chipset evaluation kit for the IOP332 chipset.
config ARCH_EP80219 config ARCH_EP80219
bool "Enable support for EP80219" bool "Enable support for EP80219"
select ARCH_IOP321 select ARCH_IOP321
select ARCH_IQ31244 select ARCH_IQ31244
help
Say Y here if you want to run your kernel on the Intel EP80219
evaluation kit for the Intel 80219 chipset (a IOP321 variant).
# Which IOP variant are we running? # Which IOP variant are we running?
config ARCH_IOP321 config ARCH_IOP321
@ -56,8 +59,8 @@ config IOP331_STEPD
bool "Chip stepping D of the IOP80331 processor or IOP80333" bool "Chip stepping D of the IOP80331 processor or IOP80333"
depends on (ARCH_IOP331) depends on (ARCH_IOP331)
help help
Say Y here if you have StepD of the IOP80331 or IOP8033 Say Y here if you have StepD of the IOP80331 or IOP8033
based platforms. based platforms.
endmenu endmenu
endif endif

7
arch/arm/mach-omap1/Kconfig
View File

@ -62,6 +62,13 @@ config MACH_OMAP_PERSEUS2
Support for TI OMAP 730 Perseus2 board. Say Y here if you have such Support for TI OMAP 730 Perseus2 board. Say Y here if you have such
a board. a board.
config MACH_OMAP_FSAMPLE
bool "TI F-Sample"
depends on ARCH_OMAP1 && ARCH_OMAP730
help
Support for TI OMAP 850 F-Sample board. Say Y here if you have such
a board.
config MACH_VOICEBLUE config MACH_VOICEBLUE
bool "Voiceblue" bool "Voiceblue"
depends on ARCH_OMAP1 && ARCH_OMAP15XX depends on ARCH_OMAP1 && ARCH_OMAP15XX

1
arch/arm/mach-omap1/Makefile
View File

@ -17,6 +17,7 @@ obj-$(CONFIG_MACH_OMAP_H2) += board-h2.o
obj-$(CONFIG_MACH_OMAP_INNOVATOR) += board-innovator.o obj-$(CONFIG_MACH_OMAP_INNOVATOR) += board-innovator.o
obj-$(CONFIG_MACH_OMAP_GENERIC) += board-generic.o obj-$(CONFIG_MACH_OMAP_GENERIC) += board-generic.o
obj-$(CONFIG_MACH_OMAP_PERSEUS2) += board-perseus2.o obj-$(CONFIG_MACH_OMAP_PERSEUS2) += board-perseus2.o
obj-$(CONFIG_MACH_OMAP_FSAMPLE) += board-fsample.o
obj-$(CONFIG_MACH_OMAP_OSK) += board-osk.o obj-$(CONFIG_MACH_OMAP_OSK) += board-osk.o
obj-$(CONFIG_MACH_OMAP_H3) += board-h3.o obj-$(CONFIG_MACH_OMAP_H3) += board-h3.o
obj-$(CONFIG_MACH_VOICEBLUE) += board-voiceblue.o obj-$(CONFIG_MACH_VOICEBLUE) += board-voiceblue.o

7
arch/arm/mach-omap1/board-ams-delta.c
View File

@ -80,8 +80,15 @@ static struct omap_uart_config ams_delta_uart_config __initdata = {
.enabled_uarts = 1, .enabled_uarts = 1,
}; };
static struct omap_usb_config ams_delta_usb_config __initdata = {
.register_host = 1,
.hmc_mode = 16,
.pins[0] = 2,
};
static struct omap_board_config_kernel ams_delta_config[] = { static struct omap_board_config_kernel ams_delta_config[] = {
{ OMAP_TAG_UART, &ams_delta_uart_config }, { OMAP_TAG_UART, &ams_delta_uart_config },
{ OMAP_TAG_USB, &ams_delta_usb_config },
}; };
static struct platform_device ams_delta_led_device = { static struct platform_device ams_delta_led_device = {

319
arch/arm/mach-omap1/board-fsample.c Normal file
View File

@ -0,0 +1,319 @@
/*
* linux/arch/arm/mach-omap1/board-fsample.c
*
* Modified from board-perseus2.c
*
* Original OMAP730 support by Jean Pihet <j-pihet@ti.com>
* Updated for 2.6 by Kevin Hilman <kjh@hilman.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/partitions.h>
#include <linux/input.h>
#include <asm/hardware.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/flash.h>
#include <asm/mach/map.h>
#include <asm/arch/tc.h>
#include <asm/arch/gpio.h>
#include <asm/arch/mux.h>
#include <asm/arch/fpga.h>
#include <asm/arch/keypad.h>
#include <asm/arch/common.h>
#include <asm/arch/board.h>
#include <asm/arch/board-fsample.h>
static int fsample_keymap[] = {
KEY(0,0,KEY_UP),
KEY(0,1,KEY_RIGHT),
KEY(0,2,KEY_LEFT),
KEY(0,3,KEY_DOWN),
KEY(0,4,KEY_CENTER),
KEY(0,5,KEY_0_5),
KEY(1,0,KEY_SOFT2),
KEY(1,1,KEY_SEND),
KEY(1,2,KEY_END),
KEY(1,3,KEY_VOLUMEDOWN),
KEY(1,4,KEY_VOLUMEUP),
KEY(1,5,KEY_RECORD),
KEY(2,0,KEY_SOFT1),
KEY(2,1,KEY_3),
KEY(2,2,KEY_6),
KEY(2,3,KEY_9),
KEY(2,4,KEY_SHARP),
KEY(2,5,KEY_2_5),
KEY(3,0,KEY_BACK),
KEY(3,1,KEY_2),
KEY(3,2,KEY_5),
KEY(3,3,KEY_8),
KEY(3,4,KEY_0),
KEY(3,5,KEY_HEADSETHOOK),
KEY(4,0,KEY_HOME),
KEY(4,1,KEY_1),
KEY(4,2,KEY_4),
KEY(4,3,KEY_7),
KEY(4,4,KEY_STAR),
KEY(4,5,KEY_POWER),
0
};
static struct resource smc91x_resources[] = {
[0] = {
.start = H2P2_DBG_FPGA_ETHR_START, /* Physical */
.end = H2P2_DBG_FPGA_ETHR_START + 0xf,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = INT_730_MPU_EXT_NIRQ,
.end = 0,
.flags = IORESOURCE_IRQ,
},
};
static struct mtd_partition nor_partitions[] = {
/* bootloader (U-Boot, etc) in first sector */
{
.name = "bootloader",
.offset = 0,
.size = SZ_128K,
.mask_flags = MTD_WRITEABLE, /* force read-only */
},
/* bootloader params in the next sector */
{
.name = "params",
.offset = MTDPART_OFS_APPEND,
.size = SZ_128K,
.mask_flags = 0,
},
/* kernel */
{
.name = "kernel",
.offset = MTDPART_OFS_APPEND,
.size = SZ_2M,
.mask_flags = 0
},
/* rest of flash is a file system */
{
.name = "rootfs",
.offset = MTDPART_OFS_APPEND,
.size = MTDPART_SIZ_FULL,
.mask_flags = 0
},
};
static struct flash_platform_data nor_data = {
.map_name = "cfi_probe",
.width = 2,
.parts = nor_partitions,
.nr_parts = ARRAY_SIZE(nor_partitions),
};
static struct resource nor_resource = {
.start = OMAP_CS0_PHYS,
.end = OMAP_CS0_PHYS + SZ_32M - 1,
.flags = IORESOURCE_MEM,
};
static struct platform_device nor_device = {
.name = "omapflash",
.id = 0,
.dev = {
.platform_data = &nor_data,
},
.num_resources = 1,
.resource = &nor_resource,
};
static struct nand_platform_data nand_data = {
.options = NAND_SAMSUNG_LP_OPTIONS,
};
static struct resource nand_resource = {
.start = OMAP_CS3_PHYS,
.end = OMAP_CS3_PHYS + SZ_4K - 1,
.flags = IORESOURCE_MEM,
};
static struct platform_device nand_device = {
.name = "omapnand",
.id = 0,
.dev = {
.platform_data = &nand_data,
},
.num_resources = 1,
.resource = &nand_resource,
};
static struct platform_device smc91x_device = {
.name = "smc91x",
.id = 0,
.num_resources = ARRAY_SIZE(smc91x_resources),
.resource = smc91x_resources,
};
static struct resource kp_resources[] = {
[0] = {
.start = INT_730_MPUIO_KEYPAD,
.end = INT_730_MPUIO_KEYPAD,
.flags = IORESOURCE_IRQ,
},
};
static struct omap_kp_platform_data kp_data = {
.rows = 8,
.cols = 8,
.keymap = fsample_keymap,
};
static struct platform_device kp_device = {
.name = "omap-keypad",
.id = -1,
.dev = {
.platform_data = &kp_data,
},
.num_resources = ARRAY_SIZE(kp_resources),
.resource = kp_resources,
};
static struct platform_device lcd_device = {
.name = "lcd_p2",
.id = -1,
};
static struct platform_device *devices[] __initdata = {
&nor_device,
&nand_device,
&smc91x_device,
&kp_device,
&lcd_device,
};
#define P2_NAND_RB_GPIO_PIN 62
static int nand_dev_ready(struct nand_platform_data *data)
{
return omap_get_gpio_datain(P2_NAND_RB_GPIO_PIN);
}
static struct omap_uart_config fsample_uart_config __initdata = {
.enabled_uarts = ((1 << 0) | (1 << 1)),
};
static struct omap_lcd_config fsample_lcd_config __initdata = {
.ctrl_name = "internal",
};
static struct omap_board_config_kernel fsample_config[] = {
{ OMAP_TAG_UART, &fsample_uart_config },
{ OMAP_TAG_LCD, &fsample_lcd_config },
};
static void __init omap_fsample_init(void)
{
if (!(omap_request_gpio(P2_NAND_RB_GPIO_PIN)))
nand_data.dev_ready = nand_dev_ready;
omap_cfg_reg(L3_1610_FLASH_CS2B_OE);
omap_cfg_reg(M8_1610_FLASH_CS2B_WE);
platform_add_devices(devices, ARRAY_SIZE(devices));
omap_board_config = fsample_config;
omap_board_config_size = ARRAY_SIZE(fsample_config);
omap_serial_init();
}
static void __init fsample_init_smc91x(void)
{
fpga_write(1, H2P2_DBG_FPGA_LAN_RESET);
mdelay(50);
fpga_write(fpga_read(H2P2_DBG_FPGA_LAN_RESET) & ~1,
H2P2_DBG_FPGA_LAN_RESET);
mdelay(50);
}
void omap_fsample_init_irq(void)
{
omap1_init_common_hw();
omap_init_irq();
omap_gpio_init();
fsample_init_smc91x();
}
/* Only FPGA needs to be mapped here. All others are done with ioremap */
static struct map_desc omap_fsample_io_desc[] __initdata = {
{
.virtual = H2P2_DBG_FPGA_BASE,
.pfn = __phys_to_pfn(H2P2_DBG_FPGA_START),
.length = H2P2_DBG_FPGA_SIZE,
.type = MT_DEVICE
},
{
.virtual = FSAMPLE_CPLD_BASE,
.pfn = __phys_to_pfn(FSAMPLE_CPLD_START),
.length = FSAMPLE_CPLD_SIZE,
.type = MT_DEVICE
}
};
static void __init omap_fsample_map_io(void)
{
omap1_map_common_io();
iotable_init(omap_fsample_io_desc,
ARRAY_SIZE(omap_fsample_io_desc));
/* Early, board-dependent init */
/*
* Hold GSM Reset until needed
*/
omap_writew(omap_readw(OMAP730_DSP_M_CTL) & ~1, OMAP730_DSP_M_CTL);
/*
* UARTs -> done automagically by 8250 driver
*/
/*
* CSx timings, GPIO Mux ... setup
*/
/* Flash: CS0 timings setup */
omap_writel(0x0000fff3, OMAP730_FLASH_CFG_0);
omap_writel(0x00000088, OMAP730_FLASH_ACFG_0);
/*
* Ethernet support through the debug board
* CS1 timings setup
*/
omap_writel(0x0000fff3, OMAP730_FLASH_CFG_1);
omap_writel(0x00000000, OMAP730_FLASH_ACFG_1);
/*
* Configure MPU_EXT_NIRQ IO in IO_CONF9 register,
* It is used as the Ethernet controller interrupt
*/
omap_writel(omap_readl(OMAP730_IO_CONF_9) & 0x1FFFFFFF, OMAP730_IO_CONF_9);
}
MACHINE_START(OMAP_FSAMPLE, "OMAP730 F-Sample")
/* Maintainer: Brian Swetland <swetland@google.com> */
.phys_io = 0xfff00000,
.io_pg_offst = ((0xfef00000) >> 18) & 0xfffc,
.boot_params = 0x10000100,
.map_io = omap_fsample_map_io,
.init_irq = omap_fsample_init_irq,
.init_machine = omap_fsample_init,
.timer = &omap_timer,
MACHINE_END

75
arch/arm/mach-omap1/board-innovator.c
View File

@ -37,6 +37,8 @@
#include <asm/arch/usb.h> #include <asm/arch/usb.h>
#include <asm/arch/keypad.h> #include <asm/arch/keypad.h>
#include <asm/arch/common.h> #include <asm/arch/common.h>
#include <asm/arch/mcbsp.h>
#include <asm/arch/omap-alsa.h>
static int innovator_keymap[] = { static int innovator_keymap[] = {
KEY(0, 0, KEY_F1), KEY(0, 0, KEY_F1),
@ -112,6 +114,42 @@ static struct platform_device innovator_flash_device = {
.resource = &innovator_flash_resource, .resource = &innovator_flash_resource,
}; };
#define DEFAULT_BITPERSAMPLE 16
static struct omap_mcbsp_reg_cfg mcbsp_regs = {
.spcr2 = FREE | FRST | GRST | XRST | XINTM(3),
.spcr1 = RINTM(3) | RRST,
.rcr2 = RPHASE | RFRLEN2(OMAP_MCBSP_WORD_8) |
RWDLEN2(OMAP_MCBSP_WORD_16) | RDATDLY(0),
.rcr1 = RFRLEN1(OMAP_MCBSP_WORD_8) | RWDLEN1(OMAP_MCBSP_WORD_16),
.xcr2 = XPHASE | XFRLEN2(OMAP_MCBSP_WORD_8) |
XWDLEN2(OMAP_MCBSP_WORD_16) | XDATDLY(0) | XFIG,
.xcr1 = XFRLEN1(OMAP_MCBSP_WORD_8) | XWDLEN1(OMAP_MCBSP_WORD_16),
.srgr1 = FWID(DEFAULT_BITPERSAMPLE - 1),
.srgr2 = GSYNC | CLKSP | FSGM | FPER(DEFAULT_BITPERSAMPLE * 2 - 1),
/*.pcr0 = FSXM | FSRM | CLKXM | CLKRM | CLKXP | CLKRP,*/ /* mcbsp: master */
.pcr0 = CLKXP | CLKRP, /* mcbsp: slave */
};
static struct omap_alsa_codec_config alsa_config = {
.name = "OMAP Innovator AIC23",
.mcbsp_regs_alsa = &mcbsp_regs,
.codec_configure_dev = NULL, // aic23_configure,
.codec_set_samplerate = NULL, // aic23_set_samplerate,
.codec_clock_setup = NULL, // aic23_clock_setup,
.codec_clock_on = NULL, // aic23_clock_on,
.codec_clock_off = NULL, // aic23_clock_off,
.get_default_samplerate = NULL, // aic23_get_default_samplerate,
};
static struct platform_device innovator_mcbsp1_device = {
.name = "omap_alsa_mcbsp",
.id = 1,
.dev = {
.platform_data = &alsa_config,
},
};
static struct resource innovator_kp_resources[] = { static struct resource innovator_kp_resources[] = {
[0] = { [0] = {
.start = INT_KEYBOARD, .start = INT_KEYBOARD,
@ -139,6 +177,10 @@ static struct platform_device innovator_kp_device = {
#ifdef CONFIG_ARCH_OMAP15XX #ifdef CONFIG_ARCH_OMAP15XX
#include <linux/spi/spi.h>
#include <linux/spi/ads7846.h>
/* Only FPGA needs to be mapped here. All others are done with ioremap */ /* Only FPGA needs to be mapped here. All others are done with ioremap */
static struct map_desc innovator1510_io_desc[] __initdata = { static struct map_desc innovator1510_io_desc[] __initdata = {
{ {
@ -174,13 +216,44 @@ static struct platform_device innovator1510_lcd_device = {
.id = -1, .id = -1,
}; };
static struct platform_device innovator1510_spi_device = {
.name = "spi_inn1510",
.id = -1,
};
static struct platform_device *innovator1510_devices[] __initdata = { static struct platform_device *innovator1510_devices[] __initdata = {
&innovator_flash_device, &innovator_flash_device,
&innovator1510_smc91x_device, &innovator1510_smc91x_device,
&innovator_mcbsp1_device,
&innovator_kp_device, &innovator_kp_device,
&innovator1510_lcd_device, &innovator1510_lcd_device,
&innovator1510_spi_device,
}; };
static int innovator_get_pendown_state(void)
{
return !(fpga_read(OMAP1510_FPGA_TOUCHSCREEN) & (1 << 5));
}
static const struct ads7846_platform_data innovator1510_ts_info = {
.model = 7846,
.vref_delay_usecs = 100, /* internal, no capacitor */
.x_plate_ohms = 419,
.y_plate_ohms = 486,
.get_pendown_state = innovator_get_pendown_state,
};
static struct spi_board_info __initdata innovator1510_boardinfo[] = { {
/* FPGA (bus "10") CS0 has an ads7846e */
.modalias = "ads7846",
.platform_data = &innovator1510_ts_info,
.irq = OMAP1510_INT_FPGA_TS,
.max_speed_hz = 120000 /* max sample rate at 3V */
* 26 /* command + data + overhead */,
.bus_num = 10,
.chip_select = 0,
} };
#endif /* CONFIG_ARCH_OMAP15XX */ #endif /* CONFIG_ARCH_OMAP15XX */
#ifdef CONFIG_ARCH_OMAP16XX #ifdef CONFIG_ARCH_OMAP16XX
@ -311,6 +384,8 @@ static void __init innovator_init(void)
#ifdef CONFIG_ARCH_OMAP15XX #ifdef CONFIG_ARCH_OMAP15XX
if (cpu_is_omap1510()) { if (cpu_is_omap1510()) {
platform_add_devices(innovator1510_devices, ARRAY_SIZE(innovator1510_devices)); platform_add_devices(innovator1510_devices, ARRAY_SIZE(innovator1510_devices));
spi_register_board_info(innovator1510_boardinfo,
ARRAY_SIZE(innovator1510_boardinfo));
} }
#endif #endif
#ifdef CONFIG_ARCH_OMAP16XX #ifdef CONFIG_ARCH_OMAP16XX

147
arch/arm/mach-omap1/board-osk.c
View File

@ -33,7 +33,6 @@
#include <linux/mtd/mtd.h> #include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h> #include <linux/mtd/partitions.h>
#include <linux/input.h>
#include <asm/hardware.h> #include <asm/hardware.h>
#include <asm/mach-types.h> #include <asm/mach-types.h>
@ -45,25 +44,10 @@
#include <asm/arch/usb.h> #include <asm/arch/usb.h>
#include <asm/arch/mux.h> #include <asm/arch/mux.h>
#include <asm/arch/tc.h> #include <asm/arch/tc.h>
#include <asm/arch/keypad.h>
#include <asm/arch/common.h> #include <asm/arch/common.h>
#include <asm/arch/mcbsp.h> #include <asm/arch/mcbsp.h>
#include <asm/arch/omap-alsa.h> #include <asm/arch/omap-alsa.h>
static int osk_keymap[] = {
KEY(0, 0, KEY_F1),
KEY(0, 3, KEY_UP),
KEY(1, 1, KEY_LEFTCTRL),
KEY(1, 2, KEY_LEFT),
KEY(2, 0, KEY_SPACE),
KEY(2, 1, KEY_ESC),
KEY(2, 2, KEY_DOWN),
KEY(3, 2, KEY_ENTER),
KEY(3, 3, KEY_RIGHT),
0
};
static struct mtd_partition osk_partitions[] = { static struct mtd_partition osk_partitions[] = {
/* bootloader (U-Boot, etc) in first sector */ /* bootloader (U-Boot, etc) in first sector */
{ {
@ -181,48 +165,17 @@ static struct omap_alsa_codec_config alsa_config = {
static struct platform_device osk5912_mcbsp1_device = { static struct platform_device osk5912_mcbsp1_device = {
.name = "omap_alsa_mcbsp", .name = "omap_alsa_mcbsp",
.id = 1, .id = 1,
.dev = { .dev = {
.platform_data = &alsa_config, .platform_data = &alsa_config,
}, },
}; };
static struct resource osk5912_kp_resources[] = {
[0] = {
.start = INT_KEYBOARD,
.end = INT_KEYBOARD,
.flags = IORESOURCE_IRQ,
},
};
static struct omap_kp_platform_data osk_kp_data = {
.rows = 8,
.cols = 8,
.keymap = osk_keymap,
};
static struct platform_device osk5912_kp_device = {
.name = "omap-keypad",
.id = -1,
.dev = {
.platform_data = &osk_kp_data,
},
.num_resources = ARRAY_SIZE(osk5912_kp_resources),
.resource = osk5912_kp_resources,
};
static struct platform_device osk5912_lcd_device = {
.name = "lcd_osk",
.id = -1,
};
static struct platform_device *osk5912_devices[] __initdata = { static struct platform_device *osk5912_devices[] __initdata = {
&osk5912_flash_device, &osk5912_flash_device,
&osk5912_smc91x_device, &osk5912_smc91x_device,
&osk5912_cf_device, &osk5912_cf_device,
&osk5912_mcbsp1_device, &osk5912_mcbsp1_device,
&osk5912_kp_device,
&osk5912_lcd_device,
}; };
static void __init osk_init_smc91x(void) static void __init osk_init_smc91x(void)
@ -276,18 +229,100 @@ static struct omap_uart_config osk_uart_config __initdata = {
.enabled_uarts = (1 << 0), .enabled_uarts = (1 << 0),
}; };
#ifdef CONFIG_OMAP_OSK_MISTRAL
static struct omap_lcd_config osk_lcd_config __initdata = { static struct omap_lcd_config osk_lcd_config __initdata = {
.ctrl_name = "internal", .ctrl_name = "internal",
}; };
#endif
static struct omap_board_config_kernel osk_config[] = { static struct omap_board_config_kernel osk_config[] = {
{ OMAP_TAG_USB, &osk_usb_config }, { OMAP_TAG_USB, &osk_usb_config },
{ OMAP_TAG_UART, &osk_uart_config }, { OMAP_TAG_UART, &osk_uart_config },
#ifdef CONFIG_OMAP_OSK_MISTRAL
{ OMAP_TAG_LCD, &osk_lcd_config }, { OMAP_TAG_LCD, &osk_lcd_config },
#endif
}; };
#ifdef CONFIG_OMAP_OSK_MISTRAL #ifdef CONFIG_OMAP_OSK_MISTRAL
#include <linux/input.h>
#include <linux/spi/spi.h>
#include <linux/spi/ads7846.h>
#include <asm/arch/keypad.h>
static const int osk_keymap[] = {
/* KEY(col, row, code) */
KEY(0, 0, KEY_F1), /* SW4 */
KEY(0, 3, KEY_UP), /* (sw2/up) */
KEY(1, 1, KEY_LEFTCTRL), /* SW5 */
KEY(1, 2, KEY_LEFT), /* (sw2/left) */
KEY(2, 0, KEY_SPACE), /* SW3 */
KEY(2, 1, KEY_ESC), /* SW6 */
KEY(2, 2, KEY_DOWN), /* (sw2/down) */
KEY(3, 2, KEY_ENTER), /* (sw2/select) */
KEY(3, 3, KEY_RIGHT), /* (sw2/right) */
0
};
static struct omap_kp_platform_data osk_kp_data = {
.rows = 8,
.cols = 8,
.keymap = (int *) osk_keymap,
};
static struct resource osk5912_kp_resources[] = {
[0] = {
.start = INT_KEYBOARD,
.end = INT_KEYBOARD,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device osk5912_kp_device = {
.name = "omap-keypad",
.id = -1,
.dev = {
.platform_data = &osk_kp_data,
},
.num_resources = ARRAY_SIZE(osk5912_kp_resources),
.resource = osk5912_kp_resources,
};
static struct platform_device osk5912_lcd_device = {
.name = "lcd_osk",
.id = -1,
};
static struct platform_device *mistral_devices[] __initdata = {
&osk5912_kp_device,
&osk5912_lcd_device,
};
static int mistral_get_pendown_state(void)
{
return !omap_get_gpio_datain(4);
}
static const struct ads7846_platform_data mistral_ts_info = {
.model = 7846,
.vref_delay_usecs = 100, /* internal, no capacitor */
.x_plate_ohms = 419,
.y_plate_ohms = 486,
.get_pendown_state = mistral_get_pendown_state,
};
static struct spi_board_info __initdata mistral_boardinfo[] = { {
/* MicroWire (bus 2) CS0 has an ads7846e */
.modalias = "ads7846",
.platform_data = &mistral_ts_info,
.irq = OMAP_GPIO_IRQ(4),
.max_speed_hz = 120000 /* max sample rate at 3V */
* 26 /* command + data + overhead */,
.bus_num = 2,
.chip_select = 0,
} };
#ifdef CONFIG_PM #ifdef CONFIG_PM
static irqreturn_t static irqreturn_t
osk_mistral_wake_interrupt(int irq, void *ignored, struct pt_regs *regs) osk_mistral_wake_interrupt(int irq, void *ignored, struct pt_regs *regs)
@ -298,14 +333,18 @@ osk_mistral_wake_interrupt(int irq, void *ignored, struct pt_regs *regs)
static void __init osk_mistral_init(void) static void __init osk_mistral_init(void)
{ {
/* FIXME here's where to feed in framebuffer, touchpad, and /* NOTE: we could actually tell if there's a Mistral board
* keyboard setup ... not in the drivers for those devices!
*
* NOTE: we could actually tell if there's a Mistral board
* attached, e.g. by trying to read something from the ads7846. * attached, e.g. by trying to read something from the ads7846.
* But this is too early for that... * But this arch_init() code is too early for that, since we
* can't talk to the ads or even the i2c eeprom.
*/ */
// omap_cfg_reg(P19_1610_GPIO6); // BUSY
omap_cfg_reg(P20_1610_GPIO4); // PENIRQ
set_irq_type(OMAP_GPIO_IRQ(4), IRQT_FALLING);
spi_register_board_info(mistral_boardinfo,
ARRAY_SIZE(mistral_boardinfo));
/* the sideways button (SW1) is for use as a "wakeup" button */ /* the sideways button (SW1) is for use as a "wakeup" button */
omap_cfg_reg(N15_1610_MPUIO2); omap_cfg_reg(N15_1610_MPUIO2);
if (omap_request_gpio(OMAP_MPUIO(2)) == 0) { if (omap_request_gpio(OMAP_MPUIO(2)) == 0) {
@ -329,6 +368,8 @@ static void __init osk_mistral_init(void)
#endif #endif
} else } else
printk(KERN_ERR "OSK+Mistral: wakeup button is awol\n"); printk(KERN_ERR "OSK+Mistral: wakeup button is awol\n");
platform_add_devices(mistral_devices, ARRAY_SIZE(mistral_devices));
} }
#else #else
static void __init osk_mistral_init(void) { } static void __init osk_mistral_init(void) { }

18
arch/arm/mach-omap1/clock.c
View File

@ -1,3 +1,4 @@
//kernel/linux-omap-fsample/arch/arm/mach-omap1/clock.c#2 - edit change 3808 (text)
/* /*
* linux/arch/arm/mach-omap1/clock.c * linux/arch/arm/mach-omap1/clock.c
* *
@ -20,6 +21,7 @@
#include <asm/io.h> #include <asm/io.h>
#include <asm/arch/cpu.h>
#include <asm/arch/usb.h> #include <asm/arch/usb.h>
#include <asm/arch/clock.h> #include <asm/arch/clock.h>
#include <asm/arch/sram.h> #include <asm/arch/sram.h>
@ -270,8 +272,12 @@ static int omap1_select_table_rate(struct clk * clk, unsigned long rate)
/* /*
* In most cases we should not need to reprogram DPLL. * In most cases we should not need to reprogram DPLL.
* Reprogramming the DPLL is tricky, it must be done from SRAM. * Reprogramming the DPLL is tricky, it must be done from SRAM.
* (on 730, bit 13 must always be 1)
*/ */
omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val); if (cpu_is_omap730())
omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val | 0x2000);
else
omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val);
ck_dpll1.rate = ptr->pll_rate; ck_dpll1.rate = ptr->pll_rate;
propagate_rate(&ck_dpll1); propagate_rate(&ck_dpll1);
@ -748,7 +754,7 @@ int __init omap1_clk_init(void)
printk(KERN_ERR "System frequencies not set. Check your config.\n"); printk(KERN_ERR "System frequencies not set. Check your config.\n");
/* Guess sane values (60MHz) */ /* Guess sane values (60MHz) */
omap_writew(0x2290, DPLL_CTL); omap_writew(0x2290, DPLL_CTL);
omap_writew(0x1005, ARM_CKCTL); omap_writew(cpu_is_omap730() ? 0x3005 : 0x1005, ARM_CKCTL);
ck_dpll1.rate = 60000000; ck_dpll1.rate = 60000000;
propagate_rate(&ck_dpll1); propagate_rate(&ck_dpll1);
} }
@ -761,13 +767,17 @@ int __init omap1_clk_init(void)
ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10, ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10,
arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10); arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10);
#ifdef CONFIG_MACH_OMAP_PERSEUS2 #if defined(CONFIG_MACH_OMAP_PERSEUS2) || defined(CONFIG_MACH_OMAP_FSAMPLE)
/* Select slicer output as OMAP input clock */ /* Select slicer output as OMAP input clock */
omap_writew(omap_readw(OMAP730_PCC_UPLD_CTRL) & ~0x1, OMAP730_PCC_UPLD_CTRL); omap_writew(omap_readw(OMAP730_PCC_UPLD_CTRL) & ~0x1, OMAP730_PCC_UPLD_CTRL);
#endif #endif
/* Turn off DSP and ARM_TIMXO. Make sure ARM_INTHCK is not divided */ /* Turn off DSP and ARM_TIMXO. Make sure ARM_INTHCK is not divided */
omap_writew(omap_readw(ARM_CKCTL) & 0x0fff, ARM_CKCTL); /* (on 730, bit 13 must not be cleared) */
if (cpu_is_omap730())
omap_writew(omap_readw(ARM_CKCTL) & 0x2fff, ARM_CKCTL);
else
omap_writew(omap_readw(ARM_CKCTL) & 0x0fff, ARM_CKCTL);
/* Put DSP/MPUI into reset until needed */ /* Put DSP/MPUI into reset until needed */
omap_writew(0, ARM_RSTCT1); omap_writew(0, ARM_RSTCT1);

7
arch/arm/mach-omap1/pm.c
View File

@ -1,3 +1,4 @@
//kernel/linux-omap-fsample/arch/arm/mach-omap1/pm.c#3 - integrate change 4545 (text)
/* /*
* linux/arch/arm/mach-omap1/pm.c * linux/arch/arm/mach-omap1/pm.c
* *
@ -50,6 +51,7 @@
#include <asm/mach/irq.h> #include <asm/mach/irq.h>
#include <asm/mach-types.h> #include <asm/mach-types.h>
#include <asm/arch/cpu.h>
#include <asm/arch/irqs.h> #include <asm/arch/irqs.h>
#include <asm/arch/clock.h> #include <asm/arch/clock.h>
#include <asm/arch/sram.h> #include <asm/arch/sram.h>
@ -326,8 +328,9 @@ void omap_pm_suspend(void)
/* stop DSP */ /* stop DSP */
omap_writew(omap_readw(ARM_RSTCT1) & ~(1 << DSP_EN), ARM_RSTCT1); omap_writew(omap_readw(ARM_RSTCT1) & ~(1 << DSP_EN), ARM_RSTCT1);
/* shut down dsp_ck */ /* shut down dsp_ck */
omap_writew(omap_readw(ARM_CKCTL) & ~(1 << EN_DSPCK), ARM_CKCTL); if (!cpu_is_omap730())
omap_writew(omap_readw(ARM_CKCTL) & ~(1 << EN_DSPCK), ARM_CKCTL);
/* temporarily enabling api_ck to access DSP registers */ /* temporarily enabling api_ck to access DSP registers */
omap_writew(omap_readw(ARM_IDLECT2) | 1 << EN_APICK, ARM_IDLECT2); omap_writew(omap_readw(ARM_IDLECT2) | 1 << EN_APICK, ARM_IDLECT2);

2
arch/arm/mach-omap1/time.c
View File

@ -93,7 +93,7 @@ static inline unsigned long long cycles_2_ns(unsigned long long cyc)
* will break. On P2, the timer count rate is 6.5 MHz after programming PTV * will break. On P2, the timer count rate is 6.5 MHz after programming PTV
* with 0. This divides the 13MHz input by 2, and is undocumented. * with 0. This divides the 13MHz input by 2, and is undocumented.
*/ */
#ifdef CONFIG_MACH_OMAP_PERSEUS2 #if defined(CONFIG_MACH_OMAP_PERSEUS2) || defined(CONFIG_MACH_OMAP_FSAMPLE)
/* REVISIT: This ifdef construct should be replaced by a query to clock /* REVISIT: This ifdef construct should be replaced by a query to clock
* framework to see if timer base frequency is 12.0, 13.0 or 19.2 MHz. * framework to see if timer base frequency is 12.0, 13.0 or 19.2 MHz.
*/ */

1
arch/arm/mach-omap2/Kconfig
View File

@ -8,6 +8,7 @@ config ARCH_OMAP24XX
config ARCH_OMAP2420 config ARCH_OMAP2420
bool "OMAP2420 support" bool "OMAP2420 support"
depends on ARCH_OMAP24XX depends on ARCH_OMAP24XX
select OMAP_DM_TIMER
comment "OMAP Board Type" comment "OMAP Board Type"
depends on ARCH_OMAP2 depends on ARCH_OMAP2

5
arch/arm/mach-omap2/Makefile
View File

@ -3,12 +3,13 @@
# #
# Common support # Common support
obj-y := irq.o id.o io.o sram-fn.o memory.o prcm.o clock.o mux.o devices.o serial.o obj-y := irq.o id.o io.o sram-fn.o memory.o prcm.o clock.o mux.o devices.o \
serial.o gpmc.o
obj-$(CONFIG_OMAP_MPU_TIMER) += timer-gp.o obj-$(CONFIG_OMAP_MPU_TIMER) += timer-gp.o
# Power Management # Power Management
obj-$(CONFIG_PM) += pm.o sleep.o obj-$(CONFIG_PM) += pm.o pm-domain.o sleep.o
# Specific board support # Specific board support
obj-$(CONFIG_MACH_OMAP_GENERIC) += board-generic.o obj-$(CONFIG_MACH_OMAP_GENERIC) += board-generic.o

37
arch/arm/mach-omap2/clock.c
View File

@ -659,26 +659,35 @@ static int omap2_clk_set_rate(struct clk *clk, unsigned long rate)
/* Isolate control register */ /* Isolate control register */
div_sel = (SRC_RATE_SEL_MASK & clk->flags); div_sel = (SRC_RATE_SEL_MASK & clk->flags);
div_off = clk->src_offset; div_off = clk->rate_offset;
validrate = omap2_clksel_round_rate(clk, rate, &new_div); validrate = omap2_clksel_round_rate(clk, rate, &new_div);
if(validrate != rate) if (validrate != rate)
return(ret); return(ret);
field_val = omap2_get_clksel(&div_sel, &field_mask, clk); field_val = omap2_get_clksel(&div_sel, &field_mask, clk);
if (div_sel == 0) if (div_sel == 0)
return ret; return ret;
if(clk->flags & CM_SYSCLKOUT_SEL1){ if (clk->flags & CM_SYSCLKOUT_SEL1) {
switch(new_div){ switch (new_div) {
case 16: field_val = 4; break; case 16:
case 8: field_val = 3; break; field_val = 4;
case 4: field_val = 2; break; break;
case 2: field_val = 1; break; case 8:
case 1: field_val = 0; break; field_val = 3;
break;
case 4:
field_val = 2;
break;
case 2:
field_val = 1;
break;
case 1:
field_val = 0;
break;
} }
} } else
else
field_val = new_div; field_val = new_div;
reg = (void __iomem *)div_sel; reg = (void __iomem *)div_sel;
@ -743,7 +752,7 @@ static u32 omap2_get_src_field(u32 *type_to_addr, u32 reg_offset,
val = 0x2; val = 0x2;
break; break;
case CM_WKUP_SEL1: case CM_WKUP_SEL1:
src_reg_addr = (u32)&CM_CLKSEL2_CORE; src_reg_addr = (u32)&CM_CLKSEL_WKUP;
mask = 0x3; mask = 0x3;
if (src_clk == &func_32k_ck) if (src_clk == &func_32k_ck)
val = 0x0; val = 0x0;
@ -783,9 +792,9 @@ static u32 omap2_get_src_field(u32 *type_to_addr, u32 reg_offset,
val = 0; val = 0;
if (src_clk == &sys_ck) if (src_clk == &sys_ck)
val = 1; val = 1;
if (src_clk == &func_54m_ck)
val = 2;
if (src_clk == &func_96m_ck) if (src_clk == &func_96m_ck)
val = 2;
if (src_clk == &func_54m_ck)
val = 3; val = 3;
break; break;
} }

2
arch/arm/mach-omap2/clock.h
View File

@ -1062,7 +1062,7 @@ static struct clk gpt2_ick = {
.parent = &l4_ck, .parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, /* Bit4 */ .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, /* Bit4 */
.enable_bit = 0, .enable_bit = 4,
.recalc = &omap2_followparent_recalc, .recalc = &omap2_followparent_recalc,
}; };

46
arch/arm/mach-omap2/devices.c
View File

@ -104,6 +104,51 @@ static inline void omap_init_sti(void)
static inline void omap_init_sti(void) {} static inline void omap_init_sti(void) {}
#endif #endif
#if defined(CONFIG_SPI_OMAP24XX)
#include <asm/arch/mcspi.h>
#define OMAP2_MCSPI1_BASE 0x48098000
#define OMAP2_MCSPI2_BASE 0x4809a000
/* FIXME: use resources instead */
static struct omap2_mcspi_platform_config omap2_mcspi1_config = {
.base = io_p2v(OMAP2_MCSPI1_BASE),
.num_cs = 4,
};
struct platform_device omap2_mcspi1 = {
.name = "omap2_mcspi",
.id = 1,
.dev = {
.platform_data = &omap2_mcspi1_config,
},
};
static struct omap2_mcspi_platform_config omap2_mcspi2_config = {
.base = io_p2v(OMAP2_MCSPI2_BASE),
.num_cs = 2,
};
struct platform_device omap2_mcspi2 = {
.name = "omap2_mcspi",
.id = 2,
.dev = {
.platform_data = &omap2_mcspi2_config,
},
};
static void omap_init_mcspi(void)
{
platform_device_register(&omap2_mcspi1);
platform_device_register(&omap2_mcspi2);
}
#else
static inline void omap_init_mcspi(void) {}
#endif
/*-------------------------------------------------------------------------*/ /*-------------------------------------------------------------------------*/
static int __init omap2_init_devices(void) static int __init omap2_init_devices(void)
@ -112,6 +157,7 @@ static int __init omap2_init_devices(void)
* in alphabetical order so they're easier to sort through. * in alphabetical order so they're easier to sort through.
*/ */
omap_init_i2c(); omap_init_i2c();
omap_init_mcspi();
omap_init_sti(); omap_init_sti();
return 0; return 0;

209
arch/arm/mach-omap2/gpmc.c Normal file
View File

@ -0,0 +1,209 @@
/*
* GPMC support functions
*
* Copyright (C) 2005-2006 Nokia Corporation
*
* Author: Juha Yrjola
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <asm/io.h>
#include <asm/arch/gpmc.h>
#undef DEBUG
#define GPMC_BASE 0x6800a000
#define GPMC_REVISION 0x00
#define GPMC_SYSCONFIG 0x10
#define GPMC_SYSSTATUS 0x14
#define GPMC_IRQSTATUS 0x18
#define GPMC_IRQENABLE 0x1c
#define GPMC_TIMEOUT_CONTROL 0x40
#define GPMC_ERR_ADDRESS 0x44
#define GPMC_ERR_TYPE 0x48
#define GPMC_CONFIG 0x50
#define GPMC_STATUS 0x54
#define GPMC_PREFETCH_CONFIG1 0x1e0
#define GPMC_PREFETCH_CONFIG2 0x1e4
#define GPMC_PREFETCH_CONTROL 0x1e8
#define GPMC_PREFETCH_STATUS 0x1f0
#define GPMC_ECC_CONFIG 0x1f4
#define GPMC_ECC_CONTROL 0x1f8
#define GPMC_ECC_SIZE_CONFIG 0x1fc
#define GPMC_CS0 0x60
#define GPMC_CS_SIZE 0x30
static void __iomem *gpmc_base =
(void __iomem *) IO_ADDRESS(GPMC_BASE);
static void __iomem *gpmc_cs_base =
(void __iomem *) IO_ADDRESS(GPMC_BASE) + GPMC_CS0;
static struct clk *gpmc_l3_clk;
static void gpmc_write_reg(int idx, u32 val)
{
__raw_writel(val, gpmc_base + idx);
}
static u32 gpmc_read_reg(int idx)
{
return __raw_readl(gpmc_base + idx);
}
void gpmc_cs_write_reg(int cs, int idx, u32 val)
{
void __iomem *reg_addr;
reg_addr = gpmc_cs_base + (cs * GPMC_CS_SIZE) + idx;
__raw_writel(val, reg_addr);
}
u32 gpmc_cs_read_reg(int cs, int idx)
{
return __raw_readl(gpmc_cs_base + (cs * GPMC_CS_SIZE) + idx);
}
/* TODO: Add support for gpmc_fck to clock framework and use it */
static unsigned long gpmc_get_fclk_period(void)
{
/* In picoseconds */
return 1000000000 / ((clk_get_rate(gpmc_l3_clk)) / 1000);
}
unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
{
unsigned long tick_ps;
/* Calculate in picosecs to yield more exact results */
tick_ps = gpmc_get_fclk_period();
return (time_ns * 1000 + tick_ps - 1) / tick_ps;
}
#ifdef DEBUG
static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
int time, const char *name)
#else
static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
int time)
#endif
{
u32 l;
int ticks, mask, nr_bits;
if (time == 0)
ticks = 0;
else
ticks = gpmc_ns_to_ticks(time);
nr_bits = end_bit - st_bit + 1;
if (ticks >= 1 << nr_bits)
return -1;
mask = (1 << nr_bits) - 1;
l = gpmc_cs_read_reg(cs, reg);
#ifdef DEBUG
printk(KERN_INFO "GPMC CS%d: %-10s: %d ticks, %3lu ns (was %i ticks)\n",
cs, name, ticks, gpmc_get_fclk_period() * ticks / 1000,
(l >> st_bit) & mask);
#endif
l &= ~(mask << st_bit);
l |= ticks << st_bit;
gpmc_cs_write_reg(cs, reg, l);
return 0;
}
#ifdef DEBUG
#define GPMC_SET_ONE(reg, st, end, field) \
if (set_gpmc_timing_reg(cs, (reg), (st), (end), \
t->field, #field) < 0) \
return -1
#else
#define GPMC_SET_ONE(reg, st, end, field) \
if (set_gpmc_timing_reg(cs, (reg), (st), (end), t->field) < 0) \
return -1
#endif
int gpmc_cs_calc_divider(int cs, unsigned int sync_clk)
{
int div;
u32 l;
l = sync_clk * 1000 + (gpmc_get_fclk_period() - 1);
div = l / gpmc_get_fclk_period();
if (div > 4)
return -1;
if (div < 0)
div = 1;
return div;
}
int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t)
{
int div;
u32 l;
div = gpmc_cs_calc_divider(cs, t->sync_clk);
if (div < 0)
return -1;
GPMC_SET_ONE(GPMC_CS_CONFIG2, 0, 3, cs_on);
GPMC_SET_ONE(GPMC_CS_CONFIG2, 8, 12, cs_rd_off);
GPMC_SET_ONE(GPMC_CS_CONFIG2, 16, 20, cs_wr_off);
GPMC_SET_ONE(GPMC_CS_CONFIG3, 0, 3, adv_on);
GPMC_SET_ONE(GPMC_CS_CONFIG3, 8, 12, adv_rd_off);
GPMC_SET_ONE(GPMC_CS_CONFIG3, 16, 20, adv_wr_off);
GPMC_SET_ONE(GPMC_CS_CONFIG4, 0, 3, oe_on);
GPMC_SET_ONE(GPMC_CS_CONFIG4, 8, 12, oe_off);
GPMC_SET_ONE(GPMC_CS_CONFIG4, 16, 19, we_on);
GPMC_SET_ONE(GPMC_CS_CONFIG4, 24, 28, we_off);
GPMC_SET_ONE(GPMC_CS_CONFIG5, 0, 4, rd_cycle);
GPMC_SET_ONE(GPMC_CS_CONFIG5, 8, 12, wr_cycle);
GPMC_SET_ONE(GPMC_CS_CONFIG5, 16, 20, access);
GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access);
#ifdef DEBUG
printk(KERN_INFO "GPMC CS%d CLK period is %lu (div %d)\n",
cs, gpmc_get_fclk_period(), div);
#endif
l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
l &= ~0x03;
l |= (div - 1);
return 0;
}
unsigned long gpmc_cs_get_base_addr(int cs)
{
return (gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7) & 0x1f) << 24;
}
void __init gpmc_init(void)
{
u32 l;
gpmc_l3_clk = clk_get(NULL, "core_l3_ck");
BUG_ON(IS_ERR(gpmc_l3_clk));
l = gpmc_read_reg(GPMC_REVISION);
printk(KERN_INFO "GPMC revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
/* Set smart idle mode and automatic L3 clock gating */
l = gpmc_read_reg(GPMC_SYSCONFIG);
l &= 0x03 << 3;
l |= (0x02 << 3) | (1 << 0);
gpmc_write_reg(GPMC_SYSCONFIG, l);
}

2
arch/arm/mach-omap2/io.c
View File

@ -26,6 +26,7 @@
extern void omap_sram_init(void); extern void omap_sram_init(void);
extern int omap2_clk_init(void); extern int omap2_clk_init(void);
extern void omap2_check_revision(void); extern void omap2_check_revision(void);
extern void gpmc_init(void);
/* /*
* The machine specific code may provide the extra mapping besides the * The machine specific code may provide the extra mapping besides the
@ -66,4 +67,5 @@ void __init omap2_init_common_hw(void)
{ {
omap2_mux_init(); omap2_mux_init();
omap2_clk_init(); omap2_clk_init();
gpmc_init();
} }

38
arch/arm/mach-omap2/mux.c
View File

@ -52,6 +52,12 @@ MUX_CFG_24XX("W19_24XX_SYS_NIRQ", 0x12c, 0, 1, 1, 1)
/* 24xx clocks */ /* 24xx clocks */
MUX_CFG_24XX("W14_24XX_SYS_CLKOUT", 0x137, 0, 1, 1, 1) MUX_CFG_24XX("W14_24XX_SYS_CLKOUT", 0x137, 0, 1, 1, 1)
/* 24xx GPMC wait pin monitoring */
MUX_CFG_24XX("L3_GPMC_WAIT0", 0x09a, 0, 1, 1, 1)
MUX_CFG_24XX("N7_GPMC_WAIT1", 0x09b, 0, 1, 1, 1)
MUX_CFG_24XX("M1_GPMC_WAIT2", 0x09c, 0, 1, 1, 1)
MUX_CFG_24XX("P1_GPMC_WAIT3", 0x09d, 0, 1, 1, 1)
/* 24xx McBSP */ /* 24xx McBSP */
MUX_CFG_24XX("Y15_24XX_MCBSP2_CLKX", 0x124, 1, 1, 0, 1) MUX_CFG_24XX("Y15_24XX_MCBSP2_CLKX", 0x124, 1, 1, 0, 1)
MUX_CFG_24XX("R14_24XX_MCBSP2_FSX", 0x125, 1, 1, 0, 1) MUX_CFG_24XX("R14_24XX_MCBSP2_FSX", 0x125, 1, 1, 0, 1)
@ -59,18 +65,38 @@ MUX_CFG_24XX("W15_24XX_MCBSP2_DR", 0x126, 1, 1, 0, 1)
MUX_CFG_24XX("V15_24XX_MCBSP2_DX", 0x127, 1, 1, 0, 1) MUX_CFG_24XX("V15_24XX_MCBSP2_DX", 0x127, 1, 1, 0, 1)
/* 24xx GPIO */ /* 24xx GPIO */
MUX_CFG_24XX("M21_242X_GPIO11", 0x0c9, 3, 1, 1, 1) MUX_CFG_24XX("M21_242X_GPIO11", 0x0c9, 3, 1, 1, 1)
MUX_CFG_24XX("AA10_242X_GPIO13", 0x0e5, 3, 0, 0, 1) MUX_CFG_24XX("AA10_242X_GPIO13", 0x0e5, 3, 0, 0, 1)
MUX_CFG_24XX("AA6_242X_GPIO14", 0x0e6, 3, 0, 0, 1) MUX_CFG_24XX("AA6_242X_GPIO14", 0x0e6, 3, 0, 0, 1)
MUX_CFG_24XX("AA4_242X_GPIO15", 0x0e7, 3, 0, 0, 1) MUX_CFG_24XX("AA4_242X_GPIO15", 0x0e7, 3, 0, 0, 1)
MUX_CFG_24XX("Y11_242X_GPIO16", 0x0e8, 3, 0, 0, 1) MUX_CFG_24XX("Y11_242X_GPIO16", 0x0e8, 3, 0, 0, 1)
MUX_CFG_24XX("AA12_242X_GPIO17", 0x0e9, 3, 0, 0, 1) MUX_CFG_24XX("AA12_242X_GPIO17", 0x0e9, 3, 0, 0, 1)
MUX_CFG_24XX("AA8_242X_GPIO58", 0x0ea, 3, 0, 0, 1) MUX_CFG_24XX("AA8_242X_GPIO58", 0x0ea, 3, 0, 0, 1)
MUX_CFG_24XX("Y20_24XX_GPIO60", 0x12c, 3, 0, 0, 1) MUX_CFG_24XX("Y20_24XX_GPIO60", 0x12c, 3, 0, 0, 1)
MUX_CFG_24XX("W4__24XX_GPIO74", 0x0f2, 3, 0, 0, 1) MUX_CFG_24XX("W4__24XX_GPIO74", 0x0f2, 3, 0, 0, 1)
MUX_CFG_24XX("M15_24XX_GPIO92", 0x10a, 3, 0, 0, 1) MUX_CFG_24XX("M15_24XX_GPIO92", 0x10a, 3, 0, 0, 1)
MUX_CFG_24XX("V14_24XX_GPIO117", 0x128, 3, 1, 0, 1) MUX_CFG_24XX("V14_24XX_GPIO117", 0x128, 3, 1, 0, 1)
/* 242x DBG GPIO */
MUX_CFG_24XX("V4_242X_GPIO49", 0xd3, 3, 0, 0, 1)
MUX_CFG_24XX("W2_242X_GPIO50", 0xd4, 3, 0, 0, 1)
MUX_CFG_24XX("U4_242X_GPIO51", 0xd5, 3, 0, 0, 1)
MUX_CFG_24XX("V3_242X_GPIO52", 0xd6, 3, 0, 0, 1)
MUX_CFG_24XX("V2_242X_GPIO53", 0xd7, 3, 0, 0, 1)
MUX_CFG_24XX("V6_242X_GPIO53", 0xcf, 3, 0, 0, 1)
MUX_CFG_24XX("T4_242X_GPIO54", 0xd8, 3, 0, 0, 1)
MUX_CFG_24XX("Y4_242X_GPIO54", 0xd0, 3, 0, 0, 1)
MUX_CFG_24XX("T3_242X_GPIO55", 0xd9, 3, 0, 0, 1)
MUX_CFG_24XX("U2_242X_GPIO56", 0xda, 3, 0, 0, 1)
/* 24xx external DMA requests */
MUX_CFG_24XX("AA10_242X_DMAREQ0", 0x0e5, 2, 0, 0, 1)
MUX_CFG_24XX("AA6_242X_DMAREQ1", 0x0e6, 2, 0, 0, 1)
MUX_CFG_24XX("E4_242X_DMAREQ2", 0x074, 2, 0, 0, 1)
MUX_CFG_24XX("G4_242X_DMAREQ3", 0x073, 2, 0, 0, 1)
MUX_CFG_24XX("D3_242X_DMAREQ4", 0x072, 2, 0, 0, 1)
MUX_CFG_24XX("E3_242X_DMAREQ5", 0x071, 2, 0, 0, 1)
/* TSC IRQ */ /* TSC IRQ */
MUX_CFG_24XX("P20_24XX_TSC_IRQ", 0x108, 0, 0, 0, 1) MUX_CFG_24XX("P20_24XX_TSC_IRQ", 0x108, 0, 0, 0, 1)

300
arch/arm/mach-omap2/pm-domain.c Normal file
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@ -0,0 +1,300 @@
/*
* linux/arch/arm/mach-omap2/pm-domain.c
*
* Power domain functions for OMAP2
*
* Copyright (C) 2006 Nokia Corporation
* Tony Lindgren <tony@atomide.com>
*
* Some code based on earlier OMAP2 sample PM code
* Copyright (C) 2005 Texas Instruments, Inc.
* Richard Woodruff <r-woodruff2@ti.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/config.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/clk.h>
#include <asm/io.h>
#include "prcm-regs.h"
/* Power domain offsets */
#define PM_MPU_OFFSET 0x100
#define PM_CORE_OFFSET 0x200
#define PM_GFX_OFFSET 0x300
#define PM_WKUP_OFFSET 0x400 /* Autoidle only */
#define PM_PLL_OFFSET 0x500 /* Autoidle only */
#define PM_DSP_OFFSET 0x800
#define PM_MDM_OFFSET 0xc00
/* Power domain wake-up dependency control register */
#define PM_WKDEP_OFFSET 0xc8
#define EN_MDM (1 << 5)
#define EN_WKUP (1 << 4)
#define EN_GFX (1 << 3)
#define EN_DSP (1 << 2)
#define EN_MPU (1 << 1)
#define EN_CORE (1 << 0)
/* Core power domain state transition control register */
#define PM_PWSTCTRL_OFFSET 0xe0
#define FORCESTATE (1 << 18) /* Only for DSP & GFX */
#define MEM4RETSTATE (1 << 6)
#define MEM3RETSTATE (1 << 5)
#define MEM2RETSTATE (1 << 4)
#define MEM1RETSTATE (1 << 3)
#define LOGICRETSTATE (1 << 2) /* Logic is retained */
#define POWERSTATE_OFF 0x3
#define POWERSTATE_RETENTION 0x1
#define POWERSTATE_ON 0x0
/* Power domain state register */
#define PM_PWSTST_OFFSET 0xe4
/* Hardware supervised state transition control register */
#define CM_CLKSTCTRL_OFFSET 0x48
#define AUTOSTAT_MPU (1 << 0) /* MPU */
#define AUTOSTAT_DSS (1 << 2) /* Core */
#define AUTOSTAT_L4 (1 << 1) /* Core */
#define AUTOSTAT_L3 (1 << 0) /* Core */
#define AUTOSTAT_GFX (1 << 0) /* GFX */
#define AUTOSTAT_IVA (1 << 8) /* 2420 IVA in DSP domain */
#define AUTOSTAT_DSP (1 << 0) /* DSP */
#define AUTOSTAT_MDM (1 << 0) /* MDM */
/* Automatic control of interface clock idling */
#define CM_AUTOIDLE1_OFFSET 0x30
#define CM_AUTOIDLE2_OFFSET 0x34 /* Core only */
#define CM_AUTOIDLE3_OFFSET 0x38 /* Core only */
#define CM_AUTOIDLE4_OFFSET 0x3c /* Core only */
#define AUTO_54M(x) (((x) & 0x3) << 6)
#define AUTO_96M(x) (((x) & 0x3) << 2)
#define AUTO_DPLL(x) (((x) & 0x3) << 0)
#define AUTO_STOPPED 0x3
#define AUTO_BYPASS_FAST 0x2 /* DPLL only */
#define AUTO_BYPASS_LOW_POWER 0x1 /* DPLL only */
#define AUTO_DISABLED 0x0
/* Voltage control PRCM_VOLTCTRL bits */
#define AUTO_EXTVOLT (1 << 15)
#define FORCE_EXTVOLT (1 << 14)
#define SETOFF_LEVEL(x) (((x) & 0x3) << 12)
#define MEMRETCTRL (1 << 8)
#define SETRET_LEVEL(x) (((x) & 0x3) << 6)
#define VOLT_LEVEL(x) (((x) & 0x3) << 0)
#define OMAP24XX_PRCM_VBASE IO_ADDRESS(OMAP24XX_PRCM_BASE)
#define prcm_readl(r) __raw_readl(OMAP24XX_PRCM_VBASE + (r))
#define prcm_writel(v, r) __raw_writel((v), OMAP24XX_PRCM_VBASE + (r))
static u32 pmdomain_get_wakeup_dependencies(int domain_offset)
{
return prcm_readl(domain_offset + PM_WKDEP_OFFSET);
}
static void pmdomain_set_wakeup_dependencies(u32 state, int domain_offset)
{
prcm_writel(state, domain_offset + PM_WKDEP_OFFSET);
}
static u32 pmdomain_get_powerstate(int domain_offset)
{
return prcm_readl(domain_offset + PM_PWSTCTRL_OFFSET);
}
static void pmdomain_set_powerstate(u32 state, int domain_offset)
{
prcm_writel(state, domain_offset + PM_PWSTCTRL_OFFSET);
}
static u32 pmdomain_get_clock_autocontrol(int domain_offset)
{
return prcm_readl(domain_offset + CM_CLKSTCTRL_OFFSET);
}
static void pmdomain_set_clock_autocontrol(u32 state, int domain_offset)
{
prcm_writel(state, domain_offset + CM_CLKSTCTRL_OFFSET);
}
static u32 pmdomain_get_clock_autoidle1(int domain_offset)
{
return prcm_readl(domain_offset + CM_AUTOIDLE1_OFFSET);
}
/* Core domain only */
static u32 pmdomain_get_clock_autoidle2(int domain_offset)
{
return prcm_readl(domain_offset + CM_AUTOIDLE2_OFFSET);
}
/* Core domain only */
static u32 pmdomain_get_clock_autoidle3(int domain_offset)
{
return prcm_readl(domain_offset + CM_AUTOIDLE3_OFFSET);
}
/* Core domain only */
static u32 pmdomain_get_clock_autoidle4(int domain_offset)
{
return prcm_readl(domain_offset + CM_AUTOIDLE4_OFFSET);
}
static void pmdomain_set_clock_autoidle1(u32 state, int domain_offset)
{
prcm_writel(state, CM_AUTOIDLE1_OFFSET + domain_offset);
}
/* Core domain only */
static void pmdomain_set_clock_autoidle2(u32 state, int domain_offset)
{
prcm_writel(state, CM_AUTOIDLE2_OFFSET + domain_offset);
}
/* Core domain only */
static void pmdomain_set_clock_autoidle3(u32 state, int domain_offset)
{
prcm_writel(state, CM_AUTOIDLE3_OFFSET + domain_offset);
}
/* Core domain only */
static void pmdomain_set_clock_autoidle4(u32 state, int domain_offset)
{
prcm_writel(state, CM_AUTOIDLE4_OFFSET + domain_offset);
}
/*
* Configures power management domains to idle clocks automatically.
*/
void pmdomain_set_autoidle(void)
{
u32 val;
/* Set PLL auto stop for 54M, 96M & DPLL */
pmdomain_set_clock_autoidle1(AUTO_54M(AUTO_STOPPED) |
AUTO_96M(AUTO_STOPPED) |
AUTO_DPLL(AUTO_STOPPED), PM_PLL_OFFSET);
/* External clock input control
* REVISIT: Should this be in clock framework?
*/
PRCM_CLKSRC_CTRL |= (0x3 << 3);
/* Configure number of 32KHz clock cycles for sys_clk */
PRCM_CLKSSETUP = 0x00ff;
/* Configure automatic voltage transition */
PRCM_VOLTSETUP = 0;
val = PRCM_VOLTCTRL;
val &= ~(SETOFF_LEVEL(0x3) | VOLT_LEVEL(0x3));
val |= SETOFF_LEVEL(1) | VOLT_LEVEL(1) | AUTO_EXTVOLT;
PRCM_VOLTCTRL = val;
/* Disable emulation tools functional clock */
PRCM_CLKEMUL_CTRL = 0x0;
/* Set core memory retention state */
val = pmdomain_get_powerstate(PM_CORE_OFFSET);
if (cpu_is_omap2420()) {
val &= ~(0x7 << 3);
val |= (MEM3RETSTATE | MEM2RETSTATE | MEM1RETSTATE);
} else {
val &= ~(0xf << 3);
val |= (MEM4RETSTATE | MEM3RETSTATE | MEM2RETSTATE |
MEM1RETSTATE);
}
pmdomain_set_powerstate(val, PM_CORE_OFFSET);
/* OCP interface smart idle. REVISIT: Enable autoidle bit0 ? */
val = SMS_SYSCONFIG;
val &= ~(0x3 << 3);
val |= (0x2 << 3) | (1 << 0);
SMS_SYSCONFIG |= val;
val = SDRC_SYSCONFIG;
val &= ~(0x3 << 3);
val |= (0x2 << 3);
SDRC_SYSCONFIG = val;
/* Configure L3 interface for smart idle.
* REVISIT: Enable autoidle bit0 ?
*/
val = GPMC_SYSCONFIG;
val &= ~(0x3 << 3);
val |= (0x2 << 3) | (1 << 0);
GPMC_SYSCONFIG = val;
pmdomain_set_powerstate(LOGICRETSTATE | POWERSTATE_RETENTION,
PM_MPU_OFFSET);
pmdomain_set_powerstate(POWERSTATE_RETENTION, PM_CORE_OFFSET);
if (!cpu_is_omap2420())
pmdomain_set_powerstate(POWERSTATE_RETENTION, PM_MDM_OFFSET);
/* Assume suspend function has saved the state for DSP and GFX */
pmdomain_set_powerstate(FORCESTATE | POWERSTATE_OFF, PM_DSP_OFFSET);
pmdomain_set_powerstate(FORCESTATE | POWERSTATE_OFF, PM_GFX_OFFSET);
#if 0
/* REVISIT: Internal USB needs special handling */
force_standby_usb();
if (cpu_is_omap2430())
force_hsmmc();
sdram_self_refresh_on_idle_req(1);
#endif
/* Enable clock auto control for all domains.
* Note that CORE domain includes also DSS, L4 & L3.
*/
pmdomain_set_clock_autocontrol(AUTOSTAT_MPU, PM_MPU_OFFSET);
pmdomain_set_clock_autocontrol(AUTOSTAT_GFX, PM_GFX_OFFSET);
pmdomain_set_clock_autocontrol(AUTOSTAT_DSS | AUTOSTAT_L4 | AUTOSTAT_L3,
PM_CORE_OFFSET);
if (cpu_is_omap2420())
pmdomain_set_clock_autocontrol(AUTOSTAT_IVA | AUTOSTAT_DSP,
PM_DSP_OFFSET);
else {
pmdomain_set_clock_autocontrol(AUTOSTAT_DSP, PM_DSP_OFFSET);
pmdomain_set_clock_autocontrol(AUTOSTAT_MDM, PM_MDM_OFFSET);
}
/* Enable clock autoidle for all domains */
pmdomain_set_clock_autoidle1(0x2, PM_DSP_OFFSET);
if (cpu_is_omap2420()) {
pmdomain_set_clock_autoidle1(0xfffffff9, PM_CORE_OFFSET);
pmdomain_set_clock_autoidle2(0x7, PM_CORE_OFFSET);
pmdomain_set_clock_autoidle1(0x3f, PM_WKUP_OFFSET);
} else {
pmdomain_set_clock_autoidle1(0xeafffff1, PM_CORE_OFFSET);
pmdomain_set_clock_autoidle2(0xfff, PM_CORE_OFFSET);
pmdomain_set_clock_autoidle1(0x7f, PM_WKUP_OFFSET);
pmdomain_set_clock_autoidle1(0x3, PM_MDM_OFFSET);
}
pmdomain_set_clock_autoidle3(0x7, PM_CORE_OFFSET);
pmdomain_set_clock_autoidle4(0x1f, PM_CORE_OFFSET);
}
/*
* Initializes power domains by removing wake-up dependencies and powering
* down DSP and GFX. Gets called from PM init. Note that DSP and IVA code
* must re-enable DSP and GFX when used.
*/
void __init pmdomain_init(void)
{
/* Remove all domain wakeup dependencies */
pmdomain_set_wakeup_dependencies(EN_WKUP | EN_CORE, PM_MPU_OFFSET);
pmdomain_set_wakeup_dependencies(0, PM_DSP_OFFSET);
pmdomain_set_wakeup_dependencies(0, PM_GFX_OFFSET);
pmdomain_set_wakeup_dependencies(EN_WKUP | EN_MPU, PM_CORE_OFFSET);
if (cpu_is_omap2430())
pmdomain_set_wakeup_dependencies(0, PM_MDM_OFFSET);
/* Power down DSP and GFX */
pmdomain_set_powerstate(POWERSTATE_OFF | FORCESTATE, PM_DSP_OFFSET);
pmdomain_set_powerstate(POWERSTATE_OFF | FORCESTATE, PM_GFX_OFFSET);
}

271
arch/arm/mach-omap2/pm.c
View File

@ -23,6 +23,7 @@
#include <linux/interrupt.h> #include <linux/interrupt.h>
#include <linux/sysfs.h> #include <linux/sysfs.h>
#include <linux/module.h> #include <linux/module.h>
#include <linux/delay.h>
#include <asm/io.h> #include <asm/io.h>
#include <asm/irq.h> #include <asm/irq.h>
@ -36,11 +37,18 @@
#include <asm/arch/sram.h> #include <asm/arch/sram.h>
#include <asm/arch/pm.h> #include <asm/arch/pm.h>
#include "prcm-regs.h"
static struct clk *vclk; static struct clk *vclk;
static void (*omap2_sram_idle)(void); static void (*omap2_sram_idle)(void);
static void (*omap2_sram_suspend)(int dllctrl, int cpu_rev); static void (*omap2_sram_suspend)(int dllctrl, int cpu_rev);
static void (*saved_idle)(void); static void (*saved_idle)(void);
extern void __init pmdomain_init(void);
extern void pmdomain_set_autoidle(void);
static unsigned int omap24xx_sleep_save[OMAP24XX_SLEEP_SAVE_SIZE];
void omap2_pm_idle(void) void omap2_pm_idle(void)
{ {
local_irq_disable(); local_irq_disable();
@ -87,23 +95,272 @@ static int omap2_pm_prepare(suspend_state_t state)
return error; return error;
} }
#define INT0_WAKE_MASK (OMAP_IRQ_BIT(INT_24XX_GPIO_BANK1) | \
OMAP_IRQ_BIT(INT_24XX_GPIO_BANK2) | \
OMAP_IRQ_BIT(INT_24XX_GPIO_BANK3))
#define INT1_WAKE_MASK (OMAP_IRQ_BIT(INT_24XX_GPIO_BANK4))
#define INT2_WAKE_MASK (OMAP_IRQ_BIT(INT_24XX_UART1_IRQ) | \
OMAP_IRQ_BIT(INT_24XX_UART2_IRQ) | \
OMAP_IRQ_BIT(INT_24XX_UART3_IRQ))
#define preg(reg) printk("%s\t(0x%p):\t0x%08x\n", #reg, &reg, reg);
static void omap2_pm_debug(char * desc)
{
printk("%s:\n", desc);
preg(CM_CLKSTCTRL_MPU);
preg(CM_CLKSTCTRL_CORE);
preg(CM_CLKSTCTRL_GFX);
preg(CM_CLKSTCTRL_DSP);
preg(CM_CLKSTCTRL_MDM);
preg(PM_PWSTCTRL_MPU);
preg(PM_PWSTCTRL_CORE);
preg(PM_PWSTCTRL_GFX);
preg(PM_PWSTCTRL_DSP);
preg(PM_PWSTCTRL_MDM);
preg(PM_PWSTST_MPU);
preg(PM_PWSTST_CORE);
preg(PM_PWSTST_GFX);
preg(PM_PWSTST_DSP);
preg(PM_PWSTST_MDM);
preg(CM_AUTOIDLE1_CORE);
preg(CM_AUTOIDLE2_CORE);
preg(CM_AUTOIDLE3_CORE);
preg(CM_AUTOIDLE4_CORE);
preg(CM_AUTOIDLE_WKUP);
preg(CM_AUTOIDLE_PLL);
preg(CM_AUTOIDLE_DSP);
preg(CM_AUTOIDLE_MDM);
preg(CM_ICLKEN1_CORE);
preg(CM_ICLKEN2_CORE);
preg(CM_ICLKEN3_CORE);
preg(CM_ICLKEN4_CORE);
preg(CM_ICLKEN_GFX);
preg(CM_ICLKEN_WKUP);
preg(CM_ICLKEN_DSP);
preg(CM_ICLKEN_MDM);
preg(CM_IDLEST1_CORE);
preg(CM_IDLEST2_CORE);
preg(CM_IDLEST3_CORE);
preg(CM_IDLEST4_CORE);
preg(CM_IDLEST_GFX);
preg(CM_IDLEST_WKUP);
preg(CM_IDLEST_CKGEN);
preg(CM_IDLEST_DSP);
preg(CM_IDLEST_MDM);
preg(RM_RSTST_MPU);
preg(RM_RSTST_GFX);
preg(RM_RSTST_WKUP);
preg(RM_RSTST_DSP);
preg(RM_RSTST_MDM);
preg(PM_WKDEP_MPU);
preg(PM_WKDEP_CORE);
preg(PM_WKDEP_GFX);
preg(PM_WKDEP_DSP);
preg(PM_WKDEP_MDM);
preg(CM_FCLKEN_WKUP);
preg(CM_ICLKEN_WKUP);
preg(CM_IDLEST_WKUP);
preg(CM_AUTOIDLE_WKUP);
preg(CM_CLKSEL_WKUP);
preg(PM_WKEN_WKUP);
preg(PM_WKST_WKUP);
}
static inline void omap2_pm_save_registers(void)
{
/* Save interrupt registers */
OMAP24XX_SAVE(INTC_MIR0);
OMAP24XX_SAVE(INTC_MIR1);
OMAP24XX_SAVE(INTC_MIR2);
/* Save power control registers */
OMAP24XX_SAVE(CM_CLKSTCTRL_MPU);
OMAP24XX_SAVE(CM_CLKSTCTRL_CORE);
OMAP24XX_SAVE(CM_CLKSTCTRL_GFX);
OMAP24XX_SAVE(CM_CLKSTCTRL_DSP);
OMAP24XX_SAVE(CM_CLKSTCTRL_MDM);
/* Save power state registers */
OMAP24XX_SAVE(PM_PWSTCTRL_MPU);
OMAP24XX_SAVE(PM_PWSTCTRL_CORE);
OMAP24XX_SAVE(PM_PWSTCTRL_GFX);
OMAP24XX_SAVE(PM_PWSTCTRL_DSP);
OMAP24XX_SAVE(PM_PWSTCTRL_MDM);
/* Save autoidle registers */
OMAP24XX_SAVE(CM_AUTOIDLE1_CORE);
OMAP24XX_SAVE(CM_AUTOIDLE2_CORE);
OMAP24XX_SAVE(CM_AUTOIDLE3_CORE);
OMAP24XX_SAVE(CM_AUTOIDLE4_CORE);
OMAP24XX_SAVE(CM_AUTOIDLE_WKUP);
OMAP24XX_SAVE(CM_AUTOIDLE_PLL);
OMAP24XX_SAVE(CM_AUTOIDLE_DSP);
OMAP24XX_SAVE(CM_AUTOIDLE_MDM);
/* Save idle state registers */
OMAP24XX_SAVE(CM_IDLEST1_CORE);
OMAP24XX_SAVE(CM_IDLEST2_CORE);
OMAP24XX_SAVE(CM_IDLEST3_CORE);
OMAP24XX_SAVE(CM_IDLEST4_CORE);
OMAP24XX_SAVE(CM_IDLEST_GFX);
OMAP24XX_SAVE(CM_IDLEST_WKUP);
OMAP24XX_SAVE(CM_IDLEST_CKGEN);
OMAP24XX_SAVE(CM_IDLEST_DSP);
OMAP24XX_SAVE(CM_IDLEST_MDM);
/* Save clock registers */
OMAP24XX_SAVE(CM_FCLKEN1_CORE);
OMAP24XX_SAVE(CM_FCLKEN2_CORE);
OMAP24XX_SAVE(CM_ICLKEN1_CORE);
OMAP24XX_SAVE(CM_ICLKEN2_CORE);
OMAP24XX_SAVE(CM_ICLKEN3_CORE);
OMAP24XX_SAVE(CM_ICLKEN4_CORE);
}
static inline void omap2_pm_restore_registers(void)
{
/* Restore clock state registers */
OMAP24XX_RESTORE(CM_CLKSTCTRL_MPU);
OMAP24XX_RESTORE(CM_CLKSTCTRL_CORE);
OMAP24XX_RESTORE(CM_CLKSTCTRL_GFX);
OMAP24XX_RESTORE(CM_CLKSTCTRL_DSP);
OMAP24XX_RESTORE(CM_CLKSTCTRL_MDM);
/* Restore power state registers */
OMAP24XX_RESTORE(PM_PWSTCTRL_MPU);
OMAP24XX_RESTORE(PM_PWSTCTRL_CORE);
OMAP24XX_RESTORE(PM_PWSTCTRL_GFX);
OMAP24XX_RESTORE(PM_PWSTCTRL_DSP);
OMAP24XX_RESTORE(PM_PWSTCTRL_MDM);
/* Restore idle state registers */
OMAP24XX_RESTORE(CM_IDLEST1_CORE);
OMAP24XX_RESTORE(CM_IDLEST2_CORE);
OMAP24XX_RESTORE(CM_IDLEST3_CORE);
OMAP24XX_RESTORE(CM_IDLEST4_CORE);
OMAP24XX_RESTORE(CM_IDLEST_GFX);
OMAP24XX_RESTORE(CM_IDLEST_WKUP);
OMAP24XX_RESTORE(CM_IDLEST_CKGEN);
OMAP24XX_RESTORE(CM_IDLEST_DSP);
OMAP24XX_RESTORE(CM_IDLEST_MDM);
/* Restore autoidle registers */
OMAP24XX_RESTORE(CM_AUTOIDLE1_CORE);
OMAP24XX_RESTORE(CM_AUTOIDLE2_CORE);
OMAP24XX_RESTORE(CM_AUTOIDLE3_CORE);
OMAP24XX_RESTORE(CM_AUTOIDLE4_CORE);
OMAP24XX_RESTORE(CM_AUTOIDLE_WKUP);
OMAP24XX_RESTORE(CM_AUTOIDLE_PLL);
OMAP24XX_RESTORE(CM_AUTOIDLE_DSP);
OMAP24XX_RESTORE(CM_AUTOIDLE_MDM);
/* Restore clock registers */
OMAP24XX_RESTORE(CM_FCLKEN1_CORE);
OMAP24XX_RESTORE(CM_FCLKEN2_CORE);
OMAP24XX_RESTORE(CM_ICLKEN1_CORE);
OMAP24XX_RESTORE(CM_ICLKEN2_CORE);
OMAP24XX_RESTORE(CM_ICLKEN3_CORE);
OMAP24XX_RESTORE(CM_ICLKEN4_CORE);
/* REVISIT: Clear interrupts here */
/* Restore interrupt registers */
OMAP24XX_RESTORE(INTC_MIR0);
OMAP24XX_RESTORE(INTC_MIR1);
OMAP24XX_RESTORE(INTC_MIR2);
}
static int omap2_pm_suspend(void)
{
int processor_type = 0;
/* REVISIT: 0x21 or 0x26? */
if (cpu_is_omap2420())
processor_type = 0x21;
if (!processor_type)
return -ENOTSUPP;
local_irq_disable();
local_fiq_disable();
omap2_pm_save_registers();
/* Disable interrupts except for the wake events */
INTC_MIR_SET0 = 0xffffffff & ~INT0_WAKE_MASK;
INTC_MIR_SET1 = 0xffffffff & ~INT1_WAKE_MASK;
INTC_MIR_SET2 = 0xffffffff & ~INT2_WAKE_MASK;
pmdomain_set_autoidle();
/* Clear old wake-up events */
PM_WKST1_CORE = 0;
PM_WKST2_CORE = 0;
PM_WKST_WKUP = 0;
/* Enable wake-up events */
PM_WKEN1_CORE = (1 << 22) | (1 << 21); /* UART1 & 2 */
PM_WKEN2_CORE = (1 << 2); /* UART3 */
PM_WKEN_WKUP = (1 << 2) | (1 << 0); /* GPIO & GPT1 */
/* Disable clocks except for CM_ICLKEN2_CORE. It gets disabled
* in the SRAM suspend code */
CM_FCLKEN1_CORE = 0;
CM_FCLKEN2_CORE = 0;
CM_ICLKEN1_CORE = 0;
CM_ICLKEN3_CORE = 0;
CM_ICLKEN4_CORE = 0;
omap2_pm_debug("Status before suspend");
/* Must wait for serial buffers to clear */
mdelay(200);
/* Jump to SRAM suspend code
* REVISIT: When is this SDRC_DLLB_CTRL?
*/
omap2_sram_suspend(SDRC_DLLA_CTRL, processor_type);
/* Back from sleep */
omap2_pm_restore_registers();
local_fiq_enable();
local_irq_enable();
return 0;
}
static int omap2_pm_enter(suspend_state_t state) static int omap2_pm_enter(suspend_state_t state)
{ {
int ret = 0;
switch (state) switch (state)
{ {
case PM_SUSPEND_STANDBY: case PM_SUSPEND_STANDBY:
case PM_SUSPEND_MEM: case PM_SUSPEND_MEM:
/* FIXME: Add suspend */ ret = omap2_pm_suspend();
break; break;
case PM_SUSPEND_DISK: case PM_SUSPEND_DISK:
return -ENOTSUPP; ret = -ENOTSUPP;
break;
default: default:
return -EINVAL; ret = -EINVAL;
} }
return 0; return ret;
} }
static int omap2_pm_finish(suspend_state_t state) static int omap2_pm_finish(suspend_state_t state)
@ -143,6 +400,8 @@ int __init omap2_pm_init(void)
pm_set_ops(&omap_pm_ops); pm_set_ops(&omap_pm_ops);
pm_idle = omap2_pm_idle; pm_idle = omap2_pm_idle;
pmdomain_init();
return 0; return 0;
} }

86
arch/arm/mach-omap2/timer-gp.c
View File

@ -6,6 +6,7 @@
* Copyright (C) 2005 Nokia Corporation * Copyright (C) 2005 Nokia Corporation
* Author: Paul Mundt <paul.mundt@nokia.com> * Author: Paul Mundt <paul.mundt@nokia.com>
* Juha Yrjölä <juha.yrjola@nokia.com> * Juha Yrjölä <juha.yrjola@nokia.com>
* OMAP Dual-mode timer framework support by Timo Teras
* *
* Some parts based off of TI's 24xx code: * Some parts based off of TI's 24xx code:
* *
@ -22,54 +23,18 @@
#include <linux/interrupt.h> #include <linux/interrupt.h>
#include <linux/err.h> #include <linux/err.h>
#include <linux/clk.h> #include <linux/clk.h>
#include <linux/delay.h>
#include <asm/mach/time.h> #include <asm/mach/time.h>
#include <asm/delay.h> #include <asm/arch/dmtimer.h>
#include <asm/io.h>
#define OMAP2_GP_TIMER1_BASE 0x48028000 static struct omap_dm_timer *gptimer;
#define OMAP2_GP_TIMER2_BASE 0x4802a000
#define OMAP2_GP_TIMER3_BASE 0x48078000
#define OMAP2_GP_TIMER4_BASE 0x4807a000
#define GP_TIMER_TIDR 0x00 static inline void omap2_gp_timer_start(unsigned long load_val)
#define GP_TIMER_TISR 0x18
#define GP_TIMER_TIER 0x1c
#define GP_TIMER_TCLR 0x24
#define GP_TIMER_TCRR 0x28
#define GP_TIMER_TLDR 0x2c
#define GP_TIMER_TSICR 0x40
#define OS_TIMER_NR 1 /* GP timer 2 */
static unsigned long timer_base[] = {
IO_ADDRESS(OMAP2_GP_TIMER1_BASE),
IO_ADDRESS(OMAP2_GP_TIMER2_BASE),
IO_ADDRESS(OMAP2_GP_TIMER3_BASE),
IO_ADDRESS(OMAP2_GP_TIMER4_BASE),
};
static inline unsigned int timer_read_reg(int nr, unsigned int reg)
{ {
return __raw_readl(timer_base[nr] + reg); omap_dm_timer_set_load(gptimer, 1, 0xffffffff - load_val);
} omap_dm_timer_set_int_enable(gptimer, OMAP_TIMER_INT_OVERFLOW);
omap_dm_timer_start(gptimer);
static inline void timer_write_reg(int nr, unsigned int reg, unsigned int val)
{
__raw_writel(val, timer_base[nr] + reg);
}
/* Note that we always enable the clock prescale divider bit */
static inline void omap2_gp_timer_start(int nr, unsigned long load_val)
{
unsigned int tmp;
tmp = 0xffffffff - load_val;
timer_write_reg(nr, GP_TIMER_TLDR, tmp);
timer_write_reg(nr, GP_TIMER_TCRR, tmp);
timer_write_reg(nr, GP_TIMER_TIER, 1 << 1);
timer_write_reg(nr, GP_TIMER_TCLR, (1 << 5) | (1 << 1) | 1);
} }
static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id, static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id,
@ -77,7 +42,7 @@ static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id,
{ {
write_seqlock(&xtime_lock); write_seqlock(&xtime_lock);
timer_write_reg(OS_TIMER_NR, GP_TIMER_TISR, 1 << 1); omap_dm_timer_write_status(gptimer, OMAP_TIMER_INT_OVERFLOW);
timer_tick(regs); timer_tick(regs);
write_sequnlock(&xtime_lock); write_sequnlock(&xtime_lock);
@ -87,41 +52,26 @@ static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id,
static struct irqaction omap2_gp_timer_irq = { static struct irqaction omap2_gp_timer_irq = {
.name = "gp timer", .name = "gp timer",
.flags = SA_INTERRUPT, .flags = SA_INTERRUPT | SA_TIMER,
.handler = omap2_gp_timer_interrupt, .handler = omap2_gp_timer_interrupt,
}; };
static void __init omap2_gp_timer_init(void) static void __init omap2_gp_timer_init(void)
{ {
struct clk * sys_ck; u32 tick_period;
u32 tick_period = 120000;
u32 l;
/* Reset clock and prescale value */ omap_dm_timer_init();
timer_write_reg(OS_TIMER_NR, GP_TIMER_TCLR, 0); gptimer = omap_dm_timer_request_specific(1);
BUG_ON(gptimer == NULL);
sys_ck = clk_get(NULL, "sys_ck"); omap_dm_timer_set_source(gptimer, OMAP_TIMER_SRC_SYS_CLK);
if (IS_ERR(sys_ck)) tick_period = clk_get_rate(omap_dm_timer_get_fclk(gptimer)) / 100;
printk(KERN_ERR "Could not get sys_ck\n");
else {
clk_enable(sys_ck);
tick_period = clk_get_rate(sys_ck) / 100;
clk_put(sys_ck);
}
tick_period /= 2; /* Minimum prescale divider is 2 */
tick_period -= 1; tick_period -= 1;
l = timer_read_reg(OS_TIMER_NR, GP_TIMER_TIDR); setup_irq(omap_dm_timer_get_irq(gptimer), &omap2_gp_timer_irq);
printk(KERN_INFO "OMAP2 GP timer (HW version %d.%d)\n", omap2_gp_timer_start(tick_period);
(l >> 4) & 0x0f, l & 0x0f);
setup_irq(38, &omap2_gp_timer_irq);
omap2_gp_timer_start(OS_TIMER_NR, tick_period);
} }
struct sys_timer omap_timer = { struct sys_timer omap_timer = {
.init = omap2_gp_timer_init, .init = omap2_gp_timer_init,
}; };

19
arch/arm/mach-pxa/Kconfig
View File

@ -35,6 +35,10 @@ config PXA_SHARPSL
SL-C3000 (Spitz), SL-C3100 (Borzoi) or SL-C6000x (Tosa) SL-C3000 (Spitz), SL-C3100 (Borzoi) or SL-C6000x (Tosa)
handheld computer. handheld computer.
config MACH_TRIZEPS4
bool "Keith und Koep Trizeps4 DIMM-Module"
select PXA27x
endchoice endchoice
if PXA_SHARPSL if PXA_SHARPSL
@ -55,6 +59,21 @@ endchoice
endif endif
if MACH_TRIZEPS4
choice
prompt "Select base board for Trizeps 4 module"
config MACH_TRIZEPS4_CONXS
bool "ConXS Eval Board"
config MACH_TRIZEPS4_ANY
bool "another Board"
endchoice
endif
endmenu endmenu
config MACH_POODLE config MACH_POODLE

2
arch/arm/mach-pxa/Makefile
View File

@ -12,6 +12,7 @@ obj-$(CONFIG_ARCH_LUBBOCK) += lubbock.o
obj-$(CONFIG_MACH_LOGICPD_PXA270) += lpd270.o obj-$(CONFIG_MACH_LOGICPD_PXA270) += lpd270.o
obj-$(CONFIG_MACH_MAINSTONE) += mainstone.o obj-$(CONFIG_MACH_MAINSTONE) += mainstone.o
obj-$(CONFIG_ARCH_PXA_IDP) += idp.o obj-$(CONFIG_ARCH_PXA_IDP) += idp.o
obj-$(CONFIG_MACH_TRIZEPS4) += trizeps4.o
obj-$(CONFIG_PXA_SHARP_C7xx) += corgi.o corgi_ssp.o corgi_lcd.o sharpsl_pm.o corgi_pm.o obj-$(CONFIG_PXA_SHARP_C7xx) += corgi.o corgi_ssp.o corgi_lcd.o sharpsl_pm.o corgi_pm.o
obj-$(CONFIG_PXA_SHARP_Cxx00) += spitz.o corgi_ssp.o corgi_lcd.o sharpsl_pm.o spitz_pm.o obj-$(CONFIG_PXA_SHARP_Cxx00) += spitz.o corgi_ssp.o corgi_lcd.o sharpsl_pm.o spitz_pm.o
obj-$(CONFIG_MACH_AKITA) += akita-ioexp.o obj-$(CONFIG_MACH_AKITA) += akita-ioexp.o
@ -23,6 +24,7 @@ led-y := leds.o
led-$(CONFIG_ARCH_LUBBOCK) += leds-lubbock.o led-$(CONFIG_ARCH_LUBBOCK) += leds-lubbock.o
led-$(CONFIG_MACH_MAINSTONE) += leds-mainstone.o led-$(CONFIG_MACH_MAINSTONE) += leds-mainstone.o
led-$(CONFIG_ARCH_PXA_IDP) += leds-idp.o led-$(CONFIG_ARCH_PXA_IDP) += leds-idp.o
led-$(CONFIG_MACH_TRIZEPS4) += leds-trizeps4.o
obj-$(CONFIG_LEDS) += $(led-y) obj-$(CONFIG_LEDS) += $(led-y)

134
arch/arm/mach-pxa/leds-trizeps4.c Normal file
View File

@ -0,0 +1,134 @@
/*
* linux/arch/arm/mach-pxa/leds-trizeps4.c
*
* Author: Jürgen Schindele
* Created: 20 02, 2006
* Copyright: Jürgen Schindele
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/config.h>
#include <linux/init.h>
#include <asm/hardware.h>
#include <asm/system.h>
#include <asm/types.h>
#include <asm/leds.h>
#include <asm/arch/pxa-regs.h>
#include <asm/arch/trizeps4.h>
#include "leds.h"
#define LED_STATE_ENABLED 1
#define LED_STATE_CLAIMED 2
#define SYS_BUSY 0x01
#define HEARTBEAT 0x02
#define BLINK 0x04
static unsigned int led_state;
static unsigned int hw_led_state;
void trizeps4_leds_event(led_event_t evt)
{
unsigned long flags;
local_irq_save(flags);
switch (evt) {
case led_start:
hw_led_state = 0;
pxa_gpio_mode( GPIO_SYS_BUSY_LED | GPIO_OUT); /* LED1 */
pxa_gpio_mode( GPIO_HEARTBEAT_LED | GPIO_OUT); /* LED2 */
led_state = LED_STATE_ENABLED;
break;
case led_stop:
led_state &= ~LED_STATE_ENABLED;
break;
case led_claim:
led_state |= LED_STATE_CLAIMED;
hw_led_state = 0;
break;
case led_release:
led_state &= ~LED_STATE_CLAIMED;
hw_led_state = 0;
break;
#ifdef CONFIG_LEDS_TIMER
case led_timer:
hw_led_state ^= HEARTBEAT;
break;
#endif
#ifdef CONFIG_LEDS_CPU
case led_idle_start:
hw_led_state &= ~SYS_BUSY;
break;
case led_idle_end:
hw_led_state |= SYS_BUSY;
break;
#endif
case led_halted:
break;
case led_green_on:
hw_led_state |= BLINK;
break;
case led_green_off:
hw_led_state &= ~BLINK;
break;
case led_amber_on:
break;
case led_amber_off:
break;
case led_red_on:
break;
case led_red_off:
break;
default:
break;
}
if (led_state & LED_STATE_ENABLED) {
switch (hw_led_state) {
case 0:
GPSR(GPIO_SYS_BUSY_LED) |= GPIO_bit(GPIO_SYS_BUSY_LED);
GPSR(GPIO_HEARTBEAT_LED) |= GPIO_bit(GPIO_HEARTBEAT_LED);
break;
case 1:
GPCR(GPIO_SYS_BUSY_LED) |= GPIO_bit(GPIO_SYS_BUSY_LED);
GPSR(GPIO_HEARTBEAT_LED) |= GPIO_bit(GPIO_HEARTBEAT_LED);
break;
case 2:
GPSR(GPIO_SYS_BUSY_LED) |= GPIO_bit(GPIO_SYS_BUSY_LED);
GPCR(GPIO_HEARTBEAT_LED) |= GPIO_bit(GPIO_HEARTBEAT_LED);
break;
case 3:
GPCR(GPIO_SYS_BUSY_LED) |= GPIO_bit(GPIO_SYS_BUSY_LED);
GPCR(GPIO_HEARTBEAT_LED) |= GPIO_bit(GPIO_HEARTBEAT_LED);
break;
}
}
else {
/* turn all off */
GPSR(GPIO_SYS_BUSY_LED) |= GPIO_bit(GPIO_SYS_BUSY_LED);
GPSR(GPIO_HEARTBEAT_LED) |= GPIO_bit(GPIO_HEARTBEAT_LED);
}
local_irq_restore(flags);
}

2
arch/arm/mach-pxa/leds.c
View File

@ -24,6 +24,8 @@ pxa_leds_init(void)
leds_event = mainstone_leds_event; leds_event = mainstone_leds_event;
if (machine_is_pxa_idp()) if (machine_is_pxa_idp())
leds_event = idp_leds_event; leds_event = idp_leds_event;
if (machine_is_trizeps4())
leds_event = trizeps4_leds_event;
leds_event(led_start); leds_event(led_start);
return 0; return 0;

1
arch/arm/mach-pxa/leds.h
View File

@ -10,3 +10,4 @@
extern void idp_leds_event(led_event_t evt); extern void idp_leds_event(led_event_t evt);
extern void lubbock_leds_event(led_event_t evt); extern void lubbock_leds_event(led_event_t evt);
extern void mainstone_leds_event(led_event_t evt); extern void mainstone_leds_event(led_event_t evt);
extern void trizeps4_leds_event(led_event_t evt);

126
arch/arm/mach-pxa/lpd270.c
View File

@ -248,58 +248,137 @@ static void lpd270_backlight_power(int on)
/* 5.7" TFT QVGA (LoLo display number 1) */ /* 5.7" TFT QVGA (LoLo display number 1) */
static struct pxafb_mach_info sharp_lq057q3dc02 __initdata = { static struct pxafb_mach_info sharp_lq057q3dc02 __initdata = {
.pixclock = 100000, .pixclock = 150000,
.xres = 240, .xres = 320,
.yres = 320, .yres = 240,
.bpp = 16, .bpp = 16,
.hsync_len = 64, .hsync_len = 0x14,
.left_margin = 0x27, .left_margin = 0x28,
.right_margin = 0x09, .right_margin = 0x0a,
.vsync_len = 0x04, .vsync_len = 0x02,
.upper_margin = 0x08, .upper_margin = 0x08,
.lower_margin = 0x14, .lower_margin = 0x14,
.sync = 0, .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
.lccr0 = 0x07800080, .lccr0 = 0x07800080,
.lccr3 = 0x04400007, .lccr3 = 0x00400000,
.pxafb_backlight_power = lpd270_backlight_power,
};
/* 12.1" TFT SVGA (LoLo display number 2) */
static struct pxafb_mach_info sharp_lq121s1dg31 __initdata = {
.pixclock = 50000,
.xres = 800,
.yres = 600,
.bpp = 16,
.hsync_len = 0x05,
.left_margin = 0x52,
.right_margin = 0x05,
.vsync_len = 0x04,
.upper_margin = 0x14,
.lower_margin = 0x0a,
.sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
.lccr0 = 0x07800080,
.lccr3 = 0x00400000,
.pxafb_backlight_power = lpd270_backlight_power,
};
/* 3.6" TFT QVGA (LoLo display number 3) */
static struct pxafb_mach_info sharp_lq036q1da01 __initdata = {
.pixclock = 150000,
.xres = 320,
.yres = 240,
.bpp = 16,
.hsync_len = 0x0e,
.left_margin = 0x04,
.right_margin = 0x0a,
.vsync_len = 0x03,
.upper_margin = 0x03,
.lower_margin = 0x03,
.sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
.lccr0 = 0x07800080,
.lccr3 = 0x00400000,
.pxafb_backlight_power = lpd270_backlight_power, .pxafb_backlight_power = lpd270_backlight_power,
}; };
/* 6.4" TFT VGA (LoLo display number 5) */ /* 6.4" TFT VGA (LoLo display number 5) */
static struct pxafb_mach_info sharp_lq64d343 __initdata = { static struct pxafb_mach_info sharp_lq64d343 __initdata = {
.pixclock = 20000, .pixclock = 25000,
.xres = 640, .xres = 640,
.yres = 480, .yres = 480,
.bpp = 16, .bpp = 16,
.hsync_len = 49, .hsync_len = 0x31,
.left_margin = 0x89, .left_margin = 0x89,
.right_margin = 0x19, .right_margin = 0x19,
.vsync_len = 18, .vsync_len = 0x12,
.upper_margin = 0x22, .upper_margin = 0x22,
.lower_margin = 0, .lower_margin = 0x00,
.sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
.lccr0 = 0x07800080, .lccr0 = 0x07800080,
.lccr3 = 0x04400001, .lccr3 = 0x00400000,
.pxafb_backlight_power = lpd270_backlight_power,
};
/* 10.4" TFT VGA (LoLo display number 7) */
static struct pxafb_mach_info sharp_lq10d368 __initdata = {
.pixclock = 25000,
.xres = 640,
.yres = 480,
.bpp = 16,
.hsync_len = 0x31,
.left_margin = 0x89,
.right_margin = 0x19,
.vsync_len = 0x12,
.upper_margin = 0x22,
.lower_margin = 0x00,
.sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
.lccr0 = 0x07800080,
.lccr3 = 0x00400000,
.pxafb_backlight_power = lpd270_backlight_power, .pxafb_backlight_power = lpd270_backlight_power,
}; };
/* 3.5" TFT QVGA (LoLo display number 8) */ /* 3.5" TFT QVGA (LoLo display number 8) */
static struct pxafb_mach_info sharp_lq035q7db02_20 __initdata = { static struct pxafb_mach_info sharp_lq035q7db02_20 __initdata = {
.pixclock = 100000, .pixclock = 150000,
.xres = 240, .xres = 240,
.yres = 320, .yres = 320,
.bpp = 16, .bpp = 16,
.hsync_len = 0x34, .hsync_len = 0x0e,
.left_margin = 0x09, .left_margin = 0x0a,
.right_margin = 0x09, .right_margin = 0x0a,
.vsync_len = 0x08, .vsync_len = 0x03,
.upper_margin = 0x05, .upper_margin = 0x05,
.lower_margin = 0x14, .lower_margin = 0x14,
.sync = 0, .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
.lccr0 = 0x07800080, .lccr0 = 0x07800080,
.lccr3 = 0x04400007, .lccr3 = 0x00400000,
.pxafb_backlight_power = lpd270_backlight_power, .pxafb_backlight_power = lpd270_backlight_power,
}; };
static struct pxafb_mach_info *lpd270_lcd_to_use;
static int __init lpd270_set_lcd(char *str)
{
if (!strnicmp(str, "lq057q3dc02", 11)) {
lpd270_lcd_to_use = &sharp_lq057q3dc02;
} else if (!strnicmp(str, "lq121s1dg31", 11)) {
lpd270_lcd_to_use = &sharp_lq121s1dg31;
} else if (!strnicmp(str, "lq036q1da01", 11)) {
lpd270_lcd_to_use = &sharp_lq036q1da01;
} else if (!strnicmp(str, "lq64d343", 8)) {
lpd270_lcd_to_use = &sharp_lq64d343;
} else if (!strnicmp(str, "lq10d368", 8)) {
lpd270_lcd_to_use = &sharp_lq10d368;
} else if (!strnicmp(str, "lq035q7db02-20", 14)) {
lpd270_lcd_to_use = &sharp_lq035q7db02_20;
} else {
printk(KERN_INFO "lpd270: unknown lcd panel [%s]\n", str);
}
return 1;
}
__setup("lcd=", lpd270_set_lcd);
static struct platform_device *platform_devices[] __initdata = { static struct platform_device *platform_devices[] __initdata = {
&smc91x_device, &smc91x_device,
&lpd270_audio_device, &lpd270_audio_device,
@ -345,9 +424,8 @@ static void __init lpd270_init(void)
platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
// set_pxa_fb_info(&sharp_lq057q3dc02); if (lpd270_lcd_to_use != NULL)
set_pxa_fb_info(&sharp_lq64d343); set_pxa_fb_info(lpd270_lcd_to_use);
// set_pxa_fb_info(&sharp_lq035q7db02_20);
pxa_set_ohci_info(&lpd270_ohci_platform_data); pxa_set_ohci_info(&lpd270_ohci_platform_data);
} }

471
arch/arm/mach-pxa/trizeps4.c Normal file
View File

@ -0,0 +1,471 @@
/*
* linux/arch/arm/mach-pxa/trizeps4.c
*
* Support for the Keith und Koep Trizeps4 Module Platform.
*
* Author: Jürgen Schindele
* Created: 20 02, 2006
* Copyright: Jürgen Schindele
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/sysdev.h>
#include <linux/interrupt.h>
#include <linux/sched.h>
#include <linux/bitops.h>
#include <linux/fb.h>
#include <linux/ioport.h>
#include <linux/delay.h>
#include <linux/serial_8250.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <asm/types.h>
#include <asm/setup.h>
#include <asm/memory.h>
#include <asm/mach-types.h>
#include <asm/hardware.h>
#include <asm/irq.h>
#include <asm/sizes.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
#include <asm/mach/flash.h>
#include <asm/arch/pxa-regs.h>
#include <asm/arch/trizeps4.h>
#include <asm/arch/audio.h>
#include <asm/arch/pxafb.h>
#include <asm/arch/mmc.h>
#include <asm/arch/irda.h>
#include <asm/arch/ohci.h>
#include "generic.h"
/********************************************************************************************
* ONBOARD FLASH
********************************************************************************************/
static struct mtd_partition trizeps4_partitions[] = {
{
.name = "Bootloader",
.size = 0x00040000,
.offset = 0,
.mask_flags = MTD_WRITEABLE /* force read-only */
},{
.name = "Kernel",
.size = 0x00400000,
.offset = 0x00040000
},{
.name = "Filesystem",
.size = MTDPART_SIZ_FULL,
.offset = 0x00440000
}
};
static struct flash_platform_data trizeps4_flash_data[] = {
{
.map_name = "cfi_probe",
.parts = trizeps4_partitions,
.nr_parts = ARRAY_SIZE(trizeps4_partitions)
}
};
static struct resource flash_resource = {
.start = PXA_CS0_PHYS,
.end = PXA_CS0_PHYS + SZ_64M - 1,
.flags = IORESOURCE_MEM,
};
static struct platform_device flash_device = {
.name = "pxa2xx-flash",
.id = 0,
.dev = {
.platform_data = &trizeps4_flash_data,
},
.resource = &flash_resource,
.num_resources = 1,
};
/********************************************************************************************
* DAVICOM DM9000 Ethernet
********************************************************************************************/
static struct resource dm9000_resources[] = {
[0] = {
.start = TRIZEPS4_ETH_PHYS+0x300,
.end = TRIZEPS4_ETH_PHYS+0x400-1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = TRIZEPS4_ETH_PHYS+0x8300,
.end = TRIZEPS4_ETH_PHYS+0x8400-1,
.flags = IORESOURCE_MEM,
},
[2] = {
.start = TRIZEPS4_ETH_IRQ,
.end = TRIZEPS4_ETH_IRQ,
.flags = (IORESOURCE_IRQ | IRQT_RISING),
},
};
static struct platform_device dm9000_device = {
.name = "dm9000",
.id = -1,
.num_resources = ARRAY_SIZE(dm9000_resources),
.resource = dm9000_resources,
};
/********************************************************************************************
* PXA270 serial ports
********************************************************************************************/
static struct plat_serial8250_port tri_serial_ports[] = {
#ifdef CONFIG_SERIAL_PXA
/* this uses the own PXA driver */
{
0,
},
#else
/* this uses the generic 8520 driver */
[0] = {
.membase = (void *)&FFUART,
.irq = IRQ_FFUART,
.flags = UPF_BOOT_AUTOCONF,
.iotype = UPIO_MEM32,
.regshift = 2,
.uartclk = (921600*16),
},
[1] = {
.membase = (void *)&BTUART,
.irq = IRQ_BTUART,
.flags = UPF_BOOT_AUTOCONF,
.iotype = UPIO_MEM32,
.regshift = 2,
.uartclk = (921600*16),
},
{
0,
},
#endif
};
static struct platform_device uart_devices = {
.name = "serial8250",
.id = 0,
.dev = {
.platform_data = tri_serial_ports,
},
.num_resources = 0,
.resource = NULL,
};
/********************************************************************************************
* PXA270 ac97 sound codec
********************************************************************************************/
static struct platform_device ac97_audio_device = {
.name = "pxa2xx-ac97",
.id = -1,
};
static struct platform_device * trizeps4_devices[] __initdata = {
&flash_device,
&uart_devices,
&dm9000_device,
&ac97_audio_device,
};
#ifdef CONFIG_MACH_TRIZEPS4_CONXS
static short trizeps_conxs_bcr;
/* PCCARD power switching supports only 3,3V */
void board_pcmcia_power(int power)
{
if (power) {
/* switch power on, put in reset and enable buffers */
trizeps_conxs_bcr |= power;
trizeps_conxs_bcr |= ConXS_BCR_CF_RESET;
trizeps_conxs_bcr &= ~(ConXS_BCR_CF_BUF_EN);
ConXS_BCR = trizeps_conxs_bcr;
/* wait a little */
udelay(2000);
/* take reset away */
trizeps_conxs_bcr &= ~(ConXS_BCR_CF_RESET);
ConXS_BCR = trizeps_conxs_bcr;
udelay(2000);
} else {
/* put in reset */
trizeps_conxs_bcr |= ConXS_BCR_CF_RESET;
ConXS_BCR = trizeps_conxs_bcr;
udelay(1000);
/* switch power off */
trizeps_conxs_bcr &= ~(0xf);
ConXS_BCR = trizeps_conxs_bcr;
}
pr_debug("%s: o%s 0x%x\n", __FUNCTION__, power ? "n": "ff", trizeps_conxs_bcr);
}
/* backlight power switching for LCD panel */
static void board_backlight_power(int on)
{
if (on) {
trizeps_conxs_bcr |= ConXS_BCR_L_DISP;
} else {
trizeps_conxs_bcr &= ~ConXS_BCR_L_DISP;
}
pr_debug("%s: o%s 0x%x\n", __FUNCTION__, on ? "n" : "ff", trizeps_conxs_bcr);
ConXS_BCR = trizeps_conxs_bcr;
}
/* Powersupply for MMC/SD cardslot */
static void board_mci_power(struct device *dev, unsigned int vdd)
{
struct pxamci_platform_data* p_d = dev->platform_data;
if (( 1 << vdd) & p_d->ocr_mask) {
pr_debug("%s: on\n", __FUNCTION__);
/* FIXME fill in values here */
} else {
pr_debug("%s: off\n", __FUNCTION__);
/* FIXME fill in values here */
}
}
static short trizeps_conxs_ircr;
/* Switch modes and Power for IRDA receiver */
static void board_irda_mode(struct device *dev, int mode)
{
unsigned long flags;
local_irq_save(flags);
if (mode & IR_SIRMODE) {
/* Slow mode */
trizeps_conxs_ircr &= ~ConXS_IRCR_MODE;
} else if (mode & IR_FIRMODE) {
/* Fast mode */
trizeps_conxs_ircr |= ConXS_IRCR_MODE;
}
if (mode & IR_OFF) {
trizeps_conxs_ircr |= ConXS_IRCR_SD;
} else {
trizeps_conxs_ircr &= ~ConXS_IRCR_SD;
}
/* FIXME write values to register */
local_irq_restore(flags);
}
#else
/* for other baseboards define dummies */
void board_pcmcia_power(int power) {;}
#define board_backlight_power NULL
#define board_mci_power NULL
#define board_irda_mode NULL
#endif /* CONFIG_MACH_TRIZEPS4_CONXS */
EXPORT_SYMBOL(board_pcmcia_power);
static int trizeps4_mci_init(struct device *dev, irqreturn_t (*mci_detect_int)(int, void *, struct pt_regs *), void *data)
{
int err;
/* setup GPIO for PXA27x MMC controller */
pxa_gpio_mode(GPIO32_MMCCLK_MD);
pxa_gpio_mode(GPIO112_MMCCMD_MD);
pxa_gpio_mode(GPIO92_MMCDAT0_MD);
pxa_gpio_mode(GPIO109_MMCDAT1_MD);
pxa_gpio_mode(GPIO110_MMCDAT2_MD);
pxa_gpio_mode(GPIO111_MMCDAT3_MD);
pxa_gpio_mode(GPIO_MMC_DET | GPIO_IN);
err = request_irq(TRIZEPS4_MMC_IRQ, mci_detect_int, SA_INTERRUPT | SA_TRIGGER_RISING, "MMC card detect", data);
if (err) {
printk(KERN_ERR "trizeps4_mci_init: MMC/SD: can't request MMC card detect IRQ\n");
return -1;
}
return 0;
}
static void trizeps4_mci_exit(struct device *dev, void *data)
{
free_irq(TRIZEPS4_MMC_IRQ, data);
}
static struct pxamci_platform_data trizeps4_mci_platform_data = {
.ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
.init = trizeps4_mci_init,
.exit = trizeps4_mci_exit,
.setpower = board_mci_power,
};
static struct pxaficp_platform_data trizeps4_ficp_platform_data = {
.transceiver_cap = IR_SIRMODE | IR_FIRMODE | IR_OFF,
.transceiver_mode = board_irda_mode,
};
static int trizeps4_ohci_init(struct device *dev)
{
/* setup Port1 GPIO pin. */
pxa_gpio_mode( 88 | GPIO_ALT_FN_1_IN); /* USBHPWR1 */
pxa_gpio_mode( 89 | GPIO_ALT_FN_2_OUT); /* USBHPEN1 */
/* Set the Power Control Polarity Low and Power Sense
Polarity Low to active low. */
UHCHR = (UHCHR | UHCHR_PCPL | UHCHR_PSPL) &
~(UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSEP3 | UHCHR_SSE);
return 0;
}
static void trizeps4_ohci_exit(struct device *dev)
{
;
}
static struct pxaohci_platform_data trizeps4_ohci_platform_data = {
.port_mode = PMM_PERPORT_MODE,
.init = trizeps4_ohci_init,
.exit = trizeps4_ohci_exit,
};
static struct map_desc trizeps4_io_desc[] __initdata = {
{ /* ConXS CFSR */
.virtual = TRIZEPS4_CFSR_VIRT,
.pfn = __phys_to_pfn(TRIZEPS4_CFSR_PHYS),
.length = 0x00001000,
.type = MT_DEVICE
},
{ /* ConXS BCR */
.virtual = TRIZEPS4_BOCR_VIRT,
.pfn = __phys_to_pfn(TRIZEPS4_BOCR_PHYS),
.length = 0x00001000,
.type = MT_DEVICE
},
{ /* ConXS IRCR */
.virtual = TRIZEPS4_IRCR_VIRT,
.pfn = __phys_to_pfn(TRIZEPS4_IRCR_PHYS),
.length = 0x00001000,
.type = MT_DEVICE
},
{ /* ConXS DCR */
.virtual = TRIZEPS4_DICR_VIRT,
.pfn = __phys_to_pfn(TRIZEPS4_DICR_PHYS),
.length = 0x00001000,
.type = MT_DEVICE
},
{ /* ConXS UPSR */
.virtual = TRIZEPS4_UPSR_VIRT,
.pfn = __phys_to_pfn(TRIZEPS4_UPSR_PHYS),
.length = 0x00001000,
.type = MT_DEVICE
}
};
static struct pxafb_mach_info sharp_lcd __initdata = {
.pixclock = 78000,
.xres = 640,
.yres = 480,
.bpp = 8,
.hsync_len = 4,
.left_margin = 4,
.right_margin = 4,
.vsync_len = 2,
.upper_margin = 0,
.lower_margin = 0,
.sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
.cmap_greyscale = 0,
.cmap_inverse = 0,
.cmap_static = 0,
.lccr0 = LCCR0_Color | LCCR0_Pas | LCCR0_Dual,
.lccr3 = 0x0340ff02,
.pxafb_backlight_power = board_backlight_power,
};
static void __init trizeps4_fixup(struct machine_desc *desc, struct tag *tags, char **cmdline, struct meminfo *mi)
{
}
static void __init trizeps4_init(void)
{
platform_add_devices(trizeps4_devices, ARRAY_SIZE(trizeps4_devices));
set_pxa_fb_info(&sharp_lcd);
pxa_set_mci_info(&trizeps4_mci_platform_data);
pxa_set_ficp_info(&trizeps4_ficp_platform_data);
pxa_set_ohci_info(&trizeps4_ohci_platform_data);
}
static void __init trizeps4_map_io(void)
{
pxa_map_io();
iotable_init(trizeps4_io_desc, ARRAY_SIZE(trizeps4_io_desc));
/* for DiskOnChip */
pxa_gpio_mode(GPIO15_nCS_1_MD);
/* for off-module PIC on ConXS board */
pxa_gpio_mode(GPIO_PIC | GPIO_IN);
/* UCB1400 irq */
pxa_gpio_mode(GPIO_UCB1400 | GPIO_IN);
/* for DM9000 LAN */
pxa_gpio_mode(GPIO78_nCS_2_MD);
pxa_gpio_mode(GPIO_DM9000 | GPIO_IN);
/* for PCMCIA device */
pxa_gpio_mode(GPIO_PCD | GPIO_IN);
pxa_gpio_mode(GPIO_PRDY | GPIO_IN);
/* for I2C adapter */
pxa_gpio_mode(GPIO117_I2CSCL_MD);
pxa_gpio_mode(GPIO118_I2CSDA_MD);
/* MMC_DET s.o. */
pxa_gpio_mode(GPIO_MMC_DET | GPIO_IN);
/* whats that for ??? */
pxa_gpio_mode(GPIO79_nCS_3_MD);
pxa_gpio_mode( GPIO_SYS_BUSY_LED | GPIO_OUT); /* LED1 */
pxa_gpio_mode( GPIO_HEARTBEAT_LED | GPIO_OUT); /* LED2 */
#ifdef CONFIG_MACH_TRIZEPS4_CONXS
#ifdef CONFIG_IDE_PXA_CF
/* if boot direct from compact flash dont disable power */
trizeps_conxs_bcr = 0x0009;
#else
/* this is the reset value */
trizeps_conxs_bcr = 0x00A0;
#endif
ConXS_BCR = trizeps_conxs_bcr;
#endif
PWER = 0x00000002;
PFER = 0x00000000;
PRER = 0x00000002;
PGSR0 = 0x0158C000;
PGSR1 = 0x00FF0080;
PGSR2 = 0x0001C004;
/* Stop 3.6MHz and drive HIGH to PCMCIA and CS */
PCFR |= PCFR_OPDE;
}
MACHINE_START(TRIZEPS4, "Keith und Koep Trizeps IV module")
/* MAINTAINER("Jürgen Schindele") */
.phys_io = 0x40000000,
.io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
.boot_params = TRIZEPS4_SDRAM_BASE + 0x100,
.fixup = trizeps4_fixup,
.init_machine = trizeps4_init,
.map_io = trizeps4_map_io,
.init_irq = pxa_init_irq,
.timer = &pxa_timer,
MACHINE_END

131
arch/arm/mach-sa1100/cpu-sa1110.c
View File

@ -15,7 +15,10 @@
* SDRAM reads (rev A0, B0, B1) * SDRAM reads (rev A0, B0, B1)
* *
* We ignore rev. A0 and B0 devices; I don't think they're worth supporting. * We ignore rev. A0 and B0 devices; I don't think they're worth supporting.
*
* The SDRAM type can be passed on the command line as cpu_sa1110.sdram=type
*/ */
#include <linux/moduleparam.h>
#include <linux/types.h> #include <linux/types.h>
#include <linux/kernel.h> #include <linux/kernel.h>
#include <linux/sched.h> #include <linux/sched.h>
@ -35,6 +38,7 @@
static struct cpufreq_driver sa1110_driver; static struct cpufreq_driver sa1110_driver;
struct sdram_params { struct sdram_params {
const char name[16];
u_char rows; /* bits */ u_char rows; /* bits */
u_char cas_latency; /* cycles */ u_char cas_latency; /* cycles */
u_char tck; /* clock cycle time (ns) */ u_char tck; /* clock cycle time (ns) */
@ -50,54 +54,53 @@ struct sdram_info {
u_int mdcas[3]; u_int mdcas[3];
}; };
static struct sdram_params tc59sm716_cl2_params __initdata = { static struct sdram_params sdram_tbl[] __initdata = {
.rows = 12, { /* Toshiba TC59SM716 CL2 */
.tck = 10, .name = "TC59SM716-CL2",
.trcd = 20, .rows = 12,
.trp = 20, .tck = 10,
.twr = 10, .trcd = 20,
.refresh = 64000, .trp = 20,
.cas_latency = 2, .twr = 10,
}; .refresh = 64000,
.cas_latency = 2,
static struct sdram_params tc59sm716_cl3_params __initdata = { }, { /* Toshiba TC59SM716 CL3 */
.rows = 12, .name = "TC59SM716-CL3",
.tck = 8, .rows = 12,
.trcd = 20, .tck = 8,
.trp = 20, .trcd = 20,
.twr = 8, .trp = 20,
.refresh = 64000, .twr = 8,
.cas_latency = 3, .refresh = 64000,
}; .cas_latency = 3,
}, { /* Samsung K4S641632D TC75 */
static struct sdram_params samsung_k4s641632d_tc75 __initdata = { .name = "K4S641632D",
.rows = 14, .rows = 14,
.tck = 9, .tck = 9,
.trcd = 27, .trcd = 27,
.trp = 20, .trp = 20,
.twr = 9, .twr = 9,
.refresh = 64000, .refresh = 64000,
.cas_latency = 3, .cas_latency = 3,
}; }, { /* Samsung KM416S4030CT */
.name = "KM416S4030CT",
static struct sdram_params samsung_km416s4030ct __initdata = { .rows = 13,
.rows = 13, .tck = 8,
.tck = 8, .trcd = 24, /* 3 CLKs */
.trcd = 24, /* 3 CLKs */ .trp = 24, /* 3 CLKs */
.trp = 24, /* 3 CLKs */ .twr = 16, /* Trdl: 2 CLKs */
.twr = 16, /* Trdl: 2 CLKs */ .refresh = 64000,
.refresh = 64000, .cas_latency = 3,
.cas_latency = 3, }, { /* Winbond W982516AH75L CL3 */
}; .name = "W982516AH75L",
.rows = 16,
static struct sdram_params wbond_w982516ah75l_cl3_params __initdata = { .tck = 8,
.rows = 16, .trcd = 20,
.tck = 8, .trp = 20,
.trcd = 20, .twr = 8,
.trp = 20, .refresh = 64000,
.twr = 8, .cas_latency = 3,
.refresh = 64000, },
.cas_latency = 3,
}; };
static struct sdram_params sdram_params; static struct sdram_params sdram_params;
@ -336,19 +339,36 @@ static struct cpufreq_driver sa1110_driver = {
.name = "sa1110", .name = "sa1110",
}; };
static struct sdram_params *sa1110_find_sdram(const char *name)
{
struct sdram_params *sdram;
for (sdram = sdram_tbl; sdram < sdram_tbl + ARRAY_SIZE(sdram_tbl); sdram++)
if (strcmp(name, sdram->name) == 0)
return sdram;
return NULL;
}
static char sdram_name[16];
static int __init sa1110_clk_init(void) static int __init sa1110_clk_init(void)
{ {
struct sdram_params *sdram = NULL; struct sdram_params *sdram;
const char *name = sdram_name;
if (machine_is_assabet()) if (!name[0]) {
sdram = &tc59sm716_cl3_params; if (machine_is_assabet())
name = "TC59SM716-CL3";
if (machine_is_pt_system3()) if (machine_is_pt_system3())
sdram = &samsung_k4s641632d_tc75; name = "K4S641632D";
if (machine_is_h3100()) if (machine_is_h3100())
sdram = &samsung_km416s4030ct; name = "KM416S4030CT";
}
sdram = sa1110_find_sdram(name);
if (sdram) { if (sdram) {
printk(KERN_DEBUG "SDRAM: tck: %d trcd: %d trp: %d" printk(KERN_DEBUG "SDRAM: tck: %d trcd: %d trp: %d"
" twr: %d refresh: %d cas_latency: %d\n", " twr: %d refresh: %d cas_latency: %d\n",
@ -363,4 +383,5 @@ static int __init sa1110_clk_init(void)
return 0; return 0;
} }
module_param_string(sdram, sdram_name, sizeof(sdram_name), 0);
arch_initcall(sa1110_clk_init); arch_initcall(sa1110_clk_init);

4
arch/arm/mm/Kconfig
View File

@ -121,8 +121,8 @@ config CPU_ARM925T
# ARM926T # ARM926T
config CPU_ARM926T config CPU_ARM926T
bool "Support ARM926T processor" bool "Support ARM926T processor"
depends on ARCH_INTEGRATOR || ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || MACH_REALVIEW_EB || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 depends on ARCH_INTEGRATOR || ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || MACH_REALVIEW_EB || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261
default y if ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 default y if ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261
select CPU_32v5 select CPU_32v5
select CPU_ABRT_EV5TJ select CPU_ABRT_EV5TJ
select CPU_CACHE_VIVT select CPU_CACHE_VIVT

227
arch/arm/mm/ioremap.c
View File

@ -27,7 +27,16 @@
#include <asm/cacheflush.h> #include <asm/cacheflush.h>
#include <asm/io.h> #include <asm/io.h>
#include <asm/mmu_context.h>
#include <asm/pgalloc.h>
#include <asm/tlbflush.h> #include <asm/tlbflush.h>
#include <asm/sizes.h>
/*
* Used by ioremap() and iounmap() code to mark (super)section-mapped
* I/O regions in vm_struct->flags field.
*/
#define VM_ARM_SECTION_MAPPING 0x80000000
static inline void static inline void
remap_area_pte(pte_t * pte, unsigned long address, unsigned long size, remap_area_pte(pte_t * pte, unsigned long address, unsigned long size,
@ -113,10 +122,168 @@ remap_area_pages(unsigned long start, unsigned long pfn,
dir++; dir++;
} while (address && (address < end)); } while (address && (address < end));
flush_cache_vmap(start, end);
return err; return err;
} }
void __check_kvm_seq(struct mm_struct *mm)
{
unsigned int seq;
do {
seq = init_mm.context.kvm_seq;
memcpy(pgd_offset(mm, VMALLOC_START),
pgd_offset_k(VMALLOC_START),
sizeof(pgd_t) * (pgd_index(VMALLOC_END) -
pgd_index(VMALLOC_START)));
mm->context.kvm_seq = seq;
} while (seq != init_mm.context.kvm_seq);
}
#ifndef CONFIG_SMP
/*
* Section support is unsafe on SMP - If you iounmap and ioremap a region,
* the other CPUs will not see this change until their next context switch.
* Meanwhile, (eg) if an interrupt comes in on one of those other CPUs
* which requires the new ioremap'd region to be referenced, the CPU will
* reference the _old_ region.
*
* Note that get_vm_area() allocates a guard 4K page, so we need to mask
* the size back to 1MB aligned or we will overflow in the loop below.
*/
static void unmap_area_sections(unsigned long virt, unsigned long size)
{
unsigned long addr = virt, end = virt + (size & ~SZ_1M);
pgd_t *pgd;
flush_cache_vunmap(addr, end);
pgd = pgd_offset_k(addr);
do {
pmd_t pmd, *pmdp = pmd_offset(pgd, addr);
pmd = *pmdp;
if (!pmd_none(pmd)) {
/*
* Clear the PMD from the page table, and
* increment the kvm sequence so others
* notice this change.
*
* Note: this is still racy on SMP machines.
*/
pmd_clear(pmdp);
init_mm.context.kvm_seq++;
/*
* Free the page table, if there was one.
*/
if ((pmd_val(pmd) & PMD_TYPE_MASK) == PMD_TYPE_TABLE)
pte_free_kernel(pmd_page_kernel(pmd));
}
addr += PGDIR_SIZE;
pgd++;
} while (addr < end);
/*
* Ensure that the active_mm is up to date - we want to
* catch any use-after-iounmap cases.
*/
if (current->active_mm->context.kvm_seq != init_mm.context.kvm_seq)
__check_kvm_seq(current->active_mm);
flush_tlb_kernel_range(virt, end);
}
static int
remap_area_sections(unsigned long virt, unsigned long pfn,
unsigned long size, unsigned long flags)
{
unsigned long prot, addr = virt, end = virt + size;
pgd_t *pgd;
/*
* Remove and free any PTE-based mapping, and
* sync the current kernel mapping.
*/
unmap_area_sections(virt, size);
prot = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_DOMAIN(DOMAIN_IO) |
(flags & (L_PTE_CACHEABLE | L_PTE_BUFFERABLE));
/*
* ARMv6 and above need XN set to prevent speculative prefetches
* hitting IO.
*/
if (cpu_architecture() >= CPU_ARCH_ARMv6)
prot |= PMD_SECT_XN;
pgd = pgd_offset_k(addr);
do {
pmd_t *pmd = pmd_offset(pgd, addr);
pmd[0] = __pmd(__pfn_to_phys(pfn) | prot);
pfn += SZ_1M >> PAGE_SHIFT;
pmd[1] = __pmd(__pfn_to_phys(pfn) | prot);
pfn += SZ_1M >> PAGE_SHIFT;
flush_pmd_entry(pmd);
addr += PGDIR_SIZE;
pgd++;
} while (addr < end);
return 0;
}
static int
remap_area_supersections(unsigned long virt, unsigned long pfn,
unsigned long size, unsigned long flags)
{
unsigned long prot, addr = virt, end = virt + size;
pgd_t *pgd;
/*
* Remove and free any PTE-based mapping, and
* sync the current kernel mapping.
*/
unmap_area_sections(virt, size);
prot = PMD_TYPE_SECT | PMD_SECT_SUPER | PMD_SECT_AP_WRITE |
PMD_DOMAIN(DOMAIN_IO) |
(flags & (L_PTE_CACHEABLE | L_PTE_BUFFERABLE));
/*
* ARMv6 and above need XN set to prevent speculative prefetches
* hitting IO.
*/
if (cpu_architecture() >= CPU_ARCH_ARMv6)
prot |= PMD_SECT_XN;
pgd = pgd_offset_k(virt);
do {
unsigned long super_pmd_val, i;
super_pmd_val = __pfn_to_phys(pfn) | prot;
super_pmd_val |= ((pfn >> (32 - PAGE_SHIFT)) & 0xf) << 20;
for (i = 0; i < 8; i++) {
pmd_t *pmd = pmd_offset(pgd, addr);
pmd[0] = __pmd(super_pmd_val);
pmd[1] = __pmd(super_pmd_val);
flush_pmd_entry(pmd);
addr += PGDIR_SIZE;
pgd++;
}
pfn += SUPERSECTION_SIZE >> PAGE_SHIFT;
} while (addr < end);
return 0;
}
#endif
/* /*
* Remap an arbitrary physical address space into the kernel virtual * Remap an arbitrary physical address space into the kernel virtual
* address space. Needed when the kernel wants to access high addresses * address space. Needed when the kernel wants to access high addresses
@ -133,18 +300,42 @@ void __iomem *
__ioremap_pfn(unsigned long pfn, unsigned long offset, size_t size, __ioremap_pfn(unsigned long pfn, unsigned long offset, size_t size,
unsigned long flags) unsigned long flags)
{ {
int err;
unsigned long addr; unsigned long addr;
struct vm_struct * area; struct vm_struct * area;
unsigned int cr = get_cr();
/*
* High mappings must be supersection aligned
*/
if (pfn >= 0x100000 && (__pfn_to_phys(pfn) & ~SUPERSECTION_MASK))
return NULL;
area = get_vm_area(size, VM_IOREMAP); area = get_vm_area(size, VM_IOREMAP);
if (!area) if (!area)
return NULL; return NULL;
addr = (unsigned long)area->addr; addr = (unsigned long)area->addr;
if (remap_area_pages(addr, pfn, size, flags)) {
#ifndef CONFIG_SMP
if ((((cpu_architecture() >= CPU_ARCH_ARMv6) && (cr & CR_XP)) ||
cpu_is_xsc3()) &&
!((__pfn_to_phys(pfn) | size | addr) & ~SUPERSECTION_MASK)) {
area->flags |= VM_ARM_SECTION_MAPPING;
err = remap_area_supersections(addr, pfn, size, flags);
} else if (!((__pfn_to_phys(pfn) | size | addr) & ~PMD_MASK)) {
area->flags |= VM_ARM_SECTION_MAPPING;
err = remap_area_sections(addr, pfn, size, flags);
} else
#endif
err = remap_area_pages(addr, pfn, size, flags);
if (err) {
vunmap((void *)addr); vunmap((void *)addr);
return NULL; return NULL;
} }
return (void __iomem *) (offset + (char *)addr);
flush_cache_vmap(addr, addr + size);
return (void __iomem *) (offset + addr);
} }
EXPORT_SYMBOL(__ioremap_pfn); EXPORT_SYMBOL(__ioremap_pfn);
@ -173,6 +364,34 @@ EXPORT_SYMBOL(__ioremap);
void __iounmap(void __iomem *addr) void __iounmap(void __iomem *addr)
{ {
vunmap((void *)(PAGE_MASK & (unsigned long)addr)); struct vm_struct **p, *tmp;
unsigned int section_mapping = 0;
addr = (void __iomem *)(PAGE_MASK & (unsigned long)addr);
/*
* If this is a section based mapping we need to handle it
* specially as the VM subysystem does not know how to handle
* such a beast. We need the lock here b/c we need to clear
* all the mappings before the area can be reclaimed
* by someone else.
*/
write_lock(&vmlist_lock);
for (p = &vmlist ; (tmp = *p) ; p = &tmp->next) {
if((tmp->flags & VM_IOREMAP) && (tmp->addr == addr)) {
if (tmp->flags & VM_ARM_SECTION_MAPPING) {
*p = tmp->next;
unmap_area_sections((unsigned long)tmp->addr,
tmp->size);
kfree(tmp);
section_mapping = 1;
}
break;
}
}
write_unlock(&vmlist_lock);
if (!section_mapping)
vunmap(addr);
} }
EXPORT_SYMBOL(__iounmap); EXPORT_SYMBOL(__iounmap);

37
arch/arm/mm/mm-armv.c
View File

@ -302,16 +302,16 @@ static struct mem_types mem_types[] __initdata = {
.prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
L_PTE_WRITE, L_PTE_WRITE,
.prot_l1 = PMD_TYPE_TABLE, .prot_l1 = PMD_TYPE_TABLE,
.prot_sect = PMD_TYPE_SECT | PMD_SECT_UNCACHED | .prot_sect = PMD_TYPE_SECT | PMD_BIT4 | PMD_SECT_UNCACHED |
PMD_SECT_AP_WRITE, PMD_SECT_AP_WRITE,
.domain = DOMAIN_IO, .domain = DOMAIN_IO,
}, },
[MT_CACHECLEAN] = { [MT_CACHECLEAN] = {
.prot_sect = PMD_TYPE_SECT, .prot_sect = PMD_TYPE_SECT | PMD_BIT4,
.domain = DOMAIN_KERNEL, .domain = DOMAIN_KERNEL,
}, },
[MT_MINICLEAN] = { [MT_MINICLEAN] = {
.prot_sect = PMD_TYPE_SECT | PMD_SECT_MINICACHE, .prot_sect = PMD_TYPE_SECT | PMD_BIT4 | PMD_SECT_MINICACHE,
.domain = DOMAIN_KERNEL, .domain = DOMAIN_KERNEL,
}, },
[MT_LOW_VECTORS] = { [MT_LOW_VECTORS] = {
@ -327,25 +327,25 @@ static struct mem_types mem_types[] __initdata = {
.domain = DOMAIN_USER, .domain = DOMAIN_USER,
}, },
[MT_MEMORY] = { [MT_MEMORY] = {
.prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE, .prot_sect = PMD_TYPE_SECT | PMD_BIT4 | PMD_SECT_AP_WRITE,
.domain = DOMAIN_KERNEL, .domain = DOMAIN_KERNEL,
}, },
[MT_ROM] = { [MT_ROM] = {
.prot_sect = PMD_TYPE_SECT, .prot_sect = PMD_TYPE_SECT | PMD_BIT4,
.domain = DOMAIN_KERNEL, .domain = DOMAIN_KERNEL,
}, },
[MT_IXP2000_DEVICE] = { /* IXP2400 requires XCB=101 for on-chip I/O */ [MT_IXP2000_DEVICE] = { /* IXP2400 requires XCB=101 for on-chip I/O */
.prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
L_PTE_WRITE, L_PTE_WRITE,
.prot_l1 = PMD_TYPE_TABLE, .prot_l1 = PMD_TYPE_TABLE,
.prot_sect = PMD_TYPE_SECT | PMD_SECT_UNCACHED | .prot_sect = PMD_TYPE_SECT | PMD_BIT4 | PMD_SECT_UNCACHED |
PMD_SECT_AP_WRITE | PMD_SECT_BUFFERABLE | PMD_SECT_AP_WRITE | PMD_SECT_BUFFERABLE |
PMD_SECT_TEX(1), PMD_SECT_TEX(1),
.domain = DOMAIN_IO, .domain = DOMAIN_IO,
}, },
[MT_NONSHARED_DEVICE] = { [MT_NONSHARED_DEVICE] = {
.prot_l1 = PMD_TYPE_TABLE, .prot_l1 = PMD_TYPE_TABLE,
.prot_sect = PMD_TYPE_SECT | PMD_SECT_NONSHARED_DEV | .prot_sect = PMD_TYPE_SECT | PMD_BIT4 | PMD_SECT_NONSHARED_DEV |
PMD_SECT_AP_WRITE, PMD_SECT_AP_WRITE,
.domain = DOMAIN_IO, .domain = DOMAIN_IO,
} }
@ -375,14 +375,21 @@ void __init build_mem_type_table(void)
ecc_mask = 0; ecc_mask = 0;
} }
if (cpu_arch <= CPU_ARCH_ARMv5TEJ && !cpu_is_xscale()) { /*
for (i = 0; i < ARRAY_SIZE(mem_types); i++) { * Xscale must not have PMD bit 4 set for section mappings.
*/
if (cpu_is_xscale())
for (i = 0; i < ARRAY_SIZE(mem_types); i++)
mem_types[i].prot_sect &= ~PMD_BIT4;
/*
* ARMv5 and lower, excluding Xscale, bit 4 must be set for
* page tables.
*/
if (cpu_arch < CPU_ARCH_ARMv6 && !cpu_is_xscale())
for (i = 0; i < ARRAY_SIZE(mem_types); i++)
if (mem_types[i].prot_l1) if (mem_types[i].prot_l1)
mem_types[i].prot_l1 |= PMD_BIT4; mem_types[i].prot_l1 |= PMD_BIT4;
if (mem_types[i].prot_sect)
mem_types[i].prot_sect |= PMD_BIT4;
}
}
cp = &cache_policies[cachepolicy]; cp = &cache_policies[cachepolicy];
kern_pgprot = user_pgprot = cp->pte; kern_pgprot = user_pgprot = cp->pte;
@ -406,8 +413,8 @@ void __init build_mem_type_table(void)
* bit 4 becomes XN which we must clear for the * bit 4 becomes XN which we must clear for the
* kernel memory mapping. * kernel memory mapping.
*/ */
mem_types[MT_MEMORY].prot_sect &= ~PMD_BIT4; mem_types[MT_MEMORY].prot_sect &= ~PMD_SECT_XN;
mem_types[MT_ROM].prot_sect &= ~PMD_BIT4; mem_types[MT_ROM].prot_sect &= ~PMD_SECT_XN;
/* /*
* Mark cache clean areas and XIP ROM read only * Mark cache clean areas and XIP ROM read only

19
arch/arm/mm/proc-arm1020.S
View File

@ -439,11 +439,12 @@ __arm1020_setup:
#ifdef CONFIG_MMU #ifdef CONFIG_MMU
mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
#endif #endif
adr r5, arm1020_crval
ldmia r5, {r5, r6}
mrc p15, 0, r0, c1, c0 @ get control register v4 mrc p15, 0, r0, c1, c0 @ get control register v4
ldr r5, arm1020_cr1_clear
bic r0, r0, r5 bic r0, r0, r5
ldr r5, arm1020_cr1_set orr r0, r0, r6
orr r0, r0, r5
#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
orr r0, r0, #0x4000 @ .R.. .... .... .... orr r0, r0, #0x4000 @ .R.. .... .... ....
#endif #endif
@ -455,12 +456,9 @@ __arm1020_setup:
* .RVI ZFRS BLDP WCAM * .RVI ZFRS BLDP WCAM
* .011 1001 ..11 0101 * .011 1001 ..11 0101
*/ */
.type arm1020_cr1_clear, #object .type arm1020_crval, #object
.type arm1020_cr1_set, #object arm1020_crval:
arm1020_cr1_clear: crval clear=0x0000593f, mmuset=0x00003935, ucset=0x00001930
.word 0x593f
arm1020_cr1_set:
.word 0x3935
__INITDATA __INITDATA
@ -523,6 +521,9 @@ cpu_arm1020_name:
__arm1020_proc_info: __arm1020_proc_info:
.long 0x4104a200 @ ARM 1020T (Architecture v5T) .long 0x4104a200 @ ARM 1020T (Architecture v5T)
.long 0xff0ffff0 .long 0xff0ffff0
.long PMD_TYPE_SECT | \
PMD_SECT_AP_WRITE | \
PMD_SECT_AP_READ
.long PMD_TYPE_SECT | \ .long PMD_TYPE_SECT | \
PMD_SECT_AP_WRITE | \ PMD_SECT_AP_WRITE | \
PMD_SECT_AP_READ PMD_SECT_AP_READ

39
arch/arm/mm/proc-arm1020e.S
View File

@ -421,11 +421,11 @@ __arm1020e_setup:
#ifdef CONFIG_MMU #ifdef CONFIG_MMU
mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
#endif #endif
adr r5, arm1020e_crval
ldmia r5, {r5, r6}
mrc p15, 0, r0, c1, c0 @ get control register v4 mrc p15, 0, r0, c1, c0 @ get control register v4
ldr r5, arm1020e_cr1_clear
bic r0, r0, r5 bic r0, r0, r5
ldr r5, arm1020e_cr1_set orr r0, r0, r6
orr r0, r0, r5
#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
orr r0, r0, #0x4000 @ .R.. .... .... .... orr r0, r0, #0x4000 @ .R.. .... .... ....
#endif #endif
@ -437,12 +437,9 @@ __arm1020e_setup:
* .RVI ZFRS BLDP WCAM * .RVI ZFRS BLDP WCAM
* .011 1001 ..11 0101 * .011 1001 ..11 0101
*/ */
.type arm1020e_cr1_clear, #object .type arm1020e_crval, #object
.type arm1020e_cr1_set, #object arm1020e_crval:
arm1020e_cr1_clear: crval clear=0x00007f3f, mmuset=0x00003935, ucset=0x00001930
.word 0x5f3f
arm1020e_cr1_set:
.word 0x3935
__INITDATA __INITDATA
@ -476,25 +473,7 @@ cpu_elf_name:
.type cpu_arm1020e_name, #object .type cpu_arm1020e_name, #object
cpu_arm1020e_name: cpu_arm1020e_name:
.ascii "ARM1020E" .asciz "ARM1020E"
#ifndef CONFIG_CPU_ICACHE_DISABLE
.ascii "i"
#endif
#ifndef CONFIG_CPU_DCACHE_DISABLE
.ascii "d"
#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
.ascii "(wt)"
#else
.ascii "(wb)"
#endif
#endif
#ifndef CONFIG_CPU_BPREDICT_DISABLE
.ascii "B"
#endif
#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
.ascii "RR"
#endif
.ascii "\0"
.size cpu_arm1020e_name, . - cpu_arm1020e_name .size cpu_arm1020e_name, . - cpu_arm1020e_name
.align .align
@ -505,6 +484,10 @@ cpu_arm1020e_name:
__arm1020e_proc_info: __arm1020e_proc_info:
.long 0x4105a200 @ ARM 1020TE (Architecture v5TE) .long 0x4105a200 @ ARM 1020TE (Architecture v5TE)
.long 0xff0ffff0 .long 0xff0ffff0
.long PMD_TYPE_SECT | \
PMD_BIT4 | \
PMD_SECT_AP_WRITE | \
PMD_SECT_AP_READ
.long PMD_TYPE_SECT | \ .long PMD_TYPE_SECT | \
PMD_BIT4 | \ PMD_BIT4 | \
PMD_SECT_AP_WRITE | \ PMD_SECT_AP_WRITE | \

39
arch/arm/mm/proc-arm1022.S
View File

@ -403,11 +403,11 @@ __arm1022_setup:
#ifdef CONFIG_MMU #ifdef CONFIG_MMU
mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
#endif #endif
adr r5, arm1022_crval
ldmia r5, {r5, r6}
mrc p15, 0, r0, c1, c0 @ get control register v4 mrc p15, 0, r0, c1, c0 @ get control register v4
ldr r5, arm1022_cr1_clear
bic r0, r0, r5 bic r0, r0, r5
ldr r5, arm1022_cr1_set orr r0, r0, r6
orr r0, r0, r5
#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
orr r0, r0, #0x4000 @ .R.............. orr r0, r0, #0x4000 @ .R..............
#endif #endif
@ -420,12 +420,9 @@ __arm1022_setup:
* .011 1001 ..11 0101 * .011 1001 ..11 0101
* *
*/ */
.type arm1022_cr1_clear, #object .type arm1022_crval, #object
.type arm1022_cr1_set, #object arm1022_crval:
arm1022_cr1_clear: crval clear=0x00007f3f, mmuset=0x00003935, ucset=0x00001930
.word 0x7f3f
arm1022_cr1_set:
.word 0x3935
__INITDATA __INITDATA
@ -459,25 +456,7 @@ cpu_elf_name:
.type cpu_arm1022_name, #object .type cpu_arm1022_name, #object
cpu_arm1022_name: cpu_arm1022_name:
.ascii "arm1022" .asciz "ARM1022"
#ifndef CONFIG_CPU_ICACHE_DISABLE
.ascii "i"
#endif
#ifndef CONFIG_CPU_DCACHE_DISABLE
.ascii "d"
#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
.ascii "(wt)"
#else
.ascii "(wb)"
#endif
#endif
#ifndef CONFIG_CPU_BPREDICT_DISABLE
.ascii "B"
#endif
#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
.ascii "RR"
#endif
.ascii "\0"
.size cpu_arm1022_name, . - cpu_arm1022_name .size cpu_arm1022_name, . - cpu_arm1022_name
.align .align
@ -488,6 +467,10 @@ cpu_arm1022_name:
__arm1022_proc_info: __arm1022_proc_info:
.long 0x4105a220 @ ARM 1022E (v5TE) .long 0x4105a220 @ ARM 1022E (v5TE)
.long 0xff0ffff0 .long 0xff0ffff0
.long PMD_TYPE_SECT | \
PMD_BIT4 | \
PMD_SECT_AP_WRITE | \
PMD_SECT_AP_READ
.long PMD_TYPE_SECT | \ .long PMD_TYPE_SECT | \
PMD_BIT4 | \ PMD_BIT4 | \
PMD_SECT_AP_WRITE | \ PMD_SECT_AP_WRITE | \

39
arch/arm/mm/proc-arm1026.S
View File

@ -398,11 +398,11 @@ __arm1026_setup:
mov r0, #4 @ explicitly disable writeback mov r0, #4 @ explicitly disable writeback
mcr p15, 7, r0, c15, c0, 0 mcr p15, 7, r0, c15, c0, 0
#endif #endif
adr r5, arm1026_crval
ldmia r5, {r5, r6}
mrc p15, 0, r0, c1, c0 @ get control register v4 mrc p15, 0, r0, c1, c0 @ get control register v4
ldr r5, arm1026_cr1_clear
bic r0, r0, r5 bic r0, r0, r5
ldr r5, arm1026_cr1_set orr r0, r0, r6
orr r0, r0, r5
#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
orr r0, r0, #0x4000 @ .R.. .... .... .... orr r0, r0, #0x4000 @ .R.. .... .... ....
#endif #endif
@ -415,12 +415,9 @@ __arm1026_setup:
* .011 1001 ..11 0101 * .011 1001 ..11 0101
* *
*/ */
.type arm1026_cr1_clear, #object .type arm1026_crval, #object
.type arm1026_cr1_set, #object arm1026_crval:
arm1026_cr1_clear: crval clear=0x00007f3f, mmuset=0x00003935, ucset=0x00001934
.word 0x7f3f
arm1026_cr1_set:
.word 0x3935
__INITDATA __INITDATA
@ -455,25 +452,7 @@ cpu_elf_name:
.type cpu_arm1026_name, #object .type cpu_arm1026_name, #object
cpu_arm1026_name: cpu_arm1026_name:
.ascii "ARM1026EJ-S" .asciz "ARM1026EJ-S"
#ifndef CONFIG_CPU_ICACHE_DISABLE
.ascii "i"
#endif
#ifndef CONFIG_CPU_DCACHE_DISABLE
.ascii "d"
#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
.ascii "(wt)"
#else
.ascii "(wb)"
#endif
#endif
#ifndef CONFIG_CPU_BPREDICT_DISABLE
.ascii "B"
#endif
#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
.ascii "RR"
#endif
.ascii "\0"
.size cpu_arm1026_name, . - cpu_arm1026_name .size cpu_arm1026_name, . - cpu_arm1026_name
.align .align
@ -484,6 +463,10 @@ cpu_arm1026_name:
__arm1026_proc_info: __arm1026_proc_info:
.long 0x4106a260 @ ARM 1026EJ-S (v5TEJ) .long 0x4106a260 @ ARM 1026EJ-S (v5TEJ)
.long 0xff0ffff0 .long 0xff0ffff0
.long PMD_TYPE_SECT | \
PMD_BIT4 | \
PMD_SECT_AP_WRITE | \
PMD_SECT_AP_READ
.long PMD_TYPE_SECT | \ .long PMD_TYPE_SECT | \
PMD_BIT4 | \ PMD_BIT4 | \
PMD_SECT_AP_WRITE | \ PMD_SECT_AP_WRITE | \

16
arch/arm/mm/proc-arm6_7.S
View File

@ -355,6 +355,10 @@ __arm6_proc_info:
.long 0x41560600 .long 0x41560600
.long 0xfffffff0 .long 0xfffffff0
.long 0x00000c1e .long 0x00000c1e
.long PMD_TYPE_SECT | \
PMD_BIT4 | \
PMD_SECT_AP_WRITE | \
PMD_SECT_AP_READ
b __arm6_setup b __arm6_setup
.long cpu_arch_name .long cpu_arch_name
.long cpu_elf_name .long cpu_elf_name
@ -371,6 +375,10 @@ __arm610_proc_info:
.long 0x41560610 .long 0x41560610
.long 0xfffffff0 .long 0xfffffff0
.long 0x00000c1e .long 0x00000c1e
.long PMD_TYPE_SECT | \
PMD_BIT4 | \
PMD_SECT_AP_WRITE | \
PMD_SECT_AP_READ
b __arm6_setup b __arm6_setup
.long cpu_arch_name .long cpu_arch_name
.long cpu_elf_name .long cpu_elf_name
@ -387,6 +395,10 @@ __arm7_proc_info:
.long 0x41007000 .long 0x41007000
.long 0xffffff00 .long 0xffffff00
.long 0x00000c1e .long 0x00000c1e
.long PMD_TYPE_SECT | \
PMD_BIT4 | \
PMD_SECT_AP_WRITE | \
PMD_SECT_AP_READ
b __arm7_setup b __arm7_setup
.long cpu_arch_name .long cpu_arch_name
.long cpu_elf_name .long cpu_elf_name
@ -408,6 +420,10 @@ __arm710_proc_info:
PMD_BIT4 | \ PMD_BIT4 | \
PMD_SECT_AP_WRITE | \ PMD_SECT_AP_WRITE | \
PMD_SECT_AP_READ PMD_SECT_AP_READ
.long PMD_TYPE_SECT | \
PMD_BIT4 | \
PMD_SECT_AP_WRITE | \
PMD_SECT_AP_READ
b __arm7_setup b __arm7_setup
.long cpu_arch_name .long cpu_arch_name
.long cpu_elf_name .long cpu_elf_name

23
arch/arm/mm/proc-arm720.S
View File

@ -169,11 +169,11 @@ __arm720_setup:
#ifdef CONFIG_MMU #ifdef CONFIG_MMU
mcr p15, 0, r0, c8, c7, 0 @ flush TLB (v4) mcr p15, 0, r0, c8, c7, 0 @ flush TLB (v4)
#endif #endif
adr r5, arm720_crval
ldmia r5, {r5, r6}
mrc p15, 0, r0, c1, c0 @ get control register mrc p15, 0, r0, c1, c0 @ get control register
ldr r5, arm720_cr1_clear
bic r0, r0, r5 bic r0, r0, r5
ldr r5, arm720_cr1_set orr r0, r0, r6
orr r0, r0, r5
mov pc, lr @ __ret (head.S) mov pc, lr @ __ret (head.S)
.size __arm720_setup, . - __arm720_setup .size __arm720_setup, . - __arm720_setup
@ -183,12 +183,9 @@ __arm720_setup:
* ..1. 1001 ..11 1101 * ..1. 1001 ..11 1101
* *
*/ */
.type arm720_cr1_clear, #object .type arm720_crval, #object
.type arm720_cr1_set, #object arm720_crval:
arm720_cr1_clear: crval clear=0x00002f3f, mmuset=0x0000213d, ucset=0x00000130
.word 0x2f3f
arm720_cr1_set:
.word 0x213d
__INITDATA __INITDATA
@ -246,6 +243,10 @@ __arm710_proc_info:
PMD_BIT4 | \ PMD_BIT4 | \
PMD_SECT_AP_WRITE | \ PMD_SECT_AP_WRITE | \
PMD_SECT_AP_READ PMD_SECT_AP_READ
.long PMD_TYPE_SECT | \
PMD_BIT4 | \
PMD_SECT_AP_WRITE | \
PMD_SECT_AP_READ
b __arm710_setup @ cpu_flush b __arm710_setup @ cpu_flush
.long cpu_arch_name @ arch_name .long cpu_arch_name @ arch_name
.long cpu_elf_name @ elf_name .long cpu_elf_name @ elf_name
@ -267,6 +268,10 @@ __arm720_proc_info:
PMD_BIT4 | \ PMD_BIT4 | \
PMD_SECT_AP_WRITE | \ PMD_SECT_AP_WRITE | \
PMD_SECT_AP_READ PMD_SECT_AP_READ
.long PMD_TYPE_SECT | \
PMD_BIT4 | \
PMD_SECT_AP_WRITE | \
PMD_SECT_AP_READ
b __arm720_setup @ cpu_flush b __arm720_setup @ cpu_flush
.long cpu_arch_name @ arch_name .long cpu_arch_name @ arch_name
.long cpu_elf_name @ elf_name .long cpu_elf_name @ elf_name

33
arch/arm/mm/proc-arm920.S
View File

@ -390,11 +390,11 @@ __arm920_setup:
#ifdef CONFIG_MMU #ifdef CONFIG_MMU
mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
#endif #endif
adr r5, arm920_crval
ldmia r5, {r5, r6}
mrc p15, 0, r0, c1, c0 @ get control register v4 mrc p15, 0, r0, c1, c0 @ get control register v4
ldr r5, arm920_cr1_clear
bic r0, r0, r5 bic r0, r0, r5
ldr r5, arm920_cr1_set orr r0, r0, r6
orr r0, r0, r5
mov pc, lr mov pc, lr
.size __arm920_setup, . - __arm920_setup .size __arm920_setup, . - __arm920_setup
@ -404,12 +404,9 @@ __arm920_setup:
* ..11 0001 ..11 0101 * ..11 0001 ..11 0101
* *
*/ */
.type arm920_cr1_clear, #object .type arm920_crval, #object
.type arm920_cr1_set, #object arm920_crval:
arm920_cr1_clear: crval clear=0x00003f3f, mmuset=0x00003135, ucset=0x00001130
.word 0x3f3f
arm920_cr1_set:
.word 0x3135
__INITDATA __INITDATA
@ -443,19 +440,7 @@ cpu_elf_name:
.type cpu_arm920_name, #object .type cpu_arm920_name, #object
cpu_arm920_name: cpu_arm920_name:
.ascii "ARM920T" .asciz "ARM920T"
#ifndef CONFIG_CPU_ICACHE_DISABLE
.ascii "i"
#endif
#ifndef CONFIG_CPU_DCACHE_DISABLE
.ascii "d"
#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
.ascii "(wt)"
#else
.ascii "(wb)"
#endif
#endif
.ascii "\0"
.size cpu_arm920_name, . - cpu_arm920_name .size cpu_arm920_name, . - cpu_arm920_name
.align .align
@ -472,6 +457,10 @@ __arm920_proc_info:
PMD_BIT4 | \ PMD_BIT4 | \
PMD_SECT_AP_WRITE | \ PMD_SECT_AP_WRITE | \
PMD_SECT_AP_READ PMD_SECT_AP_READ
.long PMD_TYPE_SECT | \
PMD_BIT4 | \
PMD_SECT_AP_WRITE | \
PMD_SECT_AP_READ
b __arm920_setup b __arm920_setup
.long cpu_arch_name .long cpu_arch_name
.long cpu_elf_name .long cpu_elf_name

33
arch/arm/mm/proc-arm922.S
View File

@ -394,11 +394,11 @@ __arm922_setup:
#ifdef CONFIG_MMU #ifdef CONFIG_MMU
mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
#endif #endif
adr r5, arm922_crval
ldmia r5, {r5, r6}
mrc p15, 0, r0, c1, c0 @ get control register v4 mrc p15, 0, r0, c1, c0 @ get control register v4
ldr r5, arm922_cr1_clear
bic r0, r0, r5 bic r0, r0, r5
ldr r5, arm922_cr1_set orr r0, r0, r6
orr r0, r0, r5
mov pc, lr mov pc, lr
.size __arm922_setup, . - __arm922_setup .size __arm922_setup, . - __arm922_setup
@ -408,12 +408,9 @@ __arm922_setup:
* ..11 0001 ..11 0101 * ..11 0001 ..11 0101
* *
*/ */
.type arm922_cr1_clear, #object .type arm922_crval, #object
.type arm922_cr1_set, #object arm922_crval:
arm922_cr1_clear: crval clear=0x00003f3f, mmuset=0x00003135, ucset=0x00001130
.word 0x3f3f
arm922_cr1_set:
.word 0x3135
__INITDATA __INITDATA
@ -447,19 +444,7 @@ cpu_elf_name:
.type cpu_arm922_name, #object .type cpu_arm922_name, #object
cpu_arm922_name: cpu_arm922_name:
.ascii "ARM922T" .asciz "ARM922T"
#ifndef CONFIG_CPU_ICACHE_DISABLE
.ascii "i"
#endif
#ifndef CONFIG_CPU_DCACHE_DISABLE
.ascii "d"
#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
.ascii "(wt)"
#else
.ascii "(wb)"
#endif
#endif
.ascii "\0"
.size cpu_arm922_name, . - cpu_arm922_name .size cpu_arm922_name, . - cpu_arm922_name
.align .align
@ -476,6 +461,10 @@ __arm922_proc_info:
PMD_BIT4 | \ PMD_BIT4 | \
PMD_SECT_AP_WRITE | \ PMD_SECT_AP_WRITE | \
PMD_SECT_AP_READ PMD_SECT_AP_READ
.long PMD_TYPE_SECT | \
PMD_BIT4 | \
PMD_SECT_AP_WRITE | \
PMD_SECT_AP_READ
b __arm922_setup b __arm922_setup
.long cpu_arch_name .long cpu_arch_name
.long cpu_elf_name .long cpu_elf_name

39
arch/arm/mm/proc-arm925.S
View File

@ -454,11 +454,10 @@ __arm925_setup:
mcr p15, 7, r0, c15, c0, 0 mcr p15, 7, r0, c15, c0, 0
#endif #endif
adr r5, {r5, r6}
mrc p15, 0, r0, c1, c0 @ get control register v4 mrc p15, 0, r0, c1, c0 @ get control register v4
ldr r5, arm925_cr1_clear
bic r0, r0, r5 bic r0, r0, r5
ldr r5, arm925_cr1_set orr r0, r0, r6
orr r0, r0, r5
#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
orr r0, r0, #0x4000 @ .1.. .... .... .... orr r0, r0, #0x4000 @ .1.. .... .... ....
#endif #endif
@ -471,12 +470,9 @@ __arm925_setup:
* .011 0001 ..11 1101 * .011 0001 ..11 1101
* *
*/ */
.type arm925_cr1_clear, #object .type arm925_crval, #object
.type arm925_cr1_set, #object arm925_crval:
arm925_cr1_clear: crval clear=0x00007f3f, mmuset=0x0000313d, ucset=0x00001130
.word 0x7f3f
arm925_cr1_set:
.word 0x313d
__INITDATA __INITDATA
@ -510,22 +506,7 @@ cpu_elf_name:
.type cpu_arm925_name, #object .type cpu_arm925_name, #object
cpu_arm925_name: cpu_arm925_name:
.ascii "ARM925T" .asciz "ARM925T"
#ifndef CONFIG_CPU_ICACHE_DISABLE
.ascii "i"
#endif
#ifndef CONFIG_CPU_DCACHE_DISABLE
.ascii "d"
#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
.ascii "(wt)"
#else
.ascii "(wb)"
#endif
#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
.ascii "RR"
#endif
#endif
.ascii "\0"
.size cpu_arm925_name, . - cpu_arm925_name .size cpu_arm925_name, . - cpu_arm925_name
.align .align
@ -536,6 +517,10 @@ cpu_arm925_name:
__arm925_proc_info: __arm925_proc_info:
.long 0x54029250 .long 0x54029250
.long 0xfffffff0 .long 0xfffffff0
.long PMD_TYPE_SECT | \
PMD_BIT4 | \
PMD_SECT_AP_WRITE | \
PMD_SECT_AP_READ
.long PMD_TYPE_SECT | \ .long PMD_TYPE_SECT | \
PMD_BIT4 | \ PMD_BIT4 | \
PMD_SECT_AP_WRITE | \ PMD_SECT_AP_WRITE | \
@ -555,6 +540,10 @@ __arm925_proc_info:
__arm915_proc_info: __arm915_proc_info:
.long 0x54029150 .long 0x54029150
.long 0xfffffff0 .long 0xfffffff0
.long PMD_TYPE_SECT | \
PMD_BIT4 | \
PMD_SECT_AP_WRITE | \
PMD_SECT_AP_READ
.long PMD_TYPE_SECT | \ .long PMD_TYPE_SECT | \
PMD_BIT4 | \ PMD_BIT4 | \
PMD_SECT_AP_WRITE | \ PMD_SECT_AP_WRITE | \

36
arch/arm/mm/proc-arm926.S
View File

@ -403,11 +403,11 @@ __arm926_setup:
mcr p15, 7, r0, c15, c0, 0 mcr p15, 7, r0, c15, c0, 0
#endif #endif
adr r5, arm926_crval
ldmia r5, {r5, r6}
mrc p15, 0, r0, c1, c0 @ get control register v4 mrc p15, 0, r0, c1, c0 @ get control register v4
ldr r5, arm926_cr1_clear
bic r0, r0, r5 bic r0, r0, r5
ldr r5, arm926_cr1_set orr r0, r0, r6
orr r0, r0, r5
#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
orr r0, r0, #0x4000 @ .1.. .... .... .... orr r0, r0, #0x4000 @ .1.. .... .... ....
#endif #endif
@ -420,12 +420,9 @@ __arm926_setup:
* .011 0001 ..11 0101 * .011 0001 ..11 0101
* *
*/ */
.type arm926_cr1_clear, #object .type arm926_crval, #object
.type arm926_cr1_set, #object arm926_crval:
arm926_cr1_clear: crval clear=0x00007f3f, mmuset=0x00003135, ucset=0x00001134
.word 0x7f3f
arm926_cr1_set:
.word 0x3135
__INITDATA __INITDATA
@ -459,22 +456,7 @@ cpu_elf_name:
.type cpu_arm926_name, #object .type cpu_arm926_name, #object
cpu_arm926_name: cpu_arm926_name:
.ascii "ARM926EJ-S" .asciz "ARM926EJ-S"
#ifndef CONFIG_CPU_ICACHE_DISABLE
.ascii "i"
#endif
#ifndef CONFIG_CPU_DCACHE_DISABLE
.ascii "d"
#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
.ascii "(wt)"
#else
.ascii "(wb)"
#endif
#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
.ascii "RR"
#endif
#endif
.ascii "\0"
.size cpu_arm926_name, . - cpu_arm926_name .size cpu_arm926_name, . - cpu_arm926_name
.align .align
@ -491,6 +473,10 @@ __arm926_proc_info:
PMD_BIT4 | \ PMD_BIT4 | \
PMD_SECT_AP_WRITE | \ PMD_SECT_AP_WRITE | \
PMD_SECT_AP_READ PMD_SECT_AP_READ
.long PMD_TYPE_SECT | \
PMD_BIT4 | \
PMD_SECT_AP_WRITE | \
PMD_SECT_AP_READ
b __arm926_setup b __arm926_setup
.long cpu_arch_name .long cpu_arch_name
.long cpu_elf_name .long cpu_elf_name

10
arch/arm/mm/proc-macros.S
View File

@ -49,3 +49,13 @@
.macro asid, rd, rn .macro asid, rd, rn
and \rd, \rn, #255 and \rd, \rn, #255
.endm .endm
.macro crval, clear, mmuset, ucset
#ifdef CONFIG_MMU
.word \clear
.word \mmuset
#else
.word \clear
.word \ucset
#endif
.endm

19
arch/arm/mm/proc-sa110.S
View File

@ -185,11 +185,12 @@ __sa110_setup:
#ifdef CONFIG_MMU #ifdef CONFIG_MMU
mcr p15, 0, r10, c8, c7 @ invalidate I,D TLBs on v4 mcr p15, 0, r10, c8, c7 @ invalidate I,D TLBs on v4
#endif #endif
adr r5, sa110_crval
ldmia r5, {r5, r6}
mrc p15, 0, r0, c1, c0 @ get control register v4 mrc p15, 0, r0, c1, c0 @ get control register v4
ldr r5, sa110_cr1_clear
bic r0, r0, r5 bic r0, r0, r5
ldr r5, sa110_cr1_set orr r0, r0, r6
orr r0, r0, r5
mov pc, lr mov pc, lr
.size __sa110_setup, . - __sa110_setup .size __sa110_setup, . - __sa110_setup
@ -199,12 +200,9 @@ __sa110_setup:
* ..01 0001 ..11 1101 * ..01 0001 ..11 1101
* *
*/ */
.type sa110_cr1_clear, #object .type sa110_crval, #object
.type sa110_cr1_set, #object sa110_crval:
sa110_cr1_clear: crval clear=0x00003f3f, mmuset=0x0000113d, ucset=0x00001130
.word 0x3f3f
sa110_cr1_set:
.word 0x113d
__INITDATA __INITDATA
@ -255,6 +253,9 @@ __sa110_proc_info:
PMD_SECT_CACHEABLE | \ PMD_SECT_CACHEABLE | \
PMD_SECT_AP_WRITE | \ PMD_SECT_AP_WRITE | \
PMD_SECT_AP_READ PMD_SECT_AP_READ
.long PMD_TYPE_SECT | \
PMD_SECT_AP_WRITE | \
PMD_SECT_AP_READ
b __sa110_setup b __sa110_setup
.long cpu_arch_name .long cpu_arch_name
.long cpu_elf_name .long cpu_elf_name

21
arch/arm/mm/proc-sa1100.S
View File

@ -198,11 +198,11 @@ __sa1100_setup:
#ifdef CONFIG_MMU #ifdef CONFIG_MMU
mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
#endif #endif
adr r5, sa1100_crval
ldmia r5, {r5, r6}
mrc p15, 0, r0, c1, c0 @ get control register v4 mrc p15, 0, r0, c1, c0 @ get control register v4
ldr r5, sa1100_cr1_clear
bic r0, r0, r5 bic r0, r0, r5
ldr r5, sa1100_cr1_set orr r0, r0, r6
orr r0, r0, r5
mov pc, lr mov pc, lr
.size __sa1100_setup, . - __sa1100_setup .size __sa1100_setup, . - __sa1100_setup
@ -212,12 +212,9 @@ __sa1100_setup:
* ..11 0001 ..11 1101 * ..11 0001 ..11 1101
* *
*/ */
.type sa1100_cr1_clear, #object .type sa1100_crval, #object
.type sa1100_cr1_set, #object sa1100_crval:
sa1100_cr1_clear: crval clear=0x00003f3f, mmuset=0x0000313d, ucset=0x00001130
.word 0x3f3f
sa1100_cr1_set:
.word 0x313d
__INITDATA __INITDATA
@ -276,6 +273,9 @@ __sa1100_proc_info:
PMD_SECT_CACHEABLE | \ PMD_SECT_CACHEABLE | \
PMD_SECT_AP_WRITE | \ PMD_SECT_AP_WRITE | \
PMD_SECT_AP_READ PMD_SECT_AP_READ
.long PMD_TYPE_SECT | \
PMD_SECT_AP_WRITE | \
PMD_SECT_AP_READ
b __sa1100_setup b __sa1100_setup
.long cpu_arch_name .long cpu_arch_name
.long cpu_elf_name .long cpu_elf_name
@ -296,6 +296,9 @@ __sa1110_proc_info:
PMD_SECT_CACHEABLE | \ PMD_SECT_CACHEABLE | \
PMD_SECT_AP_WRITE | \ PMD_SECT_AP_WRITE | \
PMD_SECT_AP_READ PMD_SECT_AP_READ
.long PMD_TYPE_SECT | \
PMD_SECT_AP_WRITE | \
PMD_SECT_AP_READ
b __sa1100_setup b __sa1100_setup
.long cpu_arch_name .long cpu_arch_name
.long cpu_elf_name .long cpu_elf_name

19
arch/arm/mm/proc-v6.S
View File

@ -212,11 +212,11 @@ __v6_setup:
orr r0, r0, #(0xf << 20) orr r0, r0, #(0xf << 20)
mcr p15, 0, r0, c1, c0, 2 @ Enable full access to VFP mcr p15, 0, r0, c1, c0, 2 @ Enable full access to VFP
#endif #endif
adr r5, v6_crval
ldmia r5, {r5, r6}
mrc p15, 0, r0, c1, c0, 0 @ read control register mrc p15, 0, r0, c1, c0, 0 @ read control register
ldr r5, v6_cr1_clear @ get mask for bits to clear
bic r0, r0, r5 @ clear bits them bic r0, r0, r5 @ clear bits them
ldr r5, v6_cr1_set @ get mask for bits to set orr r0, r0, r6 @ set them
orr r0, r0, r5 @ set them
mov pc, lr @ return to head.S:__ret mov pc, lr @ return to head.S:__ret
/* /*
@ -225,12 +225,9 @@ __v6_setup:
* rrrr rrrx xxx0 0101 xxxx xxxx x111 xxxx < forced * rrrr rrrx xxx0 0101 xxxx xxxx x111 xxxx < forced
* 0 110 0011 1.00 .111 1101 < we want * 0 110 0011 1.00 .111 1101 < we want
*/ */
.type v6_cr1_clear, #object .type v6_crval, #object
.type v6_cr1_set, #object v6_crval:
v6_cr1_clear: crval clear=0x01e0fb7f, mmuset=0x00c0387d, ucset=0x00c0187c
.word 0x01e0fb7f
v6_cr1_set:
.word 0x00c0387d
.type v6_processor_functions, #object .type v6_processor_functions, #object
ENTRY(v6_processor_functions) ENTRY(v6_processor_functions)
@ -269,6 +266,10 @@ __v6_proc_info:
PMD_SECT_CACHEABLE | \ PMD_SECT_CACHEABLE | \
PMD_SECT_AP_WRITE | \ PMD_SECT_AP_WRITE | \
PMD_SECT_AP_READ PMD_SECT_AP_READ
.long PMD_TYPE_SECT | \
PMD_SECT_XN | \
PMD_SECT_AP_WRITE | \
PMD_SECT_AP_READ
b __v6_setup b __v6_setup
.long cpu_arch_name .long cpu_arch_name
.long cpu_elf_name .long cpu_elf_name

28
arch/arm/mm/proc-xsc3.S
View File

@ -426,23 +426,26 @@ __xsc3_setup:
orr r0, r0, #(1 << 10) @ enable L2 for LLR cache orr r0, r0, #(1 << 10) @ enable L2 for LLR cache
#endif #endif
mcr p15, 0, r0, c1, c0, 1 @ set auxiliary control reg mcr p15, 0, r0, c1, c0, 1 @ set auxiliary control reg
adr r5, xsc3_crval
ldmia r5, {r5, r6}
mrc p15, 0, r0, c1, c0, 0 @ get control register mrc p15, 0, r0, c1, c0, 0 @ get control register
bic r0, r0, #0x0002 @ .... .... .... ..A. bic r0, r0, r5 @ .... .... .... ..A.
orr r0, r0, #0x0005 @ .... .... .... .C.M orr r0, r0, r6 @ .... .... .... .C.M
#if BTB_ENABLE #if BTB_ENABLE
bic r0, r0, #0x0200 @ .... ..R. .... .... orr r0, r0, #0x00000800 @ ..VI Z..S .... ....
orr r0, r0, #0x3900 @ ..VI Z..S .... ....
#else
bic r0, r0, #0x0a00 @ .... Z.R. .... ....
orr r0, r0, #0x3100 @ ..VI ...S .... ....
#endif #endif
#if L2_CACHE_ENABLE #if L2_CACHE_ENABLE
orr r0, r0, #0x4000000 @ L2 enable orr r0, r0, #0x04000000 @ L2 enable
#endif #endif
mov pc, lr mov pc, lr
.size __xsc3_setup, . - __xsc3_setup .size __xsc3_setup, . - __xsc3_setup
.type xsc3_crval, #object
xsc3_crval:
crval clear=0x04003b02, mmuset=0x00003105, ucset=0x00001100
__INITDATA __INITDATA
/* /*
@ -487,7 +490,14 @@ cpu_xsc3_name:
__xsc3_proc_info: __xsc3_proc_info:
.long 0x69056000 .long 0x69056000
.long 0xffffe000 .long 0xffffe000
.long 0x00000c0e .long PMD_TYPE_SECT | \
PMD_SECT_BUFFERABLE | \
PMD_SECT_CACHEABLE | \
PMD_SECT_AP_WRITE | \
PMD_SECT_AP_READ
.long PMD_TYPE_SECT | \
PMD_SECT_AP_WRITE | \
PMD_SECT_AP_READ
b __xsc3_setup b __xsc3_setup
.long cpu_arch_name .long cpu_arch_name
.long cpu_elf_name .long cpu_elf_name

63
arch/arm/mm/proc-xscale.S
View File

@ -138,17 +138,23 @@ ENTRY(cpu_xscale_proc_fin)
* to what would be the reset vector. * to what would be the reset vector.
* *
* loc: location to jump to for soft reset * loc: location to jump to for soft reset
*
* Beware PXA270 erratum E7.
*/ */
.align 5 .align 5
ENTRY(cpu_xscale_reset) ENTRY(cpu_xscale_reset)
mov r1, #PSR_F_BIT|PSR_I_BIT|SVC_MODE mov r1, #PSR_F_BIT|PSR_I_BIT|SVC_MODE
msr cpsr_c, r1 @ reset CPSR msr cpsr_c, r1 @ reset CPSR
mcr p15, 0, r1, c10, c4, 1 @ unlock I-TLB
mcr p15, 0, r1, c8, c5, 0 @ invalidate I-TLB
mrc p15, 0, r1, c1, c0, 0 @ ctrl register mrc p15, 0, r1, c1, c0, 0 @ ctrl register
bic r1, r1, #0x0086 @ ........B....CA. bic r1, r1, #0x0086 @ ........B....CA.
bic r1, r1, #0x3900 @ ..VIZ..S........ bic r1, r1, #0x3900 @ ..VIZ..S........
sub pc, pc, #4 @ flush pipeline
@ *** cache line aligned ***
mcr p15, 0, r1, c1, c0, 0 @ ctrl register mcr p15, 0, r1, c1, c0, 0 @ ctrl register
mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches & BTB
bic r1, r1, #0x0001 @ ...............M bic r1, r1, #0x0001 @ ...............M
mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches & BTB
mcr p15, 0, r1, c1, c0, 0 @ ctrl register mcr p15, 0, r1, c1, c0, 0 @ ctrl register
@ CAUTION: MMU turned off from this point. We count on the pipeline @ CAUTION: MMU turned off from this point. We count on the pipeline
@ already containing those two last instructions to survive. @ already containing those two last instructions to survive.
@ -475,11 +481,12 @@ __xscale_setup:
orr r0, r0, #1 << 6 @ cp6 for IOP3xx and Bulverde orr r0, r0, #1 << 6 @ cp6 for IOP3xx and Bulverde
orr r0, r0, #1 << 13 @ Its undefined whether this orr r0, r0, #1 << 13 @ Its undefined whether this
mcr p15, 0, r0, c15, c1, 0 @ affects USR or SVC modes mcr p15, 0, r0, c15, c1, 0 @ affects USR or SVC modes
adr r5, xscale_crval
ldmia r5, {r5, r6}
mrc p15, 0, r0, c1, c0, 0 @ get control register mrc p15, 0, r0, c1, c0, 0 @ get control register
ldr r5, xscale_cr1_clear
bic r0, r0, r5 bic r0, r0, r5
ldr r5, xscale_cr1_set orr r0, r0, r6
orr r0, r0, r5
mov pc, lr mov pc, lr
.size __xscale_setup, . - __xscale_setup .size __xscale_setup, . - __xscale_setup
@ -489,12 +496,9 @@ __xscale_setup:
* ..11 1.01 .... .101 * ..11 1.01 .... .101
* *
*/ */
.type xscale_cr1_clear, #object .type xscale_crval, #object
.type xscale_cr1_set, #object xscale_crval:
xscale_cr1_clear: crval clear=0x00003b07, mmuset=0x00003905, ucset=0x00001900
.word 0x3b07
xscale_cr1_set:
.word 0x3905
__INITDATA __INITDATA
@ -595,6 +599,9 @@ __80200_proc_info:
PMD_SECT_CACHEABLE | \ PMD_SECT_CACHEABLE | \
PMD_SECT_AP_WRITE | \ PMD_SECT_AP_WRITE | \
PMD_SECT_AP_READ PMD_SECT_AP_READ
.long PMD_TYPE_SECT | \
PMD_SECT_AP_WRITE | \
PMD_SECT_AP_READ
b __xscale_setup b __xscale_setup
.long cpu_arch_name .long cpu_arch_name
.long cpu_elf_name .long cpu_elf_name
@ -615,6 +622,9 @@ __8032x_proc_info:
PMD_SECT_CACHEABLE | \ PMD_SECT_CACHEABLE | \
PMD_SECT_AP_WRITE | \ PMD_SECT_AP_WRITE | \
PMD_SECT_AP_READ PMD_SECT_AP_READ
.long PMD_TYPE_SECT | \
PMD_SECT_AP_WRITE | \
PMD_SECT_AP_READ
b __xscale_setup b __xscale_setup
.long cpu_arch_name .long cpu_arch_name
.long cpu_elf_name .long cpu_elf_name
@ -635,6 +645,9 @@ __8033x_proc_info:
PMD_SECT_CACHEABLE | \ PMD_SECT_CACHEABLE | \
PMD_SECT_AP_WRITE | \ PMD_SECT_AP_WRITE | \
PMD_SECT_AP_READ PMD_SECT_AP_READ
.long PMD_TYPE_SECT | \
PMD_SECT_AP_WRITE | \
PMD_SECT_AP_READ
b __xscale_setup b __xscale_setup
.long cpu_arch_name .long cpu_arch_name
.long cpu_elf_name .long cpu_elf_name
@ -655,6 +668,9 @@ __pxa250_proc_info:
PMD_SECT_CACHEABLE | \ PMD_SECT_CACHEABLE | \
PMD_SECT_AP_WRITE | \ PMD_SECT_AP_WRITE | \
PMD_SECT_AP_READ PMD_SECT_AP_READ
.long PMD_TYPE_SECT | \
PMD_SECT_AP_WRITE | \
PMD_SECT_AP_READ
b __xscale_setup b __xscale_setup
.long cpu_arch_name .long cpu_arch_name
.long cpu_elf_name .long cpu_elf_name
@ -675,6 +691,9 @@ __pxa210_proc_info:
PMD_SECT_CACHEABLE | \ PMD_SECT_CACHEABLE | \
PMD_SECT_AP_WRITE | \ PMD_SECT_AP_WRITE | \
PMD_SECT_AP_READ PMD_SECT_AP_READ
.long PMD_TYPE_SECT | \
PMD_SECT_AP_WRITE | \
PMD_SECT_AP_READ
b __xscale_setup b __xscale_setup
.long cpu_arch_name .long cpu_arch_name
.long cpu_elf_name .long cpu_elf_name
@ -695,6 +714,9 @@ __ixp2400_proc_info:
PMD_SECT_CACHEABLE | \ PMD_SECT_CACHEABLE | \
PMD_SECT_AP_WRITE | \ PMD_SECT_AP_WRITE | \
PMD_SECT_AP_READ PMD_SECT_AP_READ
.long PMD_TYPE_SECT | \
PMD_SECT_AP_WRITE | \
PMD_SECT_AP_READ
b __xscale_setup b __xscale_setup
.long cpu_arch_name .long cpu_arch_name
.long cpu_elf_name .long cpu_elf_name
@ -715,6 +737,9 @@ __ixp2800_proc_info:
PMD_SECT_CACHEABLE | \ PMD_SECT_CACHEABLE | \
PMD_SECT_AP_WRITE | \ PMD_SECT_AP_WRITE | \
PMD_SECT_AP_READ PMD_SECT_AP_READ
.long PMD_TYPE_SECT | \
PMD_SECT_AP_WRITE | \
PMD_SECT_AP_READ
b __xscale_setup b __xscale_setup
.long cpu_arch_name .long cpu_arch_name
.long cpu_elf_name .long cpu_elf_name
@ -735,6 +760,9 @@ __ixp42x_proc_info:
PMD_SECT_CACHEABLE | \ PMD_SECT_CACHEABLE | \
PMD_SECT_AP_WRITE | \ PMD_SECT_AP_WRITE | \
PMD_SECT_AP_READ PMD_SECT_AP_READ
.long PMD_TYPE_SECT | \
PMD_SECT_AP_WRITE | \
PMD_SECT_AP_READ
b __xscale_setup b __xscale_setup
.long cpu_arch_name .long cpu_arch_name
.long cpu_elf_name .long cpu_elf_name
@ -750,7 +778,14 @@ __ixp42x_proc_info:
__ixp46x_proc_info: __ixp46x_proc_info:
.long 0x69054200 .long 0x69054200
.long 0xffffff00 .long 0xffffff00
.long 0x00000c0e .long PMD_TYPE_SECT | \
PMD_SECT_BUFFERABLE | \
PMD_SECT_CACHEABLE | \
PMD_SECT_AP_WRITE | \
PMD_SECT_AP_READ
.long PMD_TYPE_SECT | \
PMD_SECT_AP_WRITE | \
PMD_SECT_AP_READ
b __xscale_setup b __xscale_setup
.long cpu_arch_name .long cpu_arch_name
.long cpu_elf_name .long cpu_elf_name
@ -771,6 +806,9 @@ __pxa255_proc_info:
PMD_SECT_CACHEABLE | \ PMD_SECT_CACHEABLE | \
PMD_SECT_AP_WRITE | \ PMD_SECT_AP_WRITE | \
PMD_SECT_AP_READ PMD_SECT_AP_READ
.long PMD_TYPE_SECT | \
PMD_SECT_AP_WRITE | \
PMD_SECT_AP_READ
b __xscale_setup b __xscale_setup
.long cpu_arch_name .long cpu_arch_name
.long cpu_elf_name .long cpu_elf_name
@ -791,6 +829,9 @@ __pxa270_proc_info:
PMD_SECT_CACHEABLE | \ PMD_SECT_CACHEABLE | \
PMD_SECT_AP_WRITE | \ PMD_SECT_AP_WRITE | \
PMD_SECT_AP_READ PMD_SECT_AP_READ
.long PMD_TYPE_SECT | \
PMD_SECT_AP_WRITE | \
PMD_SECT_AP_READ
b __xscale_setup b __xscale_setup
.long cpu_arch_name .long cpu_arch_name
.long cpu_elf_name .long cpu_elf_name

2
arch/arm/plat-omap/Kconfig
View File

@ -91,7 +91,7 @@ config OMAP_32K_TIMER_HZ
config OMAP_DM_TIMER config OMAP_DM_TIMER
bool "Use dual-mode timer" bool "Use dual-mode timer"
depends on ARCH_OMAP16XX depends on ARCH_OMAP16XX || ARCH_OMAP24XX
help help
Select this option if you want to use OMAP Dual-Mode timers. Select this option if you want to use OMAP Dual-Mode timers.

4
arch/arm/plat-omap/clock.c
View File

@ -27,9 +27,9 @@
#include <asm/arch/clock.h> #include <asm/arch/clock.h>
LIST_HEAD(clocks); static LIST_HEAD(clocks);
static DEFINE_MUTEX(clocks_mutex); static DEFINE_MUTEX(clocks_mutex);
DEFINE_SPINLOCK(clockfw_lock); static DEFINE_SPINLOCK(clockfw_lock);
static struct clk_functions *arch_clock; static struct clk_functions *arch_clock;

18
arch/arm/plat-omap/cpu-omap.c
View File

@ -25,6 +25,14 @@
#include <asm/io.h> #include <asm/io.h>
#include <asm/system.h> #include <asm/system.h>
#define VERY_HI_RATE 900000000
#ifdef CONFIG_ARCH_OMAP1
#define MPU_CLK "mpu"
#else
#define MPU_CLK "virt_prcm_set"
#endif
/* TODO: Add support for SDRAM timing changes */ /* TODO: Add support for SDRAM timing changes */
int omap_verify_speed(struct cpufreq_policy *policy) int omap_verify_speed(struct cpufreq_policy *policy)
@ -36,7 +44,7 @@ int omap_verify_speed(struct cpufreq_policy *policy)
cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq, cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq,
policy->cpuinfo.max_freq); policy->cpuinfo.max_freq);
mpu_clk = clk_get(NULL, "mpu"); mpu_clk = clk_get(NULL, MPU_CLK);
if (IS_ERR(mpu_clk)) if (IS_ERR(mpu_clk))
return PTR_ERR(mpu_clk); return PTR_ERR(mpu_clk);
policy->min = clk_round_rate(mpu_clk, policy->min * 1000) / 1000; policy->min = clk_round_rate(mpu_clk, policy->min * 1000) / 1000;
@ -56,7 +64,7 @@ unsigned int omap_getspeed(unsigned int cpu)
if (cpu) if (cpu)
return 0; return 0;
mpu_clk = clk_get(NULL, "mpu"); mpu_clk = clk_get(NULL, MPU_CLK);
if (IS_ERR(mpu_clk)) if (IS_ERR(mpu_clk))
return 0; return 0;
rate = clk_get_rate(mpu_clk) / 1000; rate = clk_get_rate(mpu_clk) / 1000;
@ -73,7 +81,7 @@ static int omap_target(struct cpufreq_policy *policy,
struct cpufreq_freqs freqs; struct cpufreq_freqs freqs;
int ret = 0; int ret = 0;
mpu_clk = clk_get(NULL, "mpu"); mpu_clk = clk_get(NULL, MPU_CLK);
if (IS_ERR(mpu_clk)) if (IS_ERR(mpu_clk))
return PTR_ERR(mpu_clk); return PTR_ERR(mpu_clk);
@ -93,7 +101,7 @@ static int __init omap_cpu_init(struct cpufreq_policy *policy)
{ {
struct clk * mpu_clk; struct clk * mpu_clk;
mpu_clk = clk_get(NULL, "mpu"); mpu_clk = clk_get(NULL, MPU_CLK);
if (IS_ERR(mpu_clk)) if (IS_ERR(mpu_clk))
return PTR_ERR(mpu_clk); return PTR_ERR(mpu_clk);
@ -102,7 +110,7 @@ static int __init omap_cpu_init(struct cpufreq_policy *policy)
policy->cur = policy->min = policy->max = omap_getspeed(0); policy->cur = policy->min = policy->max = omap_getspeed(0);
policy->governor = CPUFREQ_DEFAULT_GOVERNOR; policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
policy->cpuinfo.min_freq = clk_round_rate(mpu_clk, 0) / 1000; policy->cpuinfo.min_freq = clk_round_rate(mpu_clk, 0) / 1000;
policy->cpuinfo.max_freq = clk_round_rate(mpu_clk, 216000000) / 1000; policy->cpuinfo.max_freq = clk_round_rate(mpu_clk, VERY_HI_RATE) / 1000;
policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL; policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;
clk_put(mpu_clk); clk_put(mpu_clk);

10
arch/arm/plat-omap/devices.c
View File

@ -104,7 +104,7 @@ static void omap_init_kp(void)
omap_cfg_reg(E20_1610_KBR3); omap_cfg_reg(E20_1610_KBR3);
omap_cfg_reg(E19_1610_KBR4); omap_cfg_reg(E19_1610_KBR4);
omap_cfg_reg(N19_1610_KBR5); omap_cfg_reg(N19_1610_KBR5);
} else if (machine_is_omap_perseus2()) { } else if (machine_is_omap_perseus2() || machine_is_omap_fsample()) {
omap_cfg_reg(E2_730_KBR0); omap_cfg_reg(E2_730_KBR0);
omap_cfg_reg(J7_730_KBR1); omap_cfg_reg(J7_730_KBR1);
omap_cfg_reg(E1_730_KBR2); omap_cfg_reg(E1_730_KBR2);
@ -161,8 +161,8 @@ static u64 mmc1_dmamask = 0xffffffff;
static struct resource mmc1_resources[] = { static struct resource mmc1_resources[] = {
{ {
.start = IO_ADDRESS(OMAP_MMC1_BASE), .start = OMAP_MMC1_BASE,
.end = IO_ADDRESS(OMAP_MMC1_BASE) + 0x7f, .end = OMAP_MMC1_BASE + 0x7f,
.flags = IORESOURCE_MEM, .flags = IORESOURCE_MEM,
}, },
{ {
@ -190,8 +190,8 @@ static u64 mmc2_dmamask = 0xffffffff;
static struct resource mmc2_resources[] = { static struct resource mmc2_resources[] = {
{ {
.start = IO_ADDRESS(OMAP_MMC2_BASE), .start = OMAP_MMC2_BASE,
.end = IO_ADDRESS(OMAP_MMC2_BASE) + 0x7f, .end = OMAP_MMC2_BASE + 0x7f,
.flags = IORESOURCE_MEM, .flags = IORESOURCE_MEM,
}, },
{ {

84
arch/arm/plat-omap/dma.c
View File

@ -43,6 +43,7 @@
#define OMAP_DMA_ACTIVE 0x01 #define OMAP_DMA_ACTIVE 0x01
#define OMAP_DMA_CCR_EN (1 << 7) #define OMAP_DMA_CCR_EN (1 << 7)
#define OMAP2_DMA_CSR_CLEAR_MASK 0xffe
#define OMAP_FUNC_MUX_ARM_BASE (0xfffe1000 + 0xec) #define OMAP_FUNC_MUX_ARM_BASE (0xfffe1000 + 0xec)
@ -166,18 +167,24 @@ void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
if (cpu_is_omap24xx() && dma_trigger) { if (cpu_is_omap24xx() && dma_trigger) {
u32 val = OMAP_DMA_CCR_REG(lch); u32 val = OMAP_DMA_CCR_REG(lch);
val &= ~(3 << 19);
if (dma_trigger > 63) if (dma_trigger > 63)
val |= 1 << 20; val |= 1 << 20;
if (dma_trigger > 31) if (dma_trigger > 31)
val |= 1 << 19; val |= 1 << 19;
val &= ~(0x1f);
val |= (dma_trigger & 0x1f); val |= (dma_trigger & 0x1f);
if (sync_mode & OMAP_DMA_SYNC_FRAME) if (sync_mode & OMAP_DMA_SYNC_FRAME)
val |= 1 << 5; val |= 1 << 5;
else
val &= ~(1 << 5);
if (sync_mode & OMAP_DMA_SYNC_BLOCK) if (sync_mode & OMAP_DMA_SYNC_BLOCK)
val |= 1 << 18; val |= 1 << 18;
else
val &= ~(1 << 18);
if (src_or_dst_synch) if (src_or_dst_synch)
val |= 1 << 24; /* source synch */ val |= 1 << 24; /* source synch */
@ -286,22 +293,39 @@ void omap_set_dma_src_data_pack(int lch, int enable)
void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode) void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
{ {
unsigned int burst = 0;
OMAP_DMA_CSDP_REG(lch) &= ~(0x03 << 7); OMAP_DMA_CSDP_REG(lch) &= ~(0x03 << 7);
switch (burst_mode) { switch (burst_mode) {
case OMAP_DMA_DATA_BURST_DIS: case OMAP_DMA_DATA_BURST_DIS:
break; break;
case OMAP_DMA_DATA_BURST_4: case OMAP_DMA_DATA_BURST_4:
OMAP_DMA_CSDP_REG(lch) |= (0x02 << 7); if (cpu_is_omap24xx())
burst = 0x1;
else
burst = 0x2;
break; break;
case OMAP_DMA_DATA_BURST_8: case OMAP_DMA_DATA_BURST_8:
/* not supported by current hardware if (cpu_is_omap24xx()) {
burst = 0x2;
break;
}
/* not supported by current hardware on OMAP1
* w |= (0x03 << 7); * w |= (0x03 << 7);
* fall through * fall through
*/ */
case OMAP_DMA_DATA_BURST_16:
if (cpu_is_omap24xx()) {
burst = 0x3;
break;
}
/* OMAP1 don't support burst 16
* fall through
*/
default: default:
BUG(); BUG();
} }
OMAP_DMA_CSDP_REG(lch) |= (burst << 7);
} }
/* Note that dest_port is only for OMAP1 */ /* Note that dest_port is only for OMAP1 */
@ -348,30 +372,49 @@ void omap_set_dma_dest_data_pack(int lch, int enable)
void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode) void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
{ {
unsigned int burst = 0;
OMAP_DMA_CSDP_REG(lch) &= ~(0x03 << 14); OMAP_DMA_CSDP_REG(lch) &= ~(0x03 << 14);
switch (burst_mode) { switch (burst_mode) {
case OMAP_DMA_DATA_BURST_DIS: case OMAP_DMA_DATA_BURST_DIS:
break; break;
case OMAP_DMA_DATA_BURST_4: case OMAP_DMA_DATA_BURST_4:
OMAP_DMA_CSDP_REG(lch) |= (0x02 << 14); if (cpu_is_omap24xx())
burst = 0x1;
else
burst = 0x2;
break; break;
case OMAP_DMA_DATA_BURST_8: case OMAP_DMA_DATA_BURST_8:
OMAP_DMA_CSDP_REG(lch) |= (0x03 << 14); if (cpu_is_omap24xx())
burst = 0x2;
else
burst = 0x3;
break; break;
case OMAP_DMA_DATA_BURST_16:
if (cpu_is_omap24xx()) {
burst = 0x3;
break;
}
/* OMAP1 don't support burst 16
* fall through
*/
default: default:
printk(KERN_ERR "Invalid DMA burst mode\n"); printk(KERN_ERR "Invalid DMA burst mode\n");
BUG(); BUG();
return; return;
} }
OMAP_DMA_CSDP_REG(lch) |= (burst << 14);
} }
static inline void omap_enable_channel_irq(int lch) static inline void omap_enable_channel_irq(int lch)
{ {
u32 status; u32 status;
/* Read CSR to make sure it's cleared. */ /* Clear CSR */
status = OMAP_DMA_CSR_REG(lch); if (cpu_class_is_omap1())
status = OMAP_DMA_CSR_REG(lch);
else if (cpu_is_omap24xx())
OMAP_DMA_CSR_REG(lch) = OMAP2_DMA_CSR_CLEAR_MASK;
/* Enable some nice interrupts. */ /* Enable some nice interrupts. */
OMAP_DMA_CICR_REG(lch) = dma_chan[lch].enabled_irqs; OMAP_DMA_CICR_REG(lch) = dma_chan[lch].enabled_irqs;
@ -470,11 +513,13 @@ int omap_request_dma(int dev_id, const char *dev_name,
chan->dev_name = dev_name; chan->dev_name = dev_name;
chan->callback = callback; chan->callback = callback;
chan->data = data; chan->data = data;
chan->enabled_irqs = OMAP_DMA_TOUT_IRQ | OMAP_DMA_DROP_IRQ | chan->enabled_irqs = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ;
OMAP_DMA_BLOCK_IRQ;
if (cpu_is_omap24xx()) if (cpu_class_is_omap1())
chan->enabled_irqs |= OMAP2_DMA_TRANS_ERR_IRQ; chan->enabled_irqs |= OMAP1_DMA_TOUT_IRQ;
else if (cpu_is_omap24xx())
chan->enabled_irqs |= OMAP2_DMA_MISALIGNED_ERR_IRQ |
OMAP2_DMA_TRANS_ERR_IRQ;
if (cpu_is_omap16xx()) { if (cpu_is_omap16xx()) {
/* If the sync device is set, configure it dynamically. */ /* If the sync device is set, configure it dynamically. */
@ -494,7 +539,7 @@ int omap_request_dma(int dev_id, const char *dev_name,
omap_enable_channel_irq(free_ch); omap_enable_channel_irq(free_ch);
/* Clear the CSR register and IRQ status register */ /* Clear the CSR register and IRQ status register */
OMAP_DMA_CSR_REG(free_ch) = 0x0; OMAP_DMA_CSR_REG(free_ch) = OMAP2_DMA_CSR_CLEAR_MASK;
omap_writel(~0x0, OMAP_DMA4_IRQSTATUS_L0); omap_writel(~0x0, OMAP_DMA4_IRQSTATUS_L0);
} }
@ -534,7 +579,7 @@ void omap_free_dma(int lch)
omap_writel(val, OMAP_DMA4_IRQENABLE_L0); omap_writel(val, OMAP_DMA4_IRQENABLE_L0);
/* Clear the CSR register and IRQ status register */ /* Clear the CSR register and IRQ status register */
OMAP_DMA_CSR_REG(lch) = 0x0; OMAP_DMA_CSR_REG(lch) = OMAP2_DMA_CSR_CLEAR_MASK;
val = omap_readl(OMAP_DMA4_IRQSTATUS_L0); val = omap_readl(OMAP_DMA4_IRQSTATUS_L0);
val |= 1 << lch; val |= 1 << lch;
@ -798,7 +843,7 @@ static int omap1_dma_handle_ch(int ch)
"%d (CSR %04x)\n", ch, csr); "%d (CSR %04x)\n", ch, csr);
return 0; return 0;
} }
if (unlikely(csr & OMAP_DMA_TOUT_IRQ)) if (unlikely(csr & OMAP1_DMA_TOUT_IRQ))
printk(KERN_WARNING "DMA timeout with device %d\n", printk(KERN_WARNING "DMA timeout with device %d\n",
dma_chan[ch].dev_id); dma_chan[ch].dev_id);
if (unlikely(csr & OMAP_DMA_DROP_IRQ)) if (unlikely(csr & OMAP_DMA_DROP_IRQ))
@ -846,20 +891,21 @@ static int omap2_dma_handle_ch(int ch)
return 0; return 0;
if (unlikely(dma_chan[ch].dev_id == -1)) if (unlikely(dma_chan[ch].dev_id == -1))
return 0; return 0;
/* REVISIT: According to 24xx TRM, there's no TOUT_IE */
if (unlikely(status & OMAP_DMA_TOUT_IRQ))
printk(KERN_INFO "DMA timeout with device %d\n",
dma_chan[ch].dev_id);
if (unlikely(status & OMAP_DMA_DROP_IRQ)) if (unlikely(status & OMAP_DMA_DROP_IRQ))
printk(KERN_INFO printk(KERN_INFO
"DMA synchronization event drop occurred with device " "DMA synchronization event drop occurred with device "
"%d\n", dma_chan[ch].dev_id); "%d\n", dma_chan[ch].dev_id);
if (unlikely(status & OMAP2_DMA_TRANS_ERR_IRQ)) if (unlikely(status & OMAP2_DMA_TRANS_ERR_IRQ))
printk(KERN_INFO "DMA transaction error with device %d\n", printk(KERN_INFO "DMA transaction error with device %d\n",
dma_chan[ch].dev_id); dma_chan[ch].dev_id);
if (unlikely(status & OMAP2_DMA_SECURE_ERR_IRQ))
printk(KERN_INFO "DMA secure error with device %d\n",
dma_chan[ch].dev_id);
if (unlikely(status & OMAP2_DMA_MISALIGNED_ERR_IRQ))
printk(KERN_INFO "DMA misaligned error with device %d\n",
dma_chan[ch].dev_id);
OMAP_DMA_CSR_REG(ch) = 0x20; OMAP_DMA_CSR_REG(ch) = OMAP2_DMA_CSR_CLEAR_MASK;
val = omap_readl(OMAP_DMA4_IRQSTATUS_L0); val = omap_readl(OMAP_DMA4_IRQSTATUS_L0);
/* ch in this function is from 0-31 while in register it is 1-32 */ /* ch in this function is from 0-31 while in register it is 1-32 */

484
arch/arm/plat-omap/dmtimer.c
View File

@ -4,7 +4,8 @@
* OMAP Dual-Mode Timers * OMAP Dual-Mode Timers
* *
* Copyright (C) 2005 Nokia Corporation * Copyright (C) 2005 Nokia Corporation
* Author: Lauri Leukkunen <lauri.leukkunen@nokia.com> * OMAP2 support by Juha Yrjola
* API improvements and OMAP2 clock framework support by Timo Teras
* *
* This program is free software; you can redistribute it and/or modify it * This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the * under the terms of the GNU General Public License as published by the
@ -26,15 +27,17 @@
*/ */
#include <linux/init.h> #include <linux/init.h>
#include <linux/spinlock.h>
#include <linux/errno.h>
#include <linux/list.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <asm/hardware.h> #include <asm/hardware.h>
#include <asm/arch/dmtimer.h> #include <asm/arch/dmtimer.h>
#include <asm/io.h> #include <asm/io.h>
#include <asm/arch/irqs.h> #include <asm/arch/irqs.h>
#include <linux/spinlock.h>
#include <linux/list.h>
#define OMAP_TIMER_COUNT 8
/* register offsets */
#define OMAP_TIMER_ID_REG 0x00 #define OMAP_TIMER_ID_REG 0x00
#define OMAP_TIMER_OCP_CFG_REG 0x10 #define OMAP_TIMER_OCP_CFG_REG 0x10
#define OMAP_TIMER_SYS_STAT_REG 0x14 #define OMAP_TIMER_SYS_STAT_REG 0x14
@ -50,52 +53,196 @@
#define OMAP_TIMER_CAPTURE_REG 0x3c #define OMAP_TIMER_CAPTURE_REG 0x3c
#define OMAP_TIMER_IF_CTRL_REG 0x40 #define OMAP_TIMER_IF_CTRL_REG 0x40
/* timer control reg bits */
#define OMAP_TIMER_CTRL_GPOCFG (1 << 14)
#define OMAP_TIMER_CTRL_CAPTMODE (1 << 13)
#define OMAP_TIMER_CTRL_PT (1 << 12)
#define OMAP_TIMER_CTRL_TCM_LOWTOHIGH (0x1 << 8)
#define OMAP_TIMER_CTRL_TCM_HIGHTOLOW (0x2 << 8)
#define OMAP_TIMER_CTRL_TCM_BOTHEDGES (0x3 << 8)
#define OMAP_TIMER_CTRL_SCPWM (1 << 7)
#define OMAP_TIMER_CTRL_CE (1 << 6) /* compare enable */
#define OMAP_TIMER_CTRL_PRE (1 << 5) /* prescaler enable */
#define OMAP_TIMER_CTRL_PTV_SHIFT 2 /* how much to shift the prescaler value */
#define OMAP_TIMER_CTRL_AR (1 << 1) /* auto-reload enable */
#define OMAP_TIMER_CTRL_ST (1 << 0) /* start timer */
static struct dmtimer_info_struct { struct omap_dm_timer {
struct list_head unused_timers; unsigned long phys_base;
struct list_head reserved_timers; int irq;
} dm_timer_info; #ifdef CONFIG_ARCH_OMAP2
struct clk *iclk, *fclk;
static struct omap_dm_timer dm_timers[] = { #endif
{ .base=0xfffb1400, .irq=INT_1610_GPTIMER1 }, void __iomem *io_base;
{ .base=0xfffb1c00, .irq=INT_1610_GPTIMER2 }, unsigned reserved:1;
{ .base=0xfffb2400, .irq=INT_1610_GPTIMER3 },
{ .base=0xfffb2c00, .irq=INT_1610_GPTIMER4 },
{ .base=0xfffb3400, .irq=INT_1610_GPTIMER5 },
{ .base=0xfffb3c00, .irq=INT_1610_GPTIMER6 },
{ .base=0xfffb4400, .irq=INT_1610_GPTIMER7 },
{ .base=0xfffb4c00, .irq=INT_1610_GPTIMER8 },
{ .base=0x0 },
}; };
#ifdef CONFIG_ARCH_OMAP1
static struct omap_dm_timer dm_timers[] = {
{ .phys_base = 0xfffb1400, .irq = INT_1610_GPTIMER1 },
{ .phys_base = 0xfffb1c00, .irq = INT_1610_GPTIMER2 },
{ .phys_base = 0xfffb2400, .irq = INT_1610_GPTIMER3 },
{ .phys_base = 0xfffb2c00, .irq = INT_1610_GPTIMER4 },
{ .phys_base = 0xfffb3400, .irq = INT_1610_GPTIMER5 },
{ .phys_base = 0xfffb3c00, .irq = INT_1610_GPTIMER6 },
{ .phys_base = 0xfffb4400, .irq = INT_1610_GPTIMER7 },
{ .phys_base = 0xfffb4c00, .irq = INT_1610_GPTIMER8 },
};
#elif defined(CONFIG_ARCH_OMAP2)
static struct omap_dm_timer dm_timers[] = {
{ .phys_base = 0x48028000, .irq = INT_24XX_GPTIMER1 },
{ .phys_base = 0x4802a000, .irq = INT_24XX_GPTIMER2 },
{ .phys_base = 0x48078000, .irq = INT_24XX_GPTIMER3 },
{ .phys_base = 0x4807a000, .irq = INT_24XX_GPTIMER4 },
{ .phys_base = 0x4807c000, .irq = INT_24XX_GPTIMER5 },
{ .phys_base = 0x4807e000, .irq = INT_24XX_GPTIMER6 },
{ .phys_base = 0x48080000, .irq = INT_24XX_GPTIMER7 },
{ .phys_base = 0x48082000, .irq = INT_24XX_GPTIMER8 },
{ .phys_base = 0x48084000, .irq = INT_24XX_GPTIMER9 },
{ .phys_base = 0x48086000, .irq = INT_24XX_GPTIMER10 },
{ .phys_base = 0x48088000, .irq = INT_24XX_GPTIMER11 },
{ .phys_base = 0x4808a000, .irq = INT_24XX_GPTIMER12 },
};
static const char *dm_source_names[] = {
"sys_ck",
"func_32k_ck",
"alt_ck"
};
static struct clk *dm_source_clocks[3];
#else
#error OMAP architecture not supported!
#endif
static const int dm_timer_count = ARRAY_SIZE(dm_timers);
static spinlock_t dm_timer_lock; static spinlock_t dm_timer_lock;
static inline u32 omap_dm_timer_read_reg(struct omap_dm_timer *timer, int reg)
inline void omap_dm_timer_write_reg(struct omap_dm_timer *timer, int reg, u32 value)
{ {
omap_writel(value, timer->base + reg); return readl(timer->io_base + reg);
}
static void omap_dm_timer_write_reg(struct omap_dm_timer *timer, int reg, u32 value)
{
writel(value, timer->io_base + reg);
while (omap_dm_timer_read_reg(timer, OMAP_TIMER_WRITE_PEND_REG)) while (omap_dm_timer_read_reg(timer, OMAP_TIMER_WRITE_PEND_REG))
; ;
} }
u32 omap_dm_timer_read_reg(struct omap_dm_timer *timer, int reg) static void omap_dm_timer_wait_for_reset(struct omap_dm_timer *timer)
{ {
return omap_readl(timer->base + reg); int c;
c = 0;
while (!(omap_dm_timer_read_reg(timer, OMAP_TIMER_SYS_STAT_REG) & 1)) {
c++;
if (c > 100000) {
printk(KERN_ERR "Timer failed to reset\n");
return;
}
}
} }
int omap_dm_timers_active(void) static void omap_dm_timer_reset(struct omap_dm_timer *timer)
{
u32 l;
if (timer != &dm_timers[0]) {
omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 0x06);
omap_dm_timer_wait_for_reset(timer);
}
omap_dm_timer_set_source(timer, OMAP_TIMER_SRC_SYS_CLK);
/* Set to smart-idle mode */
l = omap_dm_timer_read_reg(timer, OMAP_TIMER_OCP_CFG_REG);
l |= 0x02 << 3;
omap_dm_timer_write_reg(timer, OMAP_TIMER_OCP_CFG_REG, l);
}
static void omap_dm_timer_prepare(struct omap_dm_timer *timer)
{
#ifdef CONFIG_ARCH_OMAP2
clk_enable(timer->iclk);
clk_enable(timer->fclk);
#endif
omap_dm_timer_reset(timer);
}
struct omap_dm_timer *omap_dm_timer_request(void)
{
struct omap_dm_timer *timer = NULL;
unsigned long flags;
int i;
spin_lock_irqsave(&dm_timer_lock, flags);
for (i = 0; i < dm_timer_count; i++) {
if (dm_timers[i].reserved)
continue;
timer = &dm_timers[i];
timer->reserved = 1;
break;
}
spin_unlock_irqrestore(&dm_timer_lock, flags);
if (timer != NULL)
omap_dm_timer_prepare(timer);
return timer;
}
struct omap_dm_timer *omap_dm_timer_request_specific(int id)
{ {
struct omap_dm_timer *timer; struct omap_dm_timer *timer;
unsigned long flags;
for (timer = &dm_timers[0]; timer->base; ++timer) spin_lock_irqsave(&dm_timer_lock, flags);
if (omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG) & if (id <= 0 || id > dm_timer_count || dm_timers[id-1].reserved) {
OMAP_TIMER_CTRL_ST) spin_unlock_irqrestore(&dm_timer_lock, flags);
return 1; printk("BUG: warning at %s:%d/%s(): unable to get timer %d\n",
__FILE__, __LINE__, __FUNCTION__, id);
dump_stack();
return NULL;
}
return 0; timer = &dm_timers[id-1];
timer->reserved = 1;
spin_unlock_irqrestore(&dm_timer_lock, flags);
omap_dm_timer_prepare(timer);
return timer;
} }
void omap_dm_timer_free(struct omap_dm_timer *timer)
{
omap_dm_timer_reset(timer);
#ifdef CONFIG_ARCH_OMAP2
clk_disable(timer->iclk);
clk_disable(timer->fclk);
#endif
WARN_ON(!timer->reserved);
timer->reserved = 0;
}
int omap_dm_timer_get_irq(struct omap_dm_timer *timer)
{
return timer->irq;
}
#if defined(CONFIG_ARCH_OMAP1)
struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer)
{
BUG();
}
/** /**
* omap_dm_timer_modify_idlect_mask - Check if any running timers use ARMXOR * omap_dm_timer_modify_idlect_mask - Check if any running timers use ARMXOR
@ -103,25 +250,70 @@ int omap_dm_timers_active(void)
*/ */
__u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask) __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask)
{ {
int n; int i;
/* If ARMXOR cannot be idled this function call is unnecessary */ /* If ARMXOR cannot be idled this function call is unnecessary */
if (!(inputmask & (1 << 1))) if (!(inputmask & (1 << 1)))
return inputmask; return inputmask;
/* If any active timer is using ARMXOR return modified mask */ /* If any active timer is using ARMXOR return modified mask */
for (n = 0; dm_timers[n].base; ++n) for (i = 0; i < dm_timer_count; i++) {
if (omap_dm_timer_read_reg(&dm_timers[n], OMAP_TIMER_CTRL_REG)& u32 l;
OMAP_TIMER_CTRL_ST) {
if (((omap_readl(MOD_CONF_CTRL_1)>>(n*2)) & 0x03) == 0) l = omap_dm_timer_read_reg(&dm_timers[i], OMAP_TIMER_CTRL_REG);
if (l & OMAP_TIMER_CTRL_ST) {
if (((omap_readl(MOD_CONF_CTRL_1) >> (i * 2)) & 0x03) == 0)
inputmask &= ~(1 << 1); inputmask &= ~(1 << 1);
else else
inputmask &= ~(1 << 2); inputmask &= ~(1 << 2);
} }
}
return inputmask; return inputmask;
} }
#elif defined(CONFIG_ARCH_OMAP2)
struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer)
{
return timer->fclk;
}
__u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask)
{
BUG();
}
#endif
void omap_dm_timer_trigger(struct omap_dm_timer *timer)
{
omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0);
}
void omap_dm_timer_start(struct omap_dm_timer *timer)
{
u32 l;
l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
if (!(l & OMAP_TIMER_CTRL_ST)) {
l |= OMAP_TIMER_CTRL_ST;
omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
}
}
void omap_dm_timer_stop(struct omap_dm_timer *timer)
{
u32 l;
l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
if (l & OMAP_TIMER_CTRL_ST) {
l &= ~0x1;
omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
}
}
#ifdef CONFIG_ARCH_OMAP1
void omap_dm_timer_set_source(struct omap_dm_timer *timer, int source) void omap_dm_timer_set_source(struct omap_dm_timer *timer, int source)
{ {
@ -133,49 +325,85 @@ void omap_dm_timer_set_source(struct omap_dm_timer *timer, int source)
omap_writel(l, MOD_CONF_CTRL_1); omap_writel(l, MOD_CONF_CTRL_1);
} }
#else
static void omap_dm_timer_reset(struct omap_dm_timer *timer) void omap_dm_timer_set_source(struct omap_dm_timer *timer, int source)
{ {
/* Reset and set posted mode */ if (source < 0 || source >= 3)
omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 0x06); return;
omap_dm_timer_write_reg(timer, OMAP_TIMER_OCP_CFG_REG, 0x02);
omap_dm_timer_set_source(timer, OMAP_TIMER_SRC_ARMXOR); clk_disable(timer->fclk);
clk_set_parent(timer->fclk, dm_source_clocks[source]);
clk_enable(timer->fclk);
/* When the functional clock disappears, too quick writes seem to
* cause an abort. */
__delay(15000);
}
#endif
void omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload,
unsigned int load)
{
u32 l;
l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
if (autoreload)
l |= OMAP_TIMER_CTRL_AR;
else
l &= ~OMAP_TIMER_CTRL_AR;
omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, load);
omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0);
}
void omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable,
unsigned int match)
{
u32 l;
l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
if (enable)
l |= OMAP_TIMER_CTRL_CE;
else
l &= ~OMAP_TIMER_CTRL_CE;
omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG, match);
} }
void omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on,
struct omap_dm_timer * omap_dm_timer_request(void) int toggle, int trigger)
{ {
struct omap_dm_timer *timer = NULL; u32 l;
unsigned long flags;
spin_lock_irqsave(&dm_timer_lock, flags); l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
if (!list_empty(&dm_timer_info.unused_timers)) { l &= ~(OMAP_TIMER_CTRL_GPOCFG | OMAP_TIMER_CTRL_SCPWM |
timer = (struct omap_dm_timer *) OMAP_TIMER_CTRL_PT | (0x03 << 10));
dm_timer_info.unused_timers.next; if (def_on)
list_move_tail((struct list_head *)timer, l |= OMAP_TIMER_CTRL_SCPWM;
&dm_timer_info.reserved_timers); if (toggle)
l |= OMAP_TIMER_CTRL_PT;
l |= trigger << 10;
omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
}
void omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler)
{
u32 l;
l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
l &= ~(OMAP_TIMER_CTRL_PRE | (0x07 << 2));
if (prescaler >= 0x00 && prescaler <= 0x07) {
l |= OMAP_TIMER_CTRL_PRE;
l |= prescaler << 2;
} }
spin_unlock_irqrestore(&dm_timer_lock, flags); omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
return timer;
}
void omap_dm_timer_free(struct omap_dm_timer *timer)
{
unsigned long flags;
omap_dm_timer_reset(timer);
spin_lock_irqsave(&dm_timer_lock, flags);
list_move_tail((struct list_head *)timer, &dm_timer_info.unused_timers);
spin_unlock_irqrestore(&dm_timer_lock, flags);
} }
void omap_dm_timer_set_int_enable(struct omap_dm_timer *timer, void omap_dm_timer_set_int_enable(struct omap_dm_timer *timer,
unsigned int value) unsigned int value)
{ {
omap_dm_timer_write_reg(timer, OMAP_TIMER_INT_EN_REG, value); omap_dm_timer_write_reg(timer, OMAP_TIMER_INT_EN_REG, value);
} }
@ -190,97 +418,61 @@ void omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value)
omap_dm_timer_write_reg(timer, OMAP_TIMER_STAT_REG, value); omap_dm_timer_write_reg(timer, OMAP_TIMER_STAT_REG, value);
} }
void omap_dm_timer_enable_autoreload(struct omap_dm_timer *timer)
{
u32 l;
l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
l |= OMAP_TIMER_CTRL_AR;
omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
}
void omap_dm_timer_trigger(struct omap_dm_timer *timer)
{
omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 1);
}
void omap_dm_timer_set_trigger(struct omap_dm_timer *timer, unsigned int value)
{
u32 l;
l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
l |= value & 0x3;
omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
}
void omap_dm_timer_start(struct omap_dm_timer *timer)
{
u32 l;
l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
l |= OMAP_TIMER_CTRL_ST;
omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
}
void omap_dm_timer_stop(struct omap_dm_timer *timer)
{
u32 l;
l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
l &= ~0x1;
omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
}
unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer) unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer)
{ {
return omap_dm_timer_read_reg(timer, OMAP_TIMER_COUNTER_REG); return omap_dm_timer_read_reg(timer, OMAP_TIMER_COUNTER_REG);
} }
void omap_dm_timer_reset_counter(struct omap_dm_timer *timer) void omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value)
{ {
omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG, 0); return omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG, value);
} }
void omap_dm_timer_set_load(struct omap_dm_timer *timer, unsigned int load) int omap_dm_timers_active(void)
{ {
omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, load); int i;
}
void omap_dm_timer_set_match(struct omap_dm_timer *timer, unsigned int match) for (i = 0; i < dm_timer_count; i++) {
{ struct omap_dm_timer *timer;
omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG, match);
}
void omap_dm_timer_enable_compare(struct omap_dm_timer *timer) timer = &dm_timers[i];
{ if (omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG) &
u32 l; OMAP_TIMER_CTRL_ST)
return 1;
l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
l |= OMAP_TIMER_CTRL_CE;
omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
}
static inline void __dm_timer_init(void)
{
struct omap_dm_timer *timer;
spin_lock_init(&dm_timer_lock);
INIT_LIST_HEAD(&dm_timer_info.unused_timers);
INIT_LIST_HEAD(&dm_timer_info.reserved_timers);
timer = &dm_timers[0];
while (timer->base) {
list_add_tail((struct list_head *)timer, &dm_timer_info.unused_timers);
omap_dm_timer_reset(timer);
timer++;
} }
}
static int __init omap_dm_timer_init(void)
{
if (cpu_is_omap16xx())
__dm_timer_init();
return 0; return 0;
} }
arch_initcall(omap_dm_timer_init); int omap_dm_timer_init(void)
{
struct omap_dm_timer *timer;
int i;
if (!(cpu_is_omap16xx() || cpu_is_omap24xx()))
return -ENODEV;
spin_lock_init(&dm_timer_lock);
#ifdef CONFIG_ARCH_OMAP2
for (i = 0; i < ARRAY_SIZE(dm_source_names); i++) {
dm_source_clocks[i] = clk_get(NULL, dm_source_names[i]);
BUG_ON(dm_source_clocks[i] == NULL);
}
#endif
for (i = 0; i < dm_timer_count; i++) {
#ifdef CONFIG_ARCH_OMAP2
char clk_name[16];
#endif
timer = &dm_timers[i];
timer->io_base = (void __iomem *) io_p2v(timer->phys_base);
#ifdef CONFIG_ARCH_OMAP2
sprintf(clk_name, "gpt%d_ick", i + 1);
timer->iclk = clk_get(NULL, clk_name);
sprintf(clk_name, "gpt%d_fck", i + 1);
timer->fclk = clk_get(NULL, clk_name);
#endif
}
return 0;
}

103
arch/arm/plat-omap/gpio.c
View File

@ -536,6 +536,49 @@ static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
_clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio)); _clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio));
} }
static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
{
void __iomem *reg = bank->base;
int inv = 0;
u32 l;
u32 mask;
switch (bank->method) {
case METHOD_MPUIO:
reg += OMAP_MPUIO_GPIO_MASKIT;
mask = 0xffff;
inv = 1;
break;
case METHOD_GPIO_1510:
reg += OMAP1510_GPIO_INT_MASK;
mask = 0xffff;
inv = 1;
break;
case METHOD_GPIO_1610:
reg += OMAP1610_GPIO_IRQENABLE1;
mask = 0xffff;
break;
case METHOD_GPIO_730:
reg += OMAP730_GPIO_INT_MASK;
mask = 0xffffffff;
inv = 1;
break;
case METHOD_GPIO_24XX:
reg += OMAP24XX_GPIO_IRQENABLE1;
mask = 0xffffffff;
break;
default:
BUG();
return 0;
}
l = __raw_readl(reg);
if (inv)
l = ~l;
l &= mask;
return l;
}
static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable) static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable)
{ {
void __iomem *reg = bank->base; void __iomem *reg = bank->base;
@ -735,6 +778,8 @@ static void gpio_irq_handler(unsigned int irq, struct irqdesc *desc,
u32 isr; u32 isr;
unsigned int gpio_irq; unsigned int gpio_irq;
struct gpio_bank *bank; struct gpio_bank *bank;
u32 retrigger = 0;
int unmasked = 0;
desc->chip->ack(irq); desc->chip->ack(irq);
@ -759,18 +804,22 @@ static void gpio_irq_handler(unsigned int irq, struct irqdesc *desc,
#endif #endif
while(1) { while(1) {
u32 isr_saved, level_mask = 0; u32 isr_saved, level_mask = 0;
u32 enabled;
isr_saved = isr = __raw_readl(isr_reg); enabled = _get_gpio_irqbank_mask(bank);
isr_saved = isr = __raw_readl(isr_reg) & enabled;
if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO)) if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
isr &= 0x0000ffff; isr &= 0x0000ffff;
if (cpu_is_omap24xx()) if (cpu_is_omap24xx()) {
level_mask = level_mask =
__raw_readl(bank->base + __raw_readl(bank->base +
OMAP24XX_GPIO_LEVELDETECT0) | OMAP24XX_GPIO_LEVELDETECT0) |
__raw_readl(bank->base + __raw_readl(bank->base +
OMAP24XX_GPIO_LEVELDETECT1); OMAP24XX_GPIO_LEVELDETECT1);
level_mask &= enabled;
}
/* clear edge sensitive interrupts before handler(s) are /* clear edge sensitive interrupts before handler(s) are
called so that we don't miss any interrupt occurred while called so that we don't miss any interrupt occurred while
@ -781,19 +830,54 @@ static void gpio_irq_handler(unsigned int irq, struct irqdesc *desc,
/* if there is only edge sensitive GPIO pin interrupts /* if there is only edge sensitive GPIO pin interrupts
configured, we could unmask GPIO bank interrupt immediately */ configured, we could unmask GPIO bank interrupt immediately */
if (!level_mask) if (!level_mask && !unmasked) {
unmasked = 1;
desc->chip->unmask(irq); desc->chip->unmask(irq);
}
isr |= retrigger;
retrigger = 0;
if (!isr) if (!isr)
break; break;
gpio_irq = bank->virtual_irq_start; gpio_irq = bank->virtual_irq_start;
for (; isr != 0; isr >>= 1, gpio_irq++) { for (; isr != 0; isr >>= 1, gpio_irq++) {
struct irqdesc *d; struct irqdesc *d;
int irq_mask;
if (!(isr & 1)) if (!(isr & 1))
continue; continue;
d = irq_desc + gpio_irq; d = irq_desc + gpio_irq;
/* Don't run the handler if it's already running
* or was disabled lazely.
*/
if (unlikely((d->disable_depth || d->running))) {
irq_mask = 1 <<
(gpio_irq - bank->virtual_irq_start);
/* The unmasking will be done by
* enable_irq in case it is disabled or
* after returning from the handler if
* it's already running.
*/
_enable_gpio_irqbank(bank, irq_mask, 0);
if (!d->disable_depth) {
/* Level triggered interrupts
* won't ever be reentered
*/
BUG_ON(level_mask & irq_mask);
d->pending = 1;
}
continue;
}
d->running = 1;
desc_handle_irq(gpio_irq, d, regs); desc_handle_irq(gpio_irq, d, regs);
d->running = 0;
if (unlikely(d->pending && !d->disable_depth)) {
irq_mask = 1 <<
(gpio_irq - bank->virtual_irq_start);
d->pending = 0;
_enable_gpio_irqbank(bank, irq_mask, 1);
retrigger |= irq_mask;
}
} }
if (cpu_is_omap24xx()) { if (cpu_is_omap24xx()) {
@ -803,13 +887,14 @@ static void gpio_irq_handler(unsigned int irq, struct irqdesc *desc,
_enable_gpio_irqbank(bank, isr_saved & level_mask, 1); _enable_gpio_irqbank(bank, isr_saved & level_mask, 1);
} }
/* if bank has any level sensitive GPIO pin interrupt
configured, we must unmask the bank interrupt only after
handler(s) are executed in order to avoid spurious bank
interrupt */
if (level_mask)
desc->chip->unmask(irq);
} }
/* if bank has any level sensitive GPIO pin interrupt
configured, we must unmask the bank interrupt only after
handler(s) are executed in order to avoid spurious bank
interrupt */
if (!unmasked)
desc->chip->unmask(irq);
} }
static void gpio_ack_irq(unsigned int irq) static void gpio_ack_irq(unsigned int irq)

9
arch/arm/plat-omap/sram.c
View File

@ -157,14 +157,12 @@ static struct map_desc omap_sram_io_desc[] __initdata = {
{ /* .length gets filled in at runtime */ { /* .length gets filled in at runtime */
.virtual = OMAP1_SRAM_VA, .virtual = OMAP1_SRAM_VA,
.pfn = __phys_to_pfn(OMAP1_SRAM_PA), .pfn = __phys_to_pfn(OMAP1_SRAM_PA),
.type = MT_DEVICE .type = MT_MEMORY
} }
}; };
/* /*
* In order to use last 2kB of SRAM on 1611b, we must round the size * Note that we cannot use ioremap for SRAM, as clock init needs SRAM early.
* up to multiple of PAGE_SIZE. We cannot use ioremap for SRAM, as
* clock init needs SRAM early.
*/ */
void __init omap_map_sram(void) void __init omap_map_sram(void)
{ {
@ -184,8 +182,7 @@ void __init omap_map_sram(void)
omap_sram_io_desc[0].pfn = __phys_to_pfn(base); omap_sram_io_desc[0].pfn = __phys_to_pfn(base);
} }
omap_sram_io_desc[0].length = (omap_sram_size + PAGE_SIZE-1)/PAGE_SIZE; omap_sram_io_desc[0].length = 1024 * 1024; /* Use section desc */
omap_sram_io_desc[0].length *= PAGE_SIZE;
iotable_init(omap_sram_io_desc, ARRAY_SIZE(omap_sram_io_desc)); iotable_init(omap_sram_io_desc, ARRAY_SIZE(omap_sram_io_desc));
printk(KERN_INFO "SRAM: Mapped pa 0x%08lx to va 0x%08lx size: 0x%lx\n", printk(KERN_INFO "SRAM: Mapped pa 0x%08lx to va 0x%08lx size: 0x%lx\n",

128
arch/arm/plat-omap/timer32k.c
View File

@ -7,6 +7,7 @@
* Partial timer rewrite and additional dynamic tick timer support by * Partial timer rewrite and additional dynamic tick timer support by
* Tony Lindgen <tony@atomide.com> and * Tony Lindgen <tony@atomide.com> and
* Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com> * Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
* OMAP Dual-mode timer framework support by Timo Teras
* *
* MPU timer code based on the older MPU timer code for OMAP * MPU timer code based on the older MPU timer code for OMAP
* Copyright (C) 2000 RidgeRun, Inc. * Copyright (C) 2000 RidgeRun, Inc.
@ -49,6 +50,7 @@
#include <asm/irq.h> #include <asm/irq.h>
#include <asm/mach/irq.h> #include <asm/mach/irq.h>
#include <asm/mach/time.h> #include <asm/mach/time.h>
#include <asm/arch/dmtimer.h>
struct sys_timer omap_timer; struct sys_timer omap_timer;
@ -78,18 +80,6 @@ struct sys_timer omap_timer;
#define OMAP1_32K_TIMER_TVR 0x00 #define OMAP1_32K_TIMER_TVR 0x00
#define OMAP1_32K_TIMER_TCR 0x04 #define OMAP1_32K_TIMER_TCR 0x04
/* 24xx specific defines */
#define OMAP2_GP_TIMER_BASE 0x48028000
#define CM_CLKSEL_WKUP 0x48008440
#define GP_TIMER_TIDR 0x00
#define GP_TIMER_TISR 0x18
#define GP_TIMER_TIER 0x1c
#define GP_TIMER_TCLR 0x24
#define GP_TIMER_TCRR 0x28
#define GP_TIMER_TLDR 0x2c
#define GP_TIMER_TTGR 0x30
#define GP_TIMER_TSICR 0x40
#define OMAP_32K_TICKS_PER_HZ (32768 / HZ) #define OMAP_32K_TICKS_PER_HZ (32768 / HZ)
/* /*
@ -101,24 +91,55 @@ struct sys_timer omap_timer;
#define JIFFIES_TO_HW_TICKS(nr_jiffies, clock_rate) \ #define JIFFIES_TO_HW_TICKS(nr_jiffies, clock_rate) \
(((nr_jiffies) * (clock_rate)) / HZ) (((nr_jiffies) * (clock_rate)) / HZ)
#if defined(CONFIG_ARCH_OMAP1)
static inline void omap_32k_timer_write(int val, int reg) static inline void omap_32k_timer_write(int val, int reg)
{ {
if (cpu_class_is_omap1()) omap_writew(val, OMAP1_32K_TIMER_BASE + reg);
omap_writew(val, OMAP1_32K_TIMER_BASE + reg);
if (cpu_is_omap24xx())
omap_writel(val, OMAP2_GP_TIMER_BASE + reg);
} }
static inline unsigned long omap_32k_timer_read(int reg) static inline unsigned long omap_32k_timer_read(int reg)
{ {
if (cpu_class_is_omap1()) return omap_readl(OMAP1_32K_TIMER_BASE + reg) & 0xffffff;
return omap_readl(OMAP1_32K_TIMER_BASE + reg) & 0xffffff;
if (cpu_is_omap24xx())
return omap_readl(OMAP2_GP_TIMER_BASE + reg);
} }
static inline void omap_32k_timer_start(unsigned long load_val)
{
omap_32k_timer_write(load_val, OMAP1_32K_TIMER_TVR);
omap_32k_timer_write(0x0f, OMAP1_32K_TIMER_CR);
}
static inline void omap_32k_timer_stop(void)
{
omap_32k_timer_write(0x0, OMAP1_32K_TIMER_CR);
}
#define omap_32k_timer_ack_irq()
#elif defined(CONFIG_ARCH_OMAP2)
static struct omap_dm_timer *gptimer;
static inline void omap_32k_timer_start(unsigned long load_val)
{
omap_dm_timer_set_load(gptimer, 1, 0xffffffff - load_val);
omap_dm_timer_set_int_enable(gptimer, OMAP_TIMER_INT_OVERFLOW);
omap_dm_timer_start(gptimer);
}
static inline void omap_32k_timer_stop(void)
{
omap_dm_timer_stop(gptimer);
}
static inline void omap_32k_timer_ack_irq(void)
{
u32 status = omap_dm_timer_read_status(gptimer);
omap_dm_timer_write_status(gptimer, status);
}
#endif
/* /*
* The 32KHz synchronized timer is an additional timer on 16xx. * The 32KHz synchronized timer is an additional timer on 16xx.
* It is always running. * It is always running.
@ -128,29 +149,6 @@ static inline unsigned long omap_32k_sync_timer_read(void)
return omap_readl(TIMER_32K_SYNCHRONIZED); return omap_readl(TIMER_32K_SYNCHRONIZED);
} }
static inline void omap_32k_timer_start(unsigned long load_val)
{
if (cpu_class_is_omap1()) {
omap_32k_timer_write(load_val, OMAP1_32K_TIMER_TVR);
omap_32k_timer_write(0x0f, OMAP1_32K_TIMER_CR);
}
if (cpu_is_omap24xx()) {
omap_32k_timer_write(0xffffffff - load_val, GP_TIMER_TCRR);
omap_32k_timer_write((1 << 1), GP_TIMER_TIER);
omap_32k_timer_write((1 << 1) | 1, GP_TIMER_TCLR);
}
}
static inline void omap_32k_timer_stop(void)
{
if (cpu_class_is_omap1())
omap_32k_timer_write(0x0, OMAP1_32K_TIMER_CR);
if (cpu_is_omap24xx())
omap_32k_timer_write(0x0, GP_TIMER_TCLR);
}
/* /*
* Rounds down to nearest usec. Note that this will overflow for larger values. * Rounds down to nearest usec. Note that this will overflow for larger values.
*/ */
@ -202,11 +200,7 @@ static irqreturn_t omap_32k_timer_interrupt(int irq, void *dev_id,
write_seqlock_irqsave(&xtime_lock, flags); write_seqlock_irqsave(&xtime_lock, flags);
if (cpu_is_omap24xx()) { omap_32k_timer_ack_irq();
u32 status = omap_32k_timer_read(GP_TIMER_TISR);
omap_32k_timer_write(status, GP_TIMER_TISR);
}
now = omap_32k_sync_timer_read(); now = omap_32k_sync_timer_read();
while ((signed long)(now - omap_32k_last_tick) while ((signed long)(now - omap_32k_last_tick)
@ -268,9 +262,6 @@ static struct irqaction omap_32k_timer_irq = {
.handler = omap_32k_timer_interrupt, .handler = omap_32k_timer_interrupt,
}; };
static struct clk * gpt1_ick;
static struct clk * gpt1_fck;
static __init void omap_init_32k_timer(void) static __init void omap_init_32k_timer(void)
{ {
#ifdef CONFIG_NO_IDLE_HZ #ifdef CONFIG_NO_IDLE_HZ
@ -279,32 +270,22 @@ static __init void omap_init_32k_timer(void)
if (cpu_class_is_omap1()) if (cpu_class_is_omap1())
setup_irq(INT_OS_TIMER, &omap_32k_timer_irq); setup_irq(INT_OS_TIMER, &omap_32k_timer_irq);
if (cpu_is_omap24xx())
setup_irq(37, &omap_32k_timer_irq);
omap_timer.offset = omap_32k_timer_gettimeoffset; omap_timer.offset = omap_32k_timer_gettimeoffset;
omap_32k_last_tick = omap_32k_sync_timer_read(); omap_32k_last_tick = omap_32k_sync_timer_read();
#ifdef CONFIG_ARCH_OMAP2
/* REVISIT: Check 24xx TIOCP_CFG settings after idle works */ /* REVISIT: Check 24xx TIOCP_CFG settings after idle works */
if (cpu_is_omap24xx()) { if (cpu_is_omap24xx()) {
omap_32k_timer_write(0, GP_TIMER_TCLR); gptimer = omap_dm_timer_request_specific(1);
omap_writel(0, CM_CLKSEL_WKUP); /* 32KHz clock source */ BUG_ON(gptimer == NULL);
gpt1_ick = clk_get(NULL, "gpt1_ick"); omap_dm_timer_set_source(gptimer, OMAP_TIMER_SRC_32_KHZ);
if (IS_ERR(gpt1_ick)) setup_irq(omap_dm_timer_get_irq(gptimer), &omap_32k_timer_irq);
printk(KERN_ERR "Could not get gpt1_ick\n"); omap_dm_timer_set_int_enable(gptimer,
else OMAP_TIMER_INT_CAPTURE | OMAP_TIMER_INT_OVERFLOW |
clk_enable(gpt1_ick); OMAP_TIMER_INT_MATCH);
gpt1_fck = clk_get(NULL, "gpt1_fck");
if (IS_ERR(gpt1_fck))
printk(KERN_ERR "Could not get gpt1_fck\n");
else
clk_enable(gpt1_fck);
mdelay(100); /* Wait for clocks to stabilize */
omap_32k_timer_write(0x7, GP_TIMER_TISR);
} }
#endif
omap_32k_timer_start(OMAP_32K_TIMER_TICK_PERIOD); omap_32k_timer_start(OMAP_32K_TIMER_TICK_PERIOD);
} }
@ -316,6 +297,9 @@ static __init void omap_init_32k_timer(void)
*/ */
static void __init omap_timer_init(void) static void __init omap_timer_init(void)
{ {
#ifdef CONFIG_OMAP_DM_TIMER
omap_dm_timer_init();
#endif
omap_init_32k_timer(); omap_init_32k_timer();
} }

43
drivers/mmc/omap.c
View File

@ -60,6 +60,7 @@ struct mmc_omap_host {
unsigned char id; /* 16xx chips have 2 MMC blocks */ unsigned char id; /* 16xx chips have 2 MMC blocks */
struct clk * iclk; struct clk * iclk;
struct clk * fclk; struct clk * fclk;
struct resource *res;
void __iomem *base; void __iomem *base;
int irq; int irq;
unsigned char bus_mode; unsigned char bus_mode;
@ -339,8 +340,6 @@ static void
mmc_omap_xfer_data(struct mmc_omap_host *host, int write) mmc_omap_xfer_data(struct mmc_omap_host *host, int write)
{ {
int n; int n;
void __iomem *reg;
u16 *p;
if (host->buffer_bytes_left == 0) { if (host->buffer_bytes_left == 0) {
host->sg_idx++; host->sg_idx++;
@ -657,12 +656,12 @@ static void mmc_omap_dma_cb(int lch, u16 ch_status, void *data)
struct mmc_data *mmcdat = host->data; struct mmc_data *mmcdat = host->data;
if (unlikely(host->dma_ch < 0)) { if (unlikely(host->dma_ch < 0)) {
dev_err(mmc_dev(host->mmc), "DMA callback while DMA not dev_err(mmc_dev(host->mmc),
enabled\n"); "DMA callback while DMA not enabled\n");
return; return;
} }
/* FIXME: We really should do something to _handle_ the errors */ /* FIXME: We really should do something to _handle_ the errors */
if (ch_status & OMAP_DMA_TOUT_IRQ) { if (ch_status & OMAP1_DMA_TOUT_IRQ) {
dev_err(mmc_dev(host->mmc),"DMA timeout\n"); dev_err(mmc_dev(host->mmc),"DMA timeout\n");
return; return;
} }
@ -972,20 +971,20 @@ static int __init mmc_omap_probe(struct platform_device *pdev)
struct omap_mmc_conf *minfo = pdev->dev.platform_data; struct omap_mmc_conf *minfo = pdev->dev.platform_data;
struct mmc_host *mmc; struct mmc_host *mmc;
struct mmc_omap_host *host = NULL; struct mmc_omap_host *host = NULL;
struct resource *r;
int ret = 0; int ret = 0;
int irq;
if (platform_get_resource(pdev, IORESOURCE_MEM, 0) || r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
platform_get_irq(pdev, IORESOURCE_IRQ, 0)) { irq = platform_get_irq(pdev, 0);
dev_err(&pdev->dev, "mmc_omap_probe: invalid resource type\n"); if (!r || irq < 0)
return -ENODEV; return -ENXIO;
}
if (!request_mem_region(pdev->resource[0].start, r = request_mem_region(pdev->resource[0].start,
pdev->resource[0].end - pdev->resource[0].start + 1, pdev->resource[0].end - pdev->resource[0].start + 1,
pdev->name)) { pdev->name);
dev_dbg(&pdev->dev, "request_mem_region failed\n"); if (!r)
return -EBUSY; return -EBUSY;
}
mmc = mmc_alloc_host(sizeof(struct mmc_omap_host), &pdev->dev); mmc = mmc_alloc_host(sizeof(struct mmc_omap_host), &pdev->dev);
if (!mmc) { if (!mmc) {
@ -1002,6 +1001,8 @@ static int __init mmc_omap_probe(struct platform_device *pdev)
host->dma_timer.data = (unsigned long) host; host->dma_timer.data = (unsigned long) host;
host->id = pdev->id; host->id = pdev->id;
host->res = r;
host->irq = irq;
if (cpu_is_omap24xx()) { if (cpu_is_omap24xx()) {
host->iclk = clk_get(&pdev->dev, "mmc_ick"); host->iclk = clk_get(&pdev->dev, "mmc_ick");
@ -1031,13 +1032,9 @@ static int __init mmc_omap_probe(struct platform_device *pdev)
host->dma_ch = -1; host->dma_ch = -1;
host->irq = pdev->resource[1].start; host->irq = pdev->resource[1].start;
host->base = ioremap(pdev->res.start, SZ_4K); host->base = (void __iomem*)IO_ADDRESS(r->start);
if (!host->base) {
ret = -ENOMEM;
goto out;
}
if (minfo->wire4) if (minfo->wire4)
mmc->caps |= MMC_CAP_4_BIT_DATA; mmc->caps |= MMC_CAP_4_BIT_DATA;
mmc->ops = &mmc_omap_ops; mmc->ops = &mmc_omap_ops;
@ -1056,8 +1053,8 @@ static int __init mmc_omap_probe(struct platform_device *pdev)
if (host->power_pin >= 0) { if (host->power_pin >= 0) {
if ((ret = omap_request_gpio(host->power_pin)) != 0) { if ((ret = omap_request_gpio(host->power_pin)) != 0) {
dev_err(mmc_dev(host->mmc), "Unable to get GPIO dev_err(mmc_dev(host->mmc),
pin for MMC power\n"); "Unable to get GPIO pin for MMC power\n");
goto out; goto out;
} }
omap_set_gpio_direction(host->power_pin, 0); omap_set_gpio_direction(host->power_pin, 0);
@ -1099,7 +1096,7 @@ static int __init mmc_omap_probe(struct platform_device *pdev)
device_remove_file(&pdev->dev, &dev_attr_cover_switch); device_remove_file(&pdev->dev, &dev_attr_cover_switch);
} }
if (ret) { if (ret) {
dev_wan(mmc_dev(host->mmc), "Unable to create sysfs attributes\n"); dev_warn(mmc_dev(host->mmc), "Unable to create sysfs attributes\n");
free_irq(OMAP_GPIO_IRQ(host->switch_pin), host); free_irq(OMAP_GPIO_IRQ(host->switch_pin), host);
omap_free_gpio(host->switch_pin); omap_free_gpio(host->switch_pin);
host->switch_pin = -1; host->switch_pin = -1;

2
drivers/usb/gadget/omap_udc.c
View File

@ -772,7 +772,7 @@ static void dma_error(int lch, u16 ch_status, void *data)
struct omap_ep *ep = data; struct omap_ep *ep = data;
/* if ch_status & OMAP_DMA_DROP_IRQ ... */ /* if ch_status & OMAP_DMA_DROP_IRQ ... */
/* if ch_status & OMAP_DMA_TOUT_IRQ ... */ /* if ch_status & OMAP1_DMA_TOUT_IRQ ... */
ERR("%s dma error, lch %d status %02x\n", ep->ep.name, lch, ch_status); ERR("%s dma error, lch %d status %02x\n", ep->ep.name, lch, ch_status);
/* complete current transfer ... */ /* complete current transfer ... */

51
include/asm-arm/arch-omap/board-fsample.h Normal file
View File

@ -0,0 +1,51 @@
/*
* linux/include/asm-arm/arch-omap/board-fsample.h
*
* Board-specific goodies for TI F-Sample.
*
* Copyright (C) 2006 Google, Inc.
* Author: Brian Swetland <swetland@google.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_OMAP_FSAMPLE_H
#define __ASM_ARCH_OMAP_FSAMPLE_H
/* fsample is pretty close to p2-sample */
#include <asm/arch/board-perseus2.h>
#define fsample_cpld_read(reg) __raw_readb(reg)
#define fsample_cpld_write(val, reg) __raw_writeb(val, reg)
#define FSAMPLE_CPLD_BASE 0xE8100000
#define FSAMPLE_CPLD_SIZE SZ_4K
#define FSAMPLE_CPLD_START 0x05080000
#define FSAMPLE_CPLD_REG_A (FSAMPLE_CPLD_BASE + 0x00)
#define FSAMPLE_CPLD_SWITCH (FSAMPLE_CPLD_BASE + 0x02)
#define FSAMPLE_CPLD_UART (FSAMPLE_CPLD_BASE + 0x02)
#define FSAMPLE_CPLD_REG_B (FSAMPLE_CPLD_BASE + 0x04)
#define FSAMPLE_CPLD_VERSION (FSAMPLE_CPLD_BASE + 0x06)
#define FSAMPLE_CPLD_SET_CLR (FSAMPLE_CPLD_BASE + 0x06)
#define FSAMPLE_CPLD_BIT_BT_RESET 0
#define FSAMPLE_CPLD_BIT_LCD_RESET 1
#define FSAMPLE_CPLD_BIT_CAM_PWDN 2
#define FSAMPLE_CPLD_BIT_CHARGER_ENABLE 3
#define FSAMPLE_CPLD_BIT_SD_MMC_EN 4
#define FSAMPLE_CPLD_BIT_aGPS_PWREN 5
#define FSAMPLE_CPLD_BIT_BACKLIGHT 6
#define FSAMPLE_CPLD_BIT_aGPS_EN_RESET 7
#define FSAMPLE_CPLD_BIT_aGPS_SLEEPx_N 8
#define FSAMPLE_CPLD_BIT_OTG_RESET 9
#define fsample_cpld_set(bit) \
fsample_cpld_write((((bit) & 15) << 4) | 0x0f, FSAMPLE_CPLD_SET_CLR)
#define fsample_cpld_clear(bit) \
fsample_cpld_write(0xf0 | ((bit) & 15), FSAMPLE_CPLD_SET_CLR)
#endif

7
include/asm-arm/arch-omap/board.h
View File

@ -22,6 +22,7 @@
#define OMAP_TAG_UART 0x4f07 #define OMAP_TAG_UART 0x4f07
#define OMAP_TAG_FBMEM 0x4f08 #define OMAP_TAG_FBMEM 0x4f08
#define OMAP_TAG_STI_CONSOLE 0x4f09 #define OMAP_TAG_STI_CONSOLE 0x4f09
#define OMAP_TAG_CAMERA_SENSOR 0x4f0a
#define OMAP_TAG_BOOT_REASON 0x4f80 #define OMAP_TAG_BOOT_REASON 0x4f80
#define OMAP_TAG_FLASH_PART 0x4f81 #define OMAP_TAG_FLASH_PART 0x4f81
@ -61,6 +62,12 @@ struct omap_sti_console_config {
u8 channel; u8 channel;
}; };
struct omap_camera_sensor_config {
u16 reset_gpio;
int (*power_on)(void * data);
int (*power_off)(void * data);
};
struct omap_usb_config { struct omap_usb_config {
/* Configure drivers according to the connectors on your board: /* Configure drivers according to the connectors on your board:
* - "A" connector (rectagular) * - "A" connector (rectagular)

15
include/asm-arm/arch-omap/dma.h
View File

@ -185,8 +185,8 @@
/* DMA channels for 24xx */ /* DMA channels for 24xx */
#define OMAP24XX_DMA_NO_DEVICE 0 #define OMAP24XX_DMA_NO_DEVICE 0
#define OMAP24XX_DMA_XTI_DMA 1 /* S_DMA_0 */ #define OMAP24XX_DMA_XTI_DMA 1 /* S_DMA_0 */
#define OMAP24XX_DMA_EXT_NDMA_REQ0 2 /* S_DMA_1 */ #define OMAP24XX_DMA_EXT_DMAREQ0 2 /* S_DMA_1 */
#define OMAP24XX_DMA_EXT_NDMA_REQ1 3 /* S_DMA_2 */ #define OMAP24XX_DMA_EXT_DMAREQ1 3 /* S_DMA_2 */
#define OMAP24XX_DMA_GPMC 4 /* S_DMA_3 */ #define OMAP24XX_DMA_GPMC 4 /* S_DMA_3 */
#define OMAP24XX_DMA_GFX 5 /* S_DMA_4 */ #define OMAP24XX_DMA_GFX 5 /* S_DMA_4 */
#define OMAP24XX_DMA_DSS 6 /* S_DMA_5 */ #define OMAP24XX_DMA_DSS 6 /* S_DMA_5 */
@ -197,7 +197,9 @@
#define OMAP24XX_DMA_DES_TX 11 /* S_DMA_10 */ #define OMAP24XX_DMA_DES_TX 11 /* S_DMA_10 */
#define OMAP24XX_DMA_DES_RX 12 /* S_DMA_11 */ #define OMAP24XX_DMA_DES_RX 12 /* S_DMA_11 */
#define OMAP24XX_DMA_SHA1MD5_RX 13 /* S_DMA_12 */ #define OMAP24XX_DMA_SHA1MD5_RX 13 /* S_DMA_12 */
#define OMAP24XX_DMA_EXT_DMAREQ2 14 /* S_DMA_13 */
#define OMAP24XX_DMA_EXT_DMAREQ3 15 /* S_DMA_14 */
#define OMAP24XX_DMA_EXT_DMAREQ4 16 /* S_DMA_15 */
#define OMAP24XX_DMA_EAC_AC_RD 17 /* S_DMA_16 */ #define OMAP24XX_DMA_EAC_AC_RD 17 /* S_DMA_16 */
#define OMAP24XX_DMA_EAC_AC_WR 18 /* S_DMA_17 */ #define OMAP24XX_DMA_EAC_AC_WR 18 /* S_DMA_17 */
#define OMAP24XX_DMA_EAC_MD_UL_RD 19 /* S_DMA_18 */ #define OMAP24XX_DMA_EAC_MD_UL_RD 19 /* S_DMA_18 */
@ -244,6 +246,7 @@
#define OMAP24XX_DMA_MMC1_TX 61 /* SDMA_60 */ #define OMAP24XX_DMA_MMC1_TX 61 /* SDMA_60 */
#define OMAP24XX_DMA_MMC1_RX 62 /* SDMA_61 */ #define OMAP24XX_DMA_MMC1_RX 62 /* SDMA_61 */
#define OMAP24XX_DMA_MS 63 /* SDMA_62 */ #define OMAP24XX_DMA_MS 63 /* SDMA_62 */
#define OMAP24XX_DMA_EXT_DMAREQ5 64 /* S_DMA_63 */
/*----------------------------------------------------------------------------*/ /*----------------------------------------------------------------------------*/
@ -274,7 +277,7 @@
#define OMAP1610_DMA_LCD_LCH_CTRL (OMAP1610_DMA_LCD_BASE + 0xea) #define OMAP1610_DMA_LCD_LCH_CTRL (OMAP1610_DMA_LCD_BASE + 0xea)
#define OMAP1610_DMA_LCD_SRC_FI_B1_U (OMAP1610_DMA_LCD_BASE + 0xf4) #define OMAP1610_DMA_LCD_SRC_FI_B1_U (OMAP1610_DMA_LCD_BASE + 0xf4)
#define OMAP_DMA_TOUT_IRQ (1 << 0) /* Only on omap1 */ #define OMAP1_DMA_TOUT_IRQ (1 << 0)
#define OMAP_DMA_DROP_IRQ (1 << 1) #define OMAP_DMA_DROP_IRQ (1 << 1)
#define OMAP_DMA_HALF_IRQ (1 << 2) #define OMAP_DMA_HALF_IRQ (1 << 2)
#define OMAP_DMA_FRAME_IRQ (1 << 3) #define OMAP_DMA_FRAME_IRQ (1 << 3)
@ -315,11 +318,11 @@ enum {
OMAP_LCD_DMA_B2_BOTTOM OMAP_LCD_DMA_B2_BOTTOM
}; };
/* REVISIT: Check if BURST_4 is really 1 (or 2) */
enum omap_dma_burst_mode { enum omap_dma_burst_mode {
OMAP_DMA_DATA_BURST_DIS = 0, OMAP_DMA_DATA_BURST_DIS = 0,
OMAP_DMA_DATA_BURST_4, OMAP_DMA_DATA_BURST_4,
OMAP_DMA_DATA_BURST_8 OMAP_DMA_DATA_BURST_8,
OMAP_DMA_DATA_BURST_16,
}; };
enum omap_dma_color_mode { enum omap_dma_color_mode {

78
include/asm-arm/arch-omap/dmtimer.h
View File

@ -5,6 +5,7 @@
* *
* Copyright (C) 2005 Nokia Corporation * Copyright (C) 2005 Nokia Corporation
* Author: Lauri Leukkunen <lauri.leukkunen@nokia.com> * Author: Lauri Leukkunen <lauri.leukkunen@nokia.com>
* PWM and clock framwork support by Timo Teras.
* *
* This program is free software; you can redistribute it and/or modify it * This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the * under the terms of the GNU General Public License as published by the
@ -25,69 +26,56 @@
* 675 Mass Ave, Cambridge, MA 02139, USA. * 675 Mass Ave, Cambridge, MA 02139, USA.
*/ */
#ifndef __ASM_ARCH_TIMER_H #ifndef __ASM_ARCH_DMTIMER_H
#define __ASM_ARCH_TIMER_H #define __ASM_ARCH_DMTIMER_H
#include <linux/list.h> /* clock sources */
#define OMAP_TIMER_SRC_SYS_CLK 0x00
#define OMAP_TIMER_SRC_ARMXOR 0x00 #define OMAP_TIMER_SRC_32_KHZ 0x01
#define OMAP_TIMER_SRC_32_KHZ 0x01 #define OMAP_TIMER_SRC_EXT_CLK 0x02
#define OMAP_TIMER_SRC_EXT_CLK 0x02
/* timer control reg bits */
#define OMAP_TIMER_CTRL_CAPTMODE (1 << 13)
#define OMAP_TIMER_CTRL_PT (1 << 12)
#define OMAP_TIMER_CTRL_TRG_OVERFLOW (0x1 << 10)
#define OMAP_TIMER_CTRL_TRG_OFANDMATCH (0x2 << 10)
#define OMAP_TIMER_CTRL_TCM_LOWTOHIGH (0x1 << 8)
#define OMAP_TIMER_CTRL_TCM_HIGHTOLOW (0x2 << 8)
#define OMAP_TIMER_CTRL_TCM_BOTHEDGES (0x3 << 8)
#define OMAP_TIMER_CTRL_SCPWM (1 << 7)
#define OMAP_TIMER_CTRL_CE (1 << 6) /* compare enable */
#define OMAP_TIMER_CTRL_PRE (1 << 5) /* prescaler enable */
#define OMAP_TIMER_CTRL_PTV_SHIFT 2 /* how much to shift the prescaler value */
#define OMAP_TIMER_CTRL_AR (1 << 1) /* auto-reload enable */
#define OMAP_TIMER_CTRL_ST (1 << 0) /* start timer */
/* timer interrupt enable bits */ /* timer interrupt enable bits */
#define OMAP_TIMER_INT_CAPTURE (1 << 2) #define OMAP_TIMER_INT_CAPTURE (1 << 2)
#define OMAP_TIMER_INT_OVERFLOW (1 << 1) #define OMAP_TIMER_INT_OVERFLOW (1 << 1)
#define OMAP_TIMER_INT_MATCH (1 << 0) #define OMAP_TIMER_INT_MATCH (1 << 0)
/* trigger types */
#define OMAP_TIMER_TRIGGER_NONE 0x00
#define OMAP_TIMER_TRIGGER_OVERFLOW 0x01
#define OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE 0x02
struct omap_dm_timer { struct omap_dm_timer;
struct list_head timer_list; struct clk;
u32 base; int omap_dm_timer_init(void);
unsigned int irq;
};
u32 omap_dm_timer_read_reg(struct omap_dm_timer *timer, int reg); struct omap_dm_timer *omap_dm_timer_request(void);
void omap_dm_timer_write_reg(struct omap_dm_timer *timer, int reg, u32 value); struct omap_dm_timer *omap_dm_timer_request_specific(int timer_id);
struct omap_dm_timer * omap_dm_timer_request(void);
void omap_dm_timer_free(struct omap_dm_timer *timer); void omap_dm_timer_free(struct omap_dm_timer *timer);
void omap_dm_timer_set_source(struct omap_dm_timer *timer, int source);
void omap_dm_timer_set_int_enable(struct omap_dm_timer *timer, unsigned int value); int omap_dm_timer_get_irq(struct omap_dm_timer *timer);
void omap_dm_timer_set_trigger(struct omap_dm_timer *timer, unsigned int value);
void omap_dm_timer_enable_compare(struct omap_dm_timer *timer); u32 omap_dm_timer_modify_idlect_mask(u32 inputmask);
void omap_dm_timer_enable_autoreload(struct omap_dm_timer *timer); struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer);
void omap_dm_timer_trigger(struct omap_dm_timer *timer); void omap_dm_timer_trigger(struct omap_dm_timer *timer);
void omap_dm_timer_start(struct omap_dm_timer *timer); void omap_dm_timer_start(struct omap_dm_timer *timer);
void omap_dm_timer_stop(struct omap_dm_timer *timer); void omap_dm_timer_stop(struct omap_dm_timer *timer);
void omap_dm_timer_set_load(struct omap_dm_timer *timer, unsigned int load); void omap_dm_timer_set_source(struct omap_dm_timer *timer, int source);
void omap_dm_timer_set_match(struct omap_dm_timer *timer, unsigned int match); void omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload, unsigned int value);
void omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable, unsigned int match);
void omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on, int toggle, int trigger);
void omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler);
void omap_dm_timer_set_int_enable(struct omap_dm_timer *timer, unsigned int value);
unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer); unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer);
void omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value); void omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value);
unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer); unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer);
void omap_dm_timer_reset_counter(struct omap_dm_timer *timer); void omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value);
int omap_dm_timers_active(void); int omap_dm_timers_active(void);
u32 omap_dm_timer_modify_idlect_mask(u32 inputmask);
#endif /* __ASM_ARCH_TIMER_H */
#endif /* __ASM_ARCH_DMTIMER_H */

91
include/asm-arm/arch-omap/gpmc.h Normal file
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@ -0,0 +1,91 @@
/*
* General-Purpose Memory Controller for OMAP2
*
* Copyright (C) 2005-2006 Nokia Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __OMAP2_GPMC_H
#define __OMAP2_GPMC_H
#define GPMC_CS_CONFIG1 0x00
#define GPMC_CS_CONFIG2 0x04
#define GPMC_CS_CONFIG3 0x08
#define GPMC_CS_CONFIG4 0x0c
#define GPMC_CS_CONFIG5 0x10
#define GPMC_CS_CONFIG6 0x14
#define GPMC_CS_CONFIG7 0x18
#define GPMC_CS_NAND_COMMAND 0x1c
#define GPMC_CS_NAND_ADDRESS 0x20
#define GPMC_CS_NAND_DATA 0x24
#define GPMC_CONFIG1_WRAPBURST_SUPP (1 << 31)
#define GPMC_CONFIG1_READMULTIPLE_SUPP (1 << 20)
#define GPMC_CONFIG1_READTYPE_ASYNC (0 << 29)
#define GPMC_CONFIG1_READTYPE_SYNC (1 << 29)
#define GPMC_CONFIG1_WRITETYPE_ASYNC (0 << 27)
#define GPMC_CONFIG1_WRITETYPE_SYNC (1 << 27)
#define GPMC_CONFIG1_CLKACTIVATIONTIME(val) ((val & 3) << 25)
#define GPMC_CONFIG1_PAGE_LEN(val) ((val & 3) << 23)
#define GPMC_CONFIG1_WAIT_READ_MON (1 << 22)
#define GPMC_CONFIG1_WAIT_WRITE_MON (1 << 21)
#define GPMC_CONFIG1_WAIT_MON_IIME(val) ((val & 3) << 18)
#define GPMC_CONFIG1_WAIT_PIN_SEL(val) ((val & 3) << 16)
#define GPMC_CONFIG1_DEVICESIZE(val) ((val & 3) << 12)
#define GPMC_CONFIG1_DEVICESIZE_16 GPMC_CONFIG1_DEVICESIZE(1)
#define GPMC_CONFIG1_DEVICETYPE(val) ((val & 3) << 10)
#define GPMC_CONFIG1_DEVICETYPE_NOR GPMC_CONFIG1_DEVICETYPE(0)
#define GPMC_CONFIG1_DEVICETYPE_NAND GPMC_CONFIG1_DEVICETYPE(1)
#define GPMC_CONFIG1_MUXADDDATA (1 << 9)
#define GPMC_CONFIG1_TIME_PARA_GRAN (1 << 4)
#define GPMC_CONFIG1_FCLK_DIV(val) (val & 3)
#define GPMC_CONFIG1_FCLK_DIV2 (GPMC_CONFIG1_FCLK_DIV(1))
#define GPMC_CONFIG1_FCLK_DIV3 (GPMC_CONFIG1_FCLK_DIV(2))
#define GPMC_CONFIG1_FCLK_DIV4 (GPMC_CONFIG1_FCLK_DIV(3))
/*
* Note that all values in this struct are in nanoseconds, while
* the register values are in gpmc_fck cycles.
*/
struct gpmc_timings {
/* Minimum clock period for synchronous mode */
u16 sync_clk;
/* Chip-select signal timings corresponding to GPMC_CS_CONFIG2 */
u16 cs_on; /* Assertion time */
u16 cs_rd_off; /* Read deassertion time */
u16 cs_wr_off; /* Write deassertion time */
/* ADV signal timings corresponding to GPMC_CONFIG3 */
u16 adv_on; /* Assertion time */
u16 adv_rd_off; /* Read deassertion time */
u16 adv_wr_off; /* Write deassertion time */
/* WE signals timings corresponding to GPMC_CONFIG4 */
u16 we_on; /* WE assertion time */
u16 we_off; /* WE deassertion time */
/* OE signals timings corresponding to GPMC_CONFIG4 */
u16 oe_on; /* OE assertion time */
u16 oe_off; /* OE deassertion time */
/* Access time and cycle time timings corresponding to GPMC_CONFIG5 */
u16 page_burst_access; /* Multiple access word delay */
u16 access; /* Start-cycle to first data valid delay */
u16 rd_cycle; /* Total read cycle time */
u16 wr_cycle; /* Total write cycle time */
};
extern unsigned int gpmc_ns_to_ticks(unsigned int time_ns);
extern void gpmc_cs_write_reg(int cs, int idx, u32 val);
extern u32 gpmc_cs_read_reg(int cs, int idx);
extern int gpmc_cs_calc_divider(int cs, unsigned int sync_clk);
extern int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t);
extern unsigned long gpmc_cs_get_base_addr(int cs);
#endif

4
include/asm-arm/arch-omap/hardware.h
View File

@ -297,6 +297,10 @@
#include "board-perseus2.h" #include "board-perseus2.h"
#endif #endif
#ifdef CONFIG_MACH_OMAP_FSAMPLE
#include "board-fsample.h"
#endif
#ifdef CONFIG_MACH_OMAP_H3 #ifdef CONFIG_MACH_OMAP_H3
#include "board-h3.h" #include "board-h3.h"
#endif #endif

14
include/asm-arm/arch-omap/irqs.h
View File

@ -242,10 +242,24 @@
#define INT_24XX_GPIO_BANK2 30 #define INT_24XX_GPIO_BANK2 30
#define INT_24XX_GPIO_BANK3 31 #define INT_24XX_GPIO_BANK3 31
#define INT_24XX_GPIO_BANK4 32 #define INT_24XX_GPIO_BANK4 32
#define INT_24XX_GPTIMER1 37
#define INT_24XX_GPTIMER2 38
#define INT_24XX_GPTIMER3 39
#define INT_24XX_GPTIMER4 40
#define INT_24XX_GPTIMER5 41
#define INT_24XX_GPTIMER6 42
#define INT_24XX_GPTIMER7 43
#define INT_24XX_GPTIMER8 44
#define INT_24XX_GPTIMER9 45
#define INT_24XX_GPTIMER10 46
#define INT_24XX_GPTIMER11 47
#define INT_24XX_GPTIMER12 48
#define INT_24XX_MCBSP1_IRQ_TX 59 #define INT_24XX_MCBSP1_IRQ_TX 59
#define INT_24XX_MCBSP1_IRQ_RX 60 #define INT_24XX_MCBSP1_IRQ_RX 60
#define INT_24XX_MCBSP2_IRQ_TX 62 #define INT_24XX_MCBSP2_IRQ_TX 62
#define INT_24XX_MCBSP2_IRQ_RX 63 #define INT_24XX_MCBSP2_IRQ_RX 63
#define INT_24XX_UART1_IRQ 72
#define INT_24XX_UART2_IRQ 73
#define INT_24XX_UART3_IRQ 74 #define INT_24XX_UART3_IRQ 74
/* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730) and /* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730) and

26
include/asm-arm/arch-omap/mux.h
View File

@ -410,6 +410,12 @@ enum omap24xx_index {
/* 24xx clock */ /* 24xx clock */
W14_24XX_SYS_CLKOUT, W14_24XX_SYS_CLKOUT,
/* 24xx GPMC wait pin monitoring */
L3_GPMC_WAIT0,
N7_GPMC_WAIT1,
M1_GPMC_WAIT2,
P1_GPMC_WAIT3,
/* 242X McBSP */ /* 242X McBSP */
Y15_24XX_MCBSP2_CLKX, Y15_24XX_MCBSP2_CLKX,
R14_24XX_MCBSP2_FSX, R14_24XX_MCBSP2_FSX,
@ -429,6 +435,26 @@ enum omap24xx_index {
M15_24XX_GPIO92, M15_24XX_GPIO92,
V14_24XX_GPIO117, V14_24XX_GPIO117,
/* 242x DBG GPIO */
V4_242X_GPIO49,
W2_242X_GPIO50,
U4_242X_GPIO51,
V3_242X_GPIO52,
V2_242X_GPIO53,
V6_242X_GPIO53,
T4_242X_GPIO54,
Y4_242X_GPIO54,
T3_242X_GPIO55,
U2_242X_GPIO56,
/* 24xx external DMA requests */
AA10_242X_DMAREQ0,
AA6_242X_DMAREQ1,
E4_242X_DMAREQ2,
G4_242X_DMAREQ3,
D3_242X_DMAREQ4,
E3_242X_DMAREQ5,
P20_24XX_TSC_IRQ, P20_24XX_TSC_IRQ,
/* UART3 */ /* UART3 */

33
include/asm-arm/arch-omap/pm.h
View File

@ -299,10 +299,43 @@ enum omap24xx_save_state {
OMAP24XX_SLEEP_SAVE_INTC_MIR0, OMAP24XX_SLEEP_SAVE_INTC_MIR0,
OMAP24XX_SLEEP_SAVE_INTC_MIR1, OMAP24XX_SLEEP_SAVE_INTC_MIR1,
OMAP24XX_SLEEP_SAVE_INTC_MIR2, OMAP24XX_SLEEP_SAVE_INTC_MIR2,
OMAP24XX_SLEEP_SAVE_CM_CLKSTCTRL_MPU,
OMAP24XX_SLEEP_SAVE_CM_CLKSTCTRL_CORE,
OMAP24XX_SLEEP_SAVE_CM_CLKSTCTRL_GFX,
OMAP24XX_SLEEP_SAVE_CM_CLKSTCTRL_DSP,
OMAP24XX_SLEEP_SAVE_CM_CLKSTCTRL_MDM,
OMAP24XX_SLEEP_SAVE_PM_PWSTCTRL_MPU,
OMAP24XX_SLEEP_SAVE_PM_PWSTCTRL_CORE,
OMAP24XX_SLEEP_SAVE_PM_PWSTCTRL_GFX,
OMAP24XX_SLEEP_SAVE_PM_PWSTCTRL_DSP,
OMAP24XX_SLEEP_SAVE_PM_PWSTCTRL_MDM,
OMAP24XX_SLEEP_SAVE_CM_IDLEST1_CORE,
OMAP24XX_SLEEP_SAVE_CM_IDLEST2_CORE,
OMAP24XX_SLEEP_SAVE_CM_IDLEST3_CORE,
OMAP24XX_SLEEP_SAVE_CM_IDLEST4_CORE,
OMAP24XX_SLEEP_SAVE_CM_IDLEST_GFX,
OMAP24XX_SLEEP_SAVE_CM_IDLEST_WKUP,
OMAP24XX_SLEEP_SAVE_CM_IDLEST_CKGEN,
OMAP24XX_SLEEP_SAVE_CM_IDLEST_DSP,
OMAP24XX_SLEEP_SAVE_CM_IDLEST_MDM,
OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE1_CORE,
OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE2_CORE,
OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE3_CORE,
OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE4_CORE,
OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE_WKUP,
OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE_PLL,
OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE_DSP,
OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE_MDM,
OMAP24XX_SLEEP_SAVE_CM_FCLKEN1_CORE, OMAP24XX_SLEEP_SAVE_CM_FCLKEN1_CORE,
OMAP24XX_SLEEP_SAVE_CM_FCLKEN2_CORE, OMAP24XX_SLEEP_SAVE_CM_FCLKEN2_CORE,
OMAP24XX_SLEEP_SAVE_CM_ICLKEN1_CORE, OMAP24XX_SLEEP_SAVE_CM_ICLKEN1_CORE,
OMAP24XX_SLEEP_SAVE_CM_ICLKEN2_CORE, OMAP24XX_SLEEP_SAVE_CM_ICLKEN2_CORE,
OMAP24XX_SLEEP_SAVE_CM_ICLKEN3_CORE,
OMAP24XX_SLEEP_SAVE_CM_ICLKEN4_CORE, OMAP24XX_SLEEP_SAVE_CM_ICLKEN4_CORE,
OMAP24XX_SLEEP_SAVE_GPIO1_IRQENABLE1, OMAP24XX_SLEEP_SAVE_GPIO1_IRQENABLE1,
OMAP24XX_SLEEP_SAVE_GPIO2_IRQENABLE1, OMAP24XX_SLEEP_SAVE_GPIO2_IRQENABLE1,

2
include/asm-arm/arch-pxa/pxa-regs.h
View File

@ -1329,6 +1329,7 @@
#define GPIO84_NSRXD 84 /* NSSP receive */ #define GPIO84_NSRXD 84 /* NSSP receive */
#define GPIO85_nPCE_1 85 /* Card Enable for Card Space (PXA27x) */ #define GPIO85_nPCE_1 85 /* Card Enable for Card Space (PXA27x) */
#define GPIO92_MMCDAT0 92 /* MMC DAT0 (PXA27x) */ #define GPIO92_MMCDAT0 92 /* MMC DAT0 (PXA27x) */
#define GPIO102_nPCE_1 102 /* PCMCIA (PXA27x) */
#define GPIO109_MMCDAT1 109 /* MMC DAT1 (PXA27x) */ #define GPIO109_MMCDAT1 109 /* MMC DAT1 (PXA27x) */
#define GPIO110_MMCDAT2 110 /* MMC DAT2 (PXA27x) */ #define GPIO110_MMCDAT2 110 /* MMC DAT2 (PXA27x) */
#define GPIO110_MMCCS0 110 /* MMC Chip Select 0 (PXA27x) */ #define GPIO110_MMCCS0 110 /* MMC Chip Select 0 (PXA27x) */
@ -1471,6 +1472,7 @@
#define GPIO84_NSSP_RX (84 | GPIO_ALT_FN_2_IN) #define GPIO84_NSSP_RX (84 | GPIO_ALT_FN_2_IN)
#define GPIO85_nPCE_1_MD (85 | GPIO_ALT_FN_1_OUT) #define GPIO85_nPCE_1_MD (85 | GPIO_ALT_FN_1_OUT)
#define GPIO92_MMCDAT0_MD (92 | GPIO_ALT_FN_1_OUT) #define GPIO92_MMCDAT0_MD (92 | GPIO_ALT_FN_1_OUT)
#define GPIO102_nPCE_1_MD (102 | GPIO_ALT_FN_1_OUT)
#define GPIO104_pSKTSEL_MD (104 | GPIO_ALT_FN_1_OUT) #define GPIO104_pSKTSEL_MD (104 | GPIO_ALT_FN_1_OUT)
#define GPIO109_MMCDAT1_MD (109 | GPIO_ALT_FN_1_OUT) #define GPIO109_MMCDAT1_MD (109 | GPIO_ALT_FN_1_OUT)
#define GPIO110_MMCDAT2_MD (110 | GPIO_ALT_FN_1_OUT) #define GPIO110_MMCDAT2_MD (110 | GPIO_ALT_FN_1_OUT)

106
include/asm-arm/arch-pxa/trizeps4.h Normal file
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@ -0,0 +1,106 @@
/************************************************************************
* Include file for TRIZEPS4 SoM and ConXS eval-board
* Copyright (c) Jürgen Schindele
* 2006
************************************************************************/
/*
* Includes/Defines
*/
#ifndef _TRIPEPS4_H_
#define _TRIPEPS4_H_
/* physical memory regions */
#define TRIZEPS4_FLASH_PHYS (PXA_CS0_PHYS) /* Flash region */
#define TRIZEPS4_DISK_PHYS (PXA_CS1_PHYS) /* Disk On Chip region */
#define TRIZEPS4_ETH_PHYS (PXA_CS2_PHYS) /* Ethernet DM9000 region */
#define TRIZEPS4_PIC_PHYS (PXA_CS3_PHYS) /* Logic chip on ConXS-Board */
#define TRIZEPS4_SDRAM_BASE 0xa0000000 /* SDRAM region */
#define TRIZEPS4_CFSR_PHYS (PXA_CS3_PHYS) /* Logic chip on ConXS-Board CSFR register */
#define TRIZEPS4_BOCR_PHYS (PXA_CS3_PHYS+0x02000000) /* Logic chip on ConXS-Board BOCR register */
#define TRIZEPS4_IRCR_PHYS (PXA_CS3_PHYS+0x02400000) /* Logic chip on ConXS-Board IRCR register*/
#define TRIZEPS4_UPSR_PHYS (PXA_CS3_PHYS+0x02800000) /* Logic chip on ConXS-Board UPSR register*/
#define TRIZEPS4_DICR_PHYS (PXA_CS3_PHYS+0x03800000) /* Logic chip on ConXS-Board DICR register*/
/* virtual memory regions */
#define TRIZEPS4_DISK_VIRT 0xF0000000 /* Disk On Chip region */
#define TRIZEPS4_PIC_VIRT 0xF0100000 /* not used */
#define TRIZEPS4_CFSR_VIRT 0xF0100000
#define TRIZEPS4_BOCR_VIRT 0xF0200000
#define TRIZEPS4_DICR_VIRT 0xF0300000
#define TRIZEPS4_IRCR_VIRT 0xF0400000
#define TRIZEPS4_UPSR_VIRT 0xF0500000
/* size of flash */
#define TRIZEPS4_FLASH_SIZE 0x02000000 /* Flash size 32 MB */
/* Ethernet Controller Davicom DM9000 */
#define GPIO_DM9000 101
#define TRIZEPS4_ETH_IRQ IRQ_GPIO(GPIO_DM9000)
/* UCB1400 audio / TS-controller */
#define GPIO_UCB1400 1
#define TRIZEPS4_UCB1400_IRQ IRQ_GPIO(GPIO_UCB1400)
/* PCMCIA socket Compact Flash */
#define GPIO_PCD 11 /* PCMCIA Card Detect */
#define TRIZEPS4_CD_IRQ IRQ_GPIO(GPIO_PCD)
#define GPIO_PRDY 13 /* READY / nINT */
#define TRIZEPS4_READY_NINT IRQ_GPIO(GPIO_PRDY)
/* MMC socket */
#define GPIO_MMC_DET 12
#define TRIZEPS4_MMC_IRQ IRQ_GPIO(GPIO_MMC_DET)
/* LEDS using tx2 / rx2 */
#define GPIO_SYS_BUSY_LED 46
#define GPIO_HEARTBEAT_LED 47
/* Off-module PIC on ConXS board */
#define GPIO_PIC 0
#define TRIZEPS4_PIC_IRQ IRQ_GPIO(GPIO_PIC)
#define CFSR_P2V(x) ((x) - TRIZEPS4_CFSR_PHYS + TRIZEPS4_CFSR_VIRT)
#define CFSR_V2P(x) ((x) - TRIZEPS4_CFSR_VIRT + TRIZEPS4_CFSR_PHYS)
#define BCR_P2V(x) ((x) - TRIZEPS4_BOCR_PHYS + TRIZEPS4_BOCR_VIRT)
#define BCR_V2P(x) ((x) - TRIZEPS4_BOCR_VIRT + TRIZEPS4_BOCR_PHYS)
#define DCR_P2V(x) ((x) - TRIZEPS4_DICR_PHYS + TRIZEPS4_DICR_VIRT)
#define DCR_V2P(x) ((x) - TRIZEPS4_DICR_VIRT + TRIZEPS4_DICR_PHYS)
#ifndef __ASSEMBLY__
#define ConXS_CFSR (*((volatile unsigned short *)CFSR_P2V(0x0C000000)))
#define ConXS_BCR (*((volatile unsigned short *)BCR_P2V(0x0E000000)))
#define ConXS_DCR (*((volatile unsigned short *)DCR_P2V(0x0F800000)))
#else
#define ConXS_CFSR CFSR_P2V(0x0C000000)
#define ConXS_BCR BCR_P2V(0x0E000000)
#define ConXS_DCR DCR_P2V(0x0F800000)
#endif
#define ConXS_CFSR_BVD_MASK 0x0003
#define ConXS_CFSR_BVD1 (1 << 0)
#define ConXS_CFSR_BVD2 (1 << 1)
#define ConXS_CFSR_VS_MASK 0x000C
#define ConXS_CFSR_VS1 (1 << 2)
#define ConXS_CFSR_VS2 (1 << 3)
#define ConXS_CFSR_VS_5V (0x3 << 2)
#define ConXS_CFSR_VS_3V3 0x0
#define ConXS_BCR_S0_POW_EN0 (1 << 0)
#define ConXS_BCR_S0_POW_EN1 (1 << 1)
#define ConXS_BCR_L_DISP (1 << 4)
#define ConXS_BCR_CF_BUF_EN (1 << 5)
#define ConXS_BCR_CF_RESET (1 << 7)
#define ConXS_BCR_S0_VCC_3V3 0x1
#define ConXS_BCR_S0_VCC_5V0 0x2
#define ConXS_BCR_S0_VPP_12V 0x4
#define ConXS_BCR_S0_VPP_3V3 0x8
#define ConXS_IRCR_MODE (1 << 0)
#define ConXS_IRCR_SD (1 << 1)
#endif /* _TRIPEPS4_H_ */

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