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i2c: img-scb: remove fifo EMPTYING interrupts handle

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Now that we are using the transaction halt interrupt to safely control
repeated start transfers, we no longer need to handle the fifo
emptying interrupts.

Handling this interrupt along with Transaction Halt interrupt can
cause erratic behaviour.

Signed-off-by: Sifan Naeem <sifan.naeem@imgtec.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
This commit is contained in:
Sifan Naeem 2015-11-19 09:35:14 +00:00 committed by Wolfram Sang
parent c55ebe0e72
commit a8c5a8d8c9
1 changed files with 3 additions and 13 deletions
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16
drivers/i2c/busses/i2c-img-scb.c
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@ -154,7 +154,6 @@
#define INT_TIMING BIT(18) #define INT_TIMING BIT(18)
#define INT_FIFO_FULL_FILLING (INT_FIFO_FULL | INT_FIFO_FILLING) #define INT_FIFO_FULL_FILLING (INT_FIFO_FULL | INT_FIFO_FILLING)
#define INT_FIFO_EMPTY_EMPTYING (INT_FIFO_EMPTY | INT_FIFO_EMPTYING)
/* Level interrupts need clearing after handling instead of before */ /* Level interrupts need clearing after handling instead of before */
#define INT_LEVEL 0x01e00 #define INT_LEVEL 0x01e00
@ -176,8 +175,7 @@
INT_WRITE_ACK_ERR | \ INT_WRITE_ACK_ERR | \
INT_FIFO_FULL | \ INT_FIFO_FULL | \
INT_FIFO_FILLING | \ INT_FIFO_FILLING | \
INT_FIFO_EMPTY | \ INT_FIFO_EMPTY)
INT_FIFO_EMPTYING)
#define INT_ENABLE_MASK_WAITSTOP (INT_SLAVE_EVENT | \ #define INT_ENABLE_MASK_WAITSTOP (INT_SLAVE_EVENT | \
INT_ADDR_ACK_ERR | \ INT_ADDR_ACK_ERR | \
@ -874,16 +872,8 @@ static unsigned int img_i2c_auto(struct img_i2c *i2c,
return ISR_WAITSTOP; return ISR_WAITSTOP;
} }
} else { } else {
if (int_status & INT_FIFO_EMPTY_EMPTYING) { if (int_status & INT_FIFO_EMPTY) {
/* if (i2c->msg.len == 0)
* The write fifo empty indicates that we're in the
* last byte so it's safe to start a new write
* transaction without losing any bytes from the
* previous one.
* see 2.3.7 Repeated Start Transactions.
*/
if ((int_status & INT_FIFO_EMPTY) &&
i2c->msg.len == 0)
return ISR_WAITSTOP; return ISR_WAITSTOP;
img_i2c_write_fifo(i2c); img_i2c_write_fifo(i2c);
} }