dt-bindings: phy: convert phy-mtk-xsphy.txt to YAML schema
Convert phy-mtk-xsphy.txt to YAML schema mediatek,xsphy.yaml Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20201225075258.33352-3-chunfeng.yun@mediatek.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
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Chunfeng Yun
Vinod Koul
parent
a9dfa098b7
commit
a8ec9e048b
199
Documentation/devicetree/bindings/phy/mediatek,xsphy.yaml
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199
Documentation/devicetree/bindings/phy/mediatek,xsphy.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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# Copyright (c) 2020 MediaTek
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/phy/mediatek,xsphy.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: MediaTek XS-PHY Controller Device Tree Bindings
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maintainers:
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- Chunfeng Yun <chunfeng.yun@mediatek.com>
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description: |
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The XS-PHY controller supports physical layer functionality for USB3.1
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GEN2 controller on MediaTek SoCs.
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Banks layout of xsphy
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----------------------------------
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port offset bank
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u2 port0 0x0000 MISC
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0x0100 FMREG
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0x0300 U2PHY_COM
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u2 port1 0x1000 MISC
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0x1100 FMREG
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0x1300 U2PHY_COM
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u2 port2 0x2000 MISC
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...
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u31 common 0x3000 DIG_GLB
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0x3100 PHYA_GLB
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u31 port0 0x3400 DIG_LN_TOP
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0x3500 DIG_LN_TX0
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0x3600 DIG_LN_RX0
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0x3700 DIG_LN_DAIF
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0x3800 PHYA_LN
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u31 port1 0x3a00 DIG_LN_TOP
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0x3b00 DIG_LN_TX0
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0x3c00 DIG_LN_RX0
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0x3d00 DIG_LN_DAIF
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0x3e00 PHYA_LN
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...
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DIG_GLB & PHYA_GLB are shared by U31 ports.
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properties:
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$nodename:
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pattern: "^xs-phy@[0-9a-f]+$"
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compatible:
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items:
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- enum:
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- mediatek,mt3611-xsphy
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- mediatek,mt3612-xsphy
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- const: mediatek,xsphy
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reg:
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description:
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Register shared by multiple U3 ports, exclude port's private register,
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if only U2 ports provided, shouldn't use the property.
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maxItems: 1
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"#address-cells":
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enum: [1, 2]
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"#size-cells":
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enum: [1, 2]
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ranges: true
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mediatek,src-ref-clk-mhz:
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description:
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Frequency of reference clock for slew rate calibrate
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default: 26
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mediatek,src-coef:
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description:
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Coefficient for slew rate calibrate, depends on SoC process
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$ref: /schemas/types.yaml#/definitions/uint32
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default: 17
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# Required child node:
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patternProperties:
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"^usb-phy@[0-9a-f]+$":
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type: object
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description:
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A sub-node is required for each port the controller provides.
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Address range information including the usual 'reg' property
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is used inside these nodes to describe the controller's topology.
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properties:
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reg:
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maxItems: 1
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clocks:
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items:
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- description: Reference clock, (HS is 48Mhz, SS/P is 24~27Mhz)
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clock-names:
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items:
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- const: ref
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"#phy-cells":
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const: 1
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description: |
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The cells contain the following arguments.
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- description: The PHY type
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enum:
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- PHY_TYPE_USB2
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- PHY_TYPE_USB3
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# The following optional vendor properties are only for debug or HQA test
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mediatek,eye-src:
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description:
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The value of slew rate calibrate (U2 phy)
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$ref: /schemas/types.yaml#/definitions/uint32
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minimum: 1
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maximum: 7
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mediatek,eye-vrt:
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description:
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The selection of VRT reference voltage (U2 phy)
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$ref: /schemas/types.yaml#/definitions/uint32
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minimum: 1
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maximum: 7
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mediatek,eye-term:
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description:
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The selection of HS_TX TERM reference voltage (U2 phy)
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$ref: /schemas/types.yaml#/definitions/uint32
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minimum: 1
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maximum: 7
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mediatek,efuse-intr:
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description:
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The selection of Internal Resistor (U2/U3 phy)
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$ref: /schemas/types.yaml#/definitions/uint32
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minimum: 1
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maximum: 63
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mediatek,efuse-tx-imp:
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description:
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The selection of TX Impedance (U3 phy)
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$ref: /schemas/types.yaml#/definitions/uint32
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minimum: 1
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maximum: 31
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mediatek,efuse-rx-imp:
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description:
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The selection of RX Impedance (U3 phy)
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$ref: /schemas/types.yaml#/definitions/uint32
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minimum: 1
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maximum: 31
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required:
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- reg
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- clocks
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- clock-names
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- "#phy-cells"
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additionalProperties: false
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required:
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- compatible
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- "#address-cells"
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- "#size-cells"
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- ranges
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/phy/phy.h>
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u3phy: xs-phy@11c40000 {
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compatible = "mediatek,mt3611-xsphy", "mediatek,xsphy";
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reg = <0x11c43000 0x0200>;
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mediatek,src-ref-clk-mhz = <26>;
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mediatek,src-coef = <17>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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u2port0: usb-phy@11c40000 {
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reg = <0x11c40000 0x0400>;
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clocks = <&clk48m>;
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clock-names = "ref";
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mediatek,eye-src = <4>;
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#phy-cells = <1>;
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};
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u3port0: usb-phy@11c43000 {
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reg = <0x11c43400 0x0500>;
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clocks = <&clk26m>;
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clock-names = "ref";
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mediatek,efuse-intr = <28>;
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#phy-cells = <1>;
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};
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};
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...
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@ -1,109 +0,0 @@
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MediaTek XS-PHY binding
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--------------------------
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The XS-PHY controller supports physical layer functionality for USB3.1
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GEN2 controller on MediaTek SoCs.
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Required properties (controller (parent) node):
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- compatible : should be "mediatek,<soc-model>-xsphy", "mediatek,xsphy",
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soc-model is the name of SoC, such as mt3611 etc;
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when using "mediatek,xsphy" compatible string, you need SoC specific
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ones in addition, one of:
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- "mediatek,mt3611-xsphy"
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- #address-cells, #size-cells : should use the same values as the root node
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- ranges: must be present
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Optional properties (controller (parent) node):
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- reg : offset and length of register shared by multiple U3 ports,
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exclude port's private register, if only U2 ports provided,
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shouldn't use the property.
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- mediatek,src-ref-clk-mhz : u32, frequency of reference clock for slew rate
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calibrate
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- mediatek,src-coef : u32, coefficient for slew rate calibrate, depends on
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SoC process
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Required nodes : a sub-node is required for each port the controller
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provides. Address range information including the usual
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'reg' property is used inside these nodes to describe
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the controller's topology.
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Required properties (port (child) node):
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- reg : address and length of the register set for the port.
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- clocks : a list of phandle + clock-specifier pairs, one for each
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entry in clock-names
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- clock-names : must contain
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"ref": 48M reference clock for HighSpeed analog phy; and 26M
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reference clock for SuperSpeedPlus analog phy, sometimes is
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24M, 25M or 27M, depended on platform.
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- #phy-cells : should be 1
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cell after port phandle is phy type from:
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- PHY_TYPE_USB2
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- PHY_TYPE_USB3
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The following optional properties are only for debug or HQA test
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Optional properties (PHY_TYPE_USB2 port (child) node):
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- mediatek,eye-src : u32, the value of slew rate calibrate
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- mediatek,eye-vrt : u32, the selection of VRT reference voltage
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- mediatek,eye-term : u32, the selection of HS_TX TERM reference voltage
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- mediatek,efuse-intr : u32, the selection of Internal Resistor
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Optional properties (PHY_TYPE_USB3 port (child) node):
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- mediatek,efuse-intr : u32, the selection of Internal Resistor
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- mediatek,efuse-tx-imp : u32, the selection of TX Impedance
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- mediatek,efuse-rx-imp : u32, the selection of RX Impedance
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Banks layout of xsphy
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-------------------------------------------------------------
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port offset bank
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u2 port0 0x0000 MISC
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0x0100 FMREG
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0x0300 U2PHY_COM
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u2 port1 0x1000 MISC
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0x1100 FMREG
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0x1300 U2PHY_COM
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u2 port2 0x2000 MISC
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...
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u31 common 0x3000 DIG_GLB
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0x3100 PHYA_GLB
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u31 port0 0x3400 DIG_LN_TOP
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0x3500 DIG_LN_TX0
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0x3600 DIG_LN_RX0
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0x3700 DIG_LN_DAIF
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0x3800 PHYA_LN
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u31 port1 0x3a00 DIG_LN_TOP
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0x3b00 DIG_LN_TX0
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0x3c00 DIG_LN_RX0
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0x3d00 DIG_LN_DAIF
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0x3e00 PHYA_LN
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...
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DIG_GLB & PHYA_GLB are shared by U31 ports.
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Example:
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u3phy: usb-phy@11c40000 {
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compatible = "mediatek,mt3611-xsphy", "mediatek,xsphy";
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reg = <0 0x11c43000 0 0x0200>;
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mediatek,src-ref-clk-mhz = <26>;
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mediatek,src-coef = <17>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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u2port0: usb-phy@11c40000 {
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reg = <0 0x11c40000 0 0x0400>;
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clocks = <&clk48m>;
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clock-names = "ref";
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mediatek,eye-src = <4>;
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#phy-cells = <1>;
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};
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u3port0: usb-phy@11c43000 {
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reg = <0 0x11c43400 0 0x0500>;
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clocks = <&clk26m>;
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clock-names = "ref";
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mediatek,efuse-intr = <28>;
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#phy-cells = <1>;
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};
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};
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