More Qualcomm ARM64 DT updates for 5.13
This adds RPMh regulators, coresight, AOSS qmp, ipcc, llcc for the SC7280. It adds interconnect, PRNG and thermal pieces to SM8350. It specifies the now required clocks for the SDM845 gcc, corrects the firmware-name for adsp and cdsp on the db845c and defines DSI and panel bits for Xiaomi Pocophone F1. SM8150 gains iommu settings and the remaining I2C controllers and SM8250 gains Venus and the QMP PHY is updated to include the DP portion. It adds the MSM8998 based OnePlus 5/5T device and enables sound support on the Trogdor device family. Lastly it adds the GIC hypervisor registers & interrupt for when Linux is booted in EL2 on MSM8916. -----BEGIN PGP SIGNATURE----- iQJPBAABCAA5FiEEBd4DzF816k8JZtUlCx85Pw2ZrcUFAmBwgw4bHGJqb3JuLmFu ZGVyc3NvbkBsaW5hcm8ub3JnAAoJEAsfOT8Nma3FWXoQAKpPf+oQc+wVvoGCk35T Xq5MFxJvm69Ad2TjCgRkyKrb1Op02PlrzJT5CNTt8d2OZjiLH4VZnv6b6e5z8sEA 1PbAID09tCLxE6j2KV6RCt4L9JGslT6eQ2HQWCCIjte8ygI3meyjjsGr3j1BJcJM 0GdLp1UTvlcItQcVymf6OLw0z69hvNuOiEAaQ1BNF+Y9VRhM940nS35D/0vhZpdQ fP8aeCslAnu020g88P0uJESEsCQPLjywBHK2JlyYmzZzr9/OZnJvETUG6fkMjxQ/ TnJiuaGBDk//yhULYxt0t2Xi1gK76snkTLKx09p6a/GBIyNgTUW7MdEPw3n14FL9 cuFpFTZTTKw0HtaHtu2HtM/WFlBE92XlWKSKTfsVI/qR9LJn+6p6Ewi61evsg04U +z8RI+rOD/lOXbU6VtYbdPE7wTkNk4+vTTPzAWSsNr7GtuGoNR3Qb693PwV2gsdl BgkxR5sZDZAesa7tfpeZnB57fOq3N9iZHbdQWx/JaEyvou24LjHchWQv8o0xN8Av P67PlfMM6tqt5jFSs8aLp9C6bsZjkzX4OnhP7p6ah39YlR6/pNh32pk74+DSspF2 e/XyH4gO0zTJ6DgPozPBz70epH5ToDXQQEbcKQ+huFUtSOjNDdlrSKouGPcRufIn c8fgySvA9ChVIFwxju9+/Urs =7juS -----END PGP SIGNATURE----- Merge tag 'qcom-arm64-for-5.13-2' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/dt More Qualcomm ARM64 DT updates for 5.13 This adds RPMh regulators, coresight, AOSS qmp, ipcc, llcc for the SC7280. It adds interconnect, PRNG and thermal pieces to SM8350. It specifies the now required clocks for the SDM845 gcc, corrects the firmware-name for adsp and cdsp on the db845c and defines DSI and panel bits for Xiaomi Pocophone F1. SM8150 gains iommu settings and the remaining I2C controllers and SM8250 gains Venus and the QMP PHY is updated to include the DP portion. It adds the MSM8998 based OnePlus 5/5T device and enables sound support on the Trogdor device family. Lastly it adds the GIC hypervisor registers & interrupt for when Linux is booted in EL2 on MSM8916. * tag 'qcom-arm64-for-5.13-2' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (25 commits) arm64: dts: qcom: update usb qmp phy clock-cells property arm64: dts: qcom: msm8916: Add GICv2 hypervisor registers/interrupt arm64: dts: sdm845-db845c: make firmware filenames follow linux-firmware arm64: dts: qcom: sdm845-xiaomi-beryllium: Add DSI and panel bits arm64: dts: qcom: sc7280: Add Coresight support arm64: dts: qcom: sc7280: Add AOSS QMP node arm64: dts: qcom: sc7280: Add IPCC for SC7280 SoC arm64: dts: qcom: sc7280: Add device tree node for LLCC arm64: dts: qcom: Add support for OnePlus 5/5T arm64: dts: qcom: msm8998: Disable MSS remoteproc by default arm64: dts: qcom: Move rmtfs memory region arm64: dts: qcom: Add sound node for sc7180-trogdor-coachz arm64: dts: qcom: sc7180-trogdor: Add lpass dai link for I2S driver arm64: dts: qcom: use dp_phy to provide clocks to dispcc arm64: dts: qcom: sm8250: switch usb1 qmp phy to USB3+DP mode arm64: dts: qcom: sm8250: Add venus DT node arm64: dts: qcom: sm8250: Add videocc DT node arm64: dts: qcom: sm8350: Add interconnects arm64: dts: qcom: sm8350: Add support for PRNG EE arm64: dts: qcom: sc7280: Add RPMh regulators for sc7280-idp ... Link: https://lore.kernel.org/r/20210409163949.776530-1-bjorn.andersson@linaro.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
a8f6ba2825
@ -27,6 +27,8 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8998-asus-novago-tp370ql.dtb
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dtb-$(CONFIG_ARCH_QCOM) += msm8998-hp-envy-x2.dtb
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dtb-$(CONFIG_ARCH_QCOM) += msm8998-lenovo-miix-630.dtb
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dtb-$(CONFIG_ARCH_QCOM) += msm8998-mtp.dtb
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dtb-$(CONFIG_ARCH_QCOM) += msm8998-oneplus-cheeseburger.dtb
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dtb-$(CONFIG_ARCH_QCOM) += msm8998-oneplus-dumpling.dtb
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dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-1000.dtb
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dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-4000.dtb
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dtb-$(CONFIG_ARCH_QCOM) += qrb5165-rb5.dtb
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@ -1766,7 +1766,9 @@
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compatible = "qcom,msm-qgic2";
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interrupt-controller;
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#interrupt-cells = <3>;
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reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
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reg = <0x0b000000 0x1000>, <0x0b002000 0x2000>,
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<0x0b001000 0x1000>, <0x0b004000 0x2000>;
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interrupts = <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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};
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apcs: mailbox@b011000 {
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@ -281,6 +281,10 @@
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};
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};
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&remoteproc_mss {
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status = "okay";
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};
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&tlmm {
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gpio-reserved-ranges = <0 4>, <81 4>;
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@ -328,6 +328,10 @@
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status = "okay";
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};
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&remoteproc_mss {
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status = "okay";
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};
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&remoteproc_slpi {
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status = "okay";
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};
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42
arch/arm64/boot/dts/qcom/msm8998-oneplus-cheeseburger.dts
Normal file
42
arch/arm64/boot/dts/qcom/msm8998-oneplus-cheeseburger.dts
Normal file
@ -0,0 +1,42 @@
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// SPDX-License-Identifier: BSD-3-Clause
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/*
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* OnePlus 5 (cheeseburger) device tree
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*
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* Copyright (c) 2021, Jami Kettunen <jamipkettunen@gmail.com>
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*/
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#include <dt-bindings/leds/common.h>
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#include "msm8998-oneplus-common.dtsi"
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/ {
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model = "OnePlus 5";
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compatible = "oneplus,cheeseburger", "qcom,msm8998";
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/* Required for bootloader to select correct board */
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qcom,board-id = <8 0 16859 23>;
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/* Capacitive keypad button backlight */
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leds {
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compatible = "gpio-leds";
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pinctrl-names = "default";
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pinctrl-0 = <&button_backlight_default>;
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button-backlight {
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gpios = <&pmi8998_gpio 5 GPIO_ACTIVE_HIGH>;
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color = <LED_COLOR_ID_WHITE>;
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function = LED_FUNCTION_KBD_BACKLIGHT;
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default-state = "off";
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};
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};
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};
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&pmi8998_gpio {
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button_backlight_default: button-backlight-default {
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pinconf {
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pins = "gpio5";
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function = "normal";
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bias-pull-down;
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qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>;
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};
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};
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};
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514
arch/arm64/boot/dts/qcom/msm8998-oneplus-common.dtsi
Normal file
514
arch/arm64/boot/dts/qcom/msm8998-oneplus-common.dtsi
Normal file
@ -0,0 +1,514 @@
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// SPDX-License-Identifier: BSD-3-Clause
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/*
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* OnePlus 5(T) (cheeseburger / dumpling) common device tree source based on msm8998-mtp.dtsi
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*
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* Copyright (c) 2021, Jami Kettunen <jamipkettunen@gmail.com>
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* Copyright (c) 2016, The Linux Foundation. All rights reserved.
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*/
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/dts-v1/;
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
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#include "msm8998.dtsi"
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#include "pm8998.dtsi"
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#include "pmi8998.dtsi"
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#include "pm8005.dtsi"
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/ {
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/* Required for bootloader to select correct board */
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qcom,msm-id = <292 0x20001>; /* 8998 v2.1 */
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chosen {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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/* Use display framebuffer setup by the UEFI XBL bootloader for simplefb */
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framebuffer0: framebuffer@9d400000 {
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compatible = "simple-framebuffer";
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reg = <0x0 0x9d400000 0x0 0x2400000>;
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width = <1080>;
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height = <1920>;
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stride = <(1080 * 4)>;
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format = "a8r8g8b8";
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};
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};
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reserved-memory {
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/* Bootloader display framebuffer region */
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cont_splash_mem: memory@9d400000 {
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reg = <0x0 0x9d400000 0x0 0x2400000>;
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no-map;
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};
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/* For getting crash logs using Android downstream kernels */
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ramoops@ac000000 {
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compatible = "ramoops";
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reg = <0x0 0xac000000 0x0 0x200000>;
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console-size = <0x80000>;
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pmsg-size = <0x40000>;
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record-size = <0x8000>;
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ftrace-size = <0x20000>;
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};
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/*
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* The following memory regions on downstream are "dynamically allocated"
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* but given the same addresses every time. Hard code them as these addresses
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* are where the OnePlus signed firmware expects them to be.
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*/
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ipa_fws_region: ipa@f6800000 {
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compatible = "shared-dma-pool";
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reg = <0x0 0xf6800000 0x0 0x5000>;
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no-map;
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};
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zap_shader_region: gpu@f6900000 {
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compatible = "shared-dma-pool";
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reg = <0x0 0xf6900000 0x0 0x2000>;
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no-map;
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};
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};
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gpio-keys {
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compatible = "gpio-keys";
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label = "Volume buttons";
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autorepeat;
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pinctrl-names = "default";
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pinctrl-0 = <&vol_keys_default>;
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vol-down {
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label = "Volume down";
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gpios = <&pm8998_gpio 5 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_VOLUMEDOWN>;
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debounce-interval = <15>;
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wakeup-source;
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};
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vol-up {
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label = "Volume up";
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gpios = <&pm8998_gpio 6 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_VOLUMEUP>;
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debounce-interval = <15>;
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wakeup-source;
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};
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};
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gpio-hall-sensor {
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compatible = "gpio-keys";
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label = "Hall effect sensor";
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pinctrl-names = "default";
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pinctrl-0 = <&hall_sensor_default>;
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hall-sensor {
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label = "Hall Effect Sensor";
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gpios = <&tlmm 124 GPIO_ACTIVE_LOW>;
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linux,input-type = <EV_SW>;
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linux,code = <SW_LID>;
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linux,can-disable;
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wakeup-source;
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};
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};
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vph_pwr: vph-pwr-regulator {
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compatible = "regulator-fixed";
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regulator-name = "vph_pwr";
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regulator-always-on;
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regulator-boot-on;
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};
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};
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/*
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* OnePlus' ADSP firmware requires 30 MiB in total, so increase the adsp_mem
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* region by 4 MiB to account for this while relocating the other now
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* conflicting memory nodes accordingly.
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*/
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&adsp_mem {
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reg = <0x0 0x8b200000 0x0 0x1e00000>;
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};
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&mpss_mem {
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reg = <0x0 0x8d000000 0x0 0x7000000>;
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};
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&venus_mem {
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reg = <0x0 0x94000000 0x0 0x500000>;
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};
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&mba_mem {
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reg = <0x0 0x94500000 0x0 0x200000>;
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};
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&slpi_mem {
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reg = <0x0 0x94700000 0x0 0xf00000>;
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};
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&ipa_fw_mem {
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reg = <0x0 0x95600000 0x0 0x10000>;
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};
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&ipa_gsi_mem {
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reg = <0x0 0x95610000 0x0 0x5000>;
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};
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&gpu_mem {
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reg = <0x0 0x95615000 0x0 0x100000>;
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};
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&wlan_msa_mem {
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reg = <0x0 0x95715000 0x0 0x100000>;
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};
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&blsp1_i2c5 {
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status = "okay";
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touchscreen@20 {
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compatible = "syna,rmi4-i2c";
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reg = <0x20>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupt-parent = <&tlmm>;
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interrupts = <125 IRQ_TYPE_EDGE_FALLING>;
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pinctrl-names = "default";
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pinctrl-0 = <&ts_int_active &ts_reset_active>;
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vdd-supply = <&vreg_l28_3p0>;
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vio-supply = <&vreg_l6a_1p8>;
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syna,reset-delay-ms = <20>;
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syna,startup-delay-ms = <20>;
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rmi4-f01@1 {
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reg = <0x01>;
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syna,nosleep-mode = <1>;
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};
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rmi4_f12: rmi4-f12@12 {
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reg = <0x12>;
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syna,rezero-wait-ms = <20>;
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syna,sensor-type = <1>;
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touchscreen-x-mm = <68>;
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touchscreen-y-mm = <122>;
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};
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};
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};
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&blsp1_uart3 {
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status = "okay";
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bluetooth {
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compatible = "qcom,wcn3990-bt";
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vddio-supply = <&vreg_s4a_1p8>;
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vddxo-supply = <&vreg_l7a_1p8>;
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vddrf-supply = <&vreg_l17a_1p3>;
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vddch0-supply = <&vreg_l25a_3p3>;
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max-speed = <3200000>;
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};
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};
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&blsp1_uart3_on {
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rx {
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/delete-property/ bias-disable;
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/*
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* Configure a pull-up on 46 (RX). This is needed to
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* avoid garbage data when the TX pin of the Bluetooth
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* module is in tri-state (module powered off or not
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* driving the signal yet).
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||||
*/
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||||
bias-pull-up;
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||||
};
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||||
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cts {
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/delete-property/ bias-disable;
|
||||
/*
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||||
* Configure a pull-down on 47 (CTS) to match the pull
|
||||
* of the Bluetooth module.
|
||||
*/
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||||
bias-pull-down;
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||||
};
|
||||
};
|
||||
|
||||
&blsp2_uart1 {
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||||
status = "okay";
|
||||
};
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||||
|
||||
&pm8005_lsid1 {
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||||
pm8005-regulators {
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||||
compatible = "qcom,pm8005-regulators";
|
||||
|
||||
vdd_s1-supply = <&vph_pwr>;
|
||||
|
||||
pm8005_s1: s1 { /* VDD_GFX supply */
|
||||
regulator-min-microvolt = <524000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
regulator-enable-ramp-delay = <500>;
|
||||
|
||||
/* hack until we rig up the gpu consumer */
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pm8998_gpio {
|
||||
vol_keys_default: vol-keys-default {
|
||||
pinconf {
|
||||
pins = "gpio5", "gpio6";
|
||||
function = "normal";
|
||||
bias-pull-up;
|
||||
input-enable;
|
||||
qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&qusb2phy {
|
||||
status = "okay";
|
||||
|
||||
vdda-pll-supply = <&vreg_l12a_1p8>;
|
||||
vdda-phy-dpdm-supply = <&vreg_l24a_3p075>;
|
||||
};
|
||||
|
||||
&rpm_requests {
|
||||
pm8998-regulators {
|
||||
compatible = "qcom,rpm-pm8998-regulators";
|
||||
|
||||
vdd_s1-supply = <&vph_pwr>;
|
||||
vdd_s2-supply = <&vph_pwr>;
|
||||
vdd_s3-supply = <&vph_pwr>;
|
||||
vdd_s4-supply = <&vph_pwr>;
|
||||
vdd_s5-supply = <&vph_pwr>;
|
||||
vdd_s6-supply = <&vph_pwr>;
|
||||
vdd_s7-supply = <&vph_pwr>;
|
||||
vdd_s8-supply = <&vph_pwr>;
|
||||
vdd_s9-supply = <&vph_pwr>;
|
||||
vdd_s10-supply = <&vph_pwr>;
|
||||
vdd_s11-supply = <&vph_pwr>;
|
||||
vdd_s12-supply = <&vph_pwr>;
|
||||
vdd_s13-supply = <&vph_pwr>;
|
||||
vdd_l1_l27-supply = <&vreg_s7a_1p025>;
|
||||
vdd_l2_l8_l17-supply = <&vreg_s3a_1p35>;
|
||||
vdd_l3_l11-supply = <&vreg_s7a_1p025>;
|
||||
vdd_l4_l5-supply = <&vreg_s7a_1p025>;
|
||||
vdd_l6-supply = <&vreg_s5a_2p04>;
|
||||
vdd_l7_l12_l14_l15-supply = <&vreg_s5a_2p04>;
|
||||
vdd_l9-supply = <&vreg_bob>;
|
||||
vdd_l10_l23_l25-supply = <&vreg_bob>;
|
||||
vdd_l13_l19_l21-supply = <&vreg_bob>;
|
||||
vdd_l16_l28-supply = <&vreg_bob>;
|
||||
vdd_l18_l22-supply = <&vreg_bob>;
|
||||
vdd_l20_l24-supply = <&vreg_bob>;
|
||||
vdd_l26-supply = <&vreg_s3a_1p35>;
|
||||
vdd_lvs1_lvs2-supply = <&vreg_s4a_1p8>;
|
||||
|
||||
vreg_s3a_1p35: s3 {
|
||||
regulator-min-microvolt = <1352000>;
|
||||
regulator-max-microvolt = <1352000>;
|
||||
};
|
||||
vreg_s4a_1p8: s4 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-allow-set-load;
|
||||
};
|
||||
vreg_s5a_2p04: s5 {
|
||||
regulator-min-microvolt = <1904000>;
|
||||
regulator-max-microvolt = <2040000>;
|
||||
};
|
||||
vreg_s7a_1p025: s7 {
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <1028000>;
|
||||
};
|
||||
vreg_l1a_0p875: l1 {
|
||||
regulator-min-microvolt = <880000>;
|
||||
regulator-max-microvolt = <880000>;
|
||||
};
|
||||
vreg_l2a_1p2: l2 {
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
};
|
||||
vreg_l3a_1p0: l3 {
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
};
|
||||
vreg_l5a_0p8: l5 {
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <800000>;
|
||||
};
|
||||
vreg_l6a_1p8: l6 {
|
||||
regulator-min-microvolt = <1808000>;
|
||||
regulator-max-microvolt = <1808000>;
|
||||
};
|
||||
vreg_l7a_1p8: l7 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
};
|
||||
vreg_l8a_1p2: l8 {
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
};
|
||||
vreg_l9a_1p8: l9 {
|
||||
regulator-min-microvolt = <1808000>;
|
||||
regulator-max-microvolt = <2960000>;
|
||||
};
|
||||
vreg_l10a_1p8: l10 {
|
||||
regulator-min-microvolt = <1808000>;
|
||||
regulator-max-microvolt = <2960000>;
|
||||
};
|
||||
vreg_l11a_1p0: l11 {
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
};
|
||||
vreg_l12a_1p8: l12 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
};
|
||||
vreg_l13a_2p95: l13 {
|
||||
regulator-min-microvolt = <1808000>;
|
||||
regulator-max-microvolt = <2960000>;
|
||||
};
|
||||
vreg_l14a_1p88: l14 {
|
||||
regulator-min-microvolt = <1880000>;
|
||||
regulator-max-microvolt = <1880000>;
|
||||
};
|
||||
vreg_l15a_1p8: l15 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
};
|
||||
vreg_l16a_2p7: l16 {
|
||||
regulator-min-microvolt = <2704000>;
|
||||
regulator-max-microvolt = <2704000>;
|
||||
};
|
||||
vreg_l17a_1p3: l17 {
|
||||
regulator-min-microvolt = <1304000>;
|
||||
regulator-max-microvolt = <1304000>;
|
||||
};
|
||||
vreg_l18a_2p7: l18 {
|
||||
regulator-min-microvolt = <2704000>;
|
||||
regulator-max-microvolt = <2704000>;
|
||||
};
|
||||
vreg_l19a_3p0: l19 {
|
||||
regulator-min-microvolt = <3008000>;
|
||||
regulator-max-microvolt = <3008000>;
|
||||
};
|
||||
vreg_l20a_2p95: l20 {
|
||||
regulator-min-microvolt = <2960000>;
|
||||
regulator-max-microvolt = <2960000>;
|
||||
regulator-allow-set-load;
|
||||
};
|
||||
vreg_l21a_2p95: l21 {
|
||||
regulator-min-microvolt = <2960000>;
|
||||
regulator-max-microvolt = <2960000>;
|
||||
regulator-allow-set-load;
|
||||
regulator-system-load = <800000>;
|
||||
};
|
||||
vreg_l22a_2p85: l22 {
|
||||
regulator-min-microvolt = <2864000>;
|
||||
regulator-max-microvolt = <2864000>;
|
||||
};
|
||||
vreg_l23a_3p3: l23 {
|
||||
regulator-min-microvolt = <3312000>;
|
||||
regulator-max-microvolt = <3312000>;
|
||||
};
|
||||
vreg_l24a_3p075: l24 {
|
||||
regulator-min-microvolt = <3088000>;
|
||||
regulator-max-microvolt = <3088000>;
|
||||
};
|
||||
vreg_l25a_3p3: l25 {
|
||||
regulator-min-microvolt = <3104000>;
|
||||
regulator-max-microvolt = <3312000>;
|
||||
};
|
||||
vreg_l26a_1p2: l26 {
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-allow-set-load;
|
||||
};
|
||||
vreg_l28_3p0: l28 {
|
||||
regulator-min-microvolt = <3008000>;
|
||||
regulator-max-microvolt = <3008000>;
|
||||
};
|
||||
vreg_lvs1a_1p8: lvs1 { };
|
||||
vreg_lvs2a_1p8: lvs2 { };
|
||||
};
|
||||
|
||||
pmi8998-regulators {
|
||||
compatible = "qcom,rpm-pmi8998-regulators";
|
||||
|
||||
vdd_bob-supply = <&vph_pwr>;
|
||||
|
||||
vreg_bob: bob {
|
||||
regulator-min-microvolt = <3312000>;
|
||||
regulator-max-microvolt = <3600000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&tlmm {
|
||||
gpio-reserved-ranges = <0 4>, <81 4>;
|
||||
|
||||
hall_sensor_default: hall-sensor-default {
|
||||
pins = "gpio124";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
input-enable;
|
||||
};
|
||||
|
||||
ts_int_active: ts-int-active {
|
||||
pins = "gpio125";
|
||||
function = "gpio";
|
||||
drive-strength = <8>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
ts_reset_active: ts-reset-active {
|
||||
pins = "gpio89";
|
||||
function = "gpio";
|
||||
drive-strength = <8>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
&ufshc {
|
||||
status = "okay";
|
||||
|
||||
vcc-supply = <&vreg_l20a_2p95>;
|
||||
vccq-supply = <&vreg_l26a_1p2>;
|
||||
vccq2-supply = <&vreg_s4a_1p8>;
|
||||
vcc-max-microamp = <750000>;
|
||||
vccq-max-microamp = <560000>;
|
||||
vccq2-max-microamp = <750000>;
|
||||
};
|
||||
|
||||
&ufsphy {
|
||||
status = "okay";
|
||||
|
||||
vdda-phy-supply = <&vreg_l1a_0p875>;
|
||||
vdda-pll-supply = <&vreg_l2a_1p2>;
|
||||
vddp-ref-clk-supply = <&vreg_l26a_1p2>;
|
||||
vdda-phy-max-microamp = <51400>;
|
||||
vdda-pll-max-microamp = <14600>;
|
||||
vddp-ref-clk-max-microamp = <100>;
|
||||
vddp-ref-clk-always-on;
|
||||
};
|
||||
|
||||
&usb3 {
|
||||
status = "okay";
|
||||
|
||||
/* Disable USB3 clock requirement as the device only supports USB2 */
|
||||
qcom,select-utmi-as-pipe-clk;
|
||||
};
|
||||
|
||||
&usb3_dwc3 {
|
||||
/* Drop the unused USB 3 PHY */
|
||||
phys = <&qusb2phy>;
|
||||
phy-names = "usb2-phy";
|
||||
|
||||
/* Fastest mode for USB 2 */
|
||||
maximum-speed = "high-speed";
|
||||
|
||||
/* Force to peripheral until we can switch modes */
|
||||
dr_mode = "peripheral";
|
||||
};
|
||||
|
||||
&wifi {
|
||||
/* Leave disabled until MSS is functional */
|
||||
vdd-0.8-cx-mx-supply = <&vreg_l5a_0p8>;
|
||||
vdd-1.8-xo-supply = <&vreg_l7a_1p8>;
|
||||
vdd-1.3-rfa-supply = <&vreg_l17a_1p3>;
|
||||
vdd-3.3-ch0-supply = <&vreg_l25a_3p3>;
|
||||
};
|
||||
25
arch/arm64/boot/dts/qcom/msm8998-oneplus-dumpling.dts
Normal file
25
arch/arm64/boot/dts/qcom/msm8998-oneplus-dumpling.dts
Normal file
@ -0,0 +1,25 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* OnePlus 5T (dumpling) device tree
|
||||
*
|
||||
* Copyright (c) 2021, Jami Kettunen <jamipkettunen@gmail.com>
|
||||
*/
|
||||
|
||||
#include "msm8998-oneplus-common.dtsi"
|
||||
|
||||
/ {
|
||||
model = "OnePlus 5T";
|
||||
compatible = "oneplus,dumpling", "qcom,msm8998";
|
||||
/* Required for bootloader to select correct board */
|
||||
qcom,board-id = <8 0 17801 43>;
|
||||
};
|
||||
|
||||
/* Update the screen height values from 1920 to 2160 on the 5T */
|
||||
&framebuffer0 {
|
||||
height = <2160>;
|
||||
};
|
||||
|
||||
/* Adjust digitizer area height to match the 5T's taller panel */
|
||||
&rmi4_f12 {
|
||||
touchscreen-y-mm = <137>;
|
||||
};
|
||||
@ -1398,6 +1398,8 @@
|
||||
<&rpmpd MSM8998_VDDMX>;
|
||||
power-domain-names = "cx", "mx";
|
||||
|
||||
status = "disabled";
|
||||
|
||||
mba {
|
||||
memory-region = <&mba_mem>;
|
||||
};
|
||||
|
||||
@ -89,6 +89,16 @@ ap_ts_pen_1v8: &i2c4 {
|
||||
data-lanes = <0 1 2 3>;
|
||||
};
|
||||
|
||||
&sound {
|
||||
compatible = "google,sc7180-coachz";
|
||||
model = "sc7180-adau7002-max98357a";
|
||||
audio-routing = "PDM_DAT", "DMIC";
|
||||
};
|
||||
|
||||
&sound_multimedia0_codec {
|
||||
sound-dai = <&adau7002>;
|
||||
};
|
||||
|
||||
/* PINCTRL - modifications to sc7180-trogdor.dtsi */
|
||||
|
||||
&en_pp3300_dx_edp {
|
||||
|
||||
@ -9,6 +9,7 @@
|
||||
#include <dt-bindings/input/gpio-keys.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
|
||||
#include <dt-bindings/sound/sc7180-lpass.h>
|
||||
|
||||
/* PMICs depend on spmi_bus label and so must come after SoC */
|
||||
#include "pm6150.dtsi"
|
||||
@ -48,7 +49,7 @@
|
||||
|
||||
/* Increase the size from 2MB to 8MB */
|
||||
&rmtfs_mem {
|
||||
reg = <0x0 0x84400000 0x0 0x800000>;
|
||||
reg = <0x0 0x94600000 0x0 0x800000>;
|
||||
};
|
||||
|
||||
/ {
|
||||
@ -283,6 +284,42 @@
|
||||
max-brightness = <1023>;
|
||||
};
|
||||
};
|
||||
|
||||
sound: sound {
|
||||
compatible = "google,sc7180-trogdor";
|
||||
model = "sc7180-rt5682-max98357a-1mic";
|
||||
|
||||
audio-routing =
|
||||
"Headphone Jack", "HPOL",
|
||||
"Headphone Jack", "HPOR";
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
dai-link@0 {
|
||||
link-name = "MultiMedia0";
|
||||
reg = <MI2S_PRIMARY>;
|
||||
cpu {
|
||||
sound-dai = <&lpass_cpu MI2S_PRIMARY>;
|
||||
};
|
||||
|
||||
sound_multimedia0_codec: codec {
|
||||
sound-dai = <&alc5682 0 /* aif1 */>;
|
||||
};
|
||||
};
|
||||
|
||||
dai-link@1 {
|
||||
link-name = "MultiMedia1";
|
||||
reg = <MI2S_SECONDARY>;
|
||||
cpu {
|
||||
sound-dai = <&lpass_cpu MI2S_SECONDARY>;
|
||||
};
|
||||
|
||||
sound_multimedia1_codec: codec {
|
||||
sound-dai = <&max98357a>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&qfprom {
|
||||
@ -720,6 +757,27 @@ hp_i2c: &i2c9 {
|
||||
modem-init;
|
||||
};
|
||||
|
||||
&lpass_cpu {
|
||||
status = "okay";
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sec_mi2s_active>, <&pri_mi2s_active>, <&pri_mi2s_mclk_active>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
mi2s@0 {
|
||||
reg = <MI2S_PRIMARY>;
|
||||
qcom,playback-sd-lines = <1>;
|
||||
qcom,capture-sd-lines = <0>;
|
||||
};
|
||||
|
||||
mi2s@1 {
|
||||
reg = <MI2S_SECONDARY>;
|
||||
qcom,playback-sd-lines = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mdp {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
@ -110,9 +110,9 @@
|
||||
no-map;
|
||||
};
|
||||
|
||||
rmtfs_mem: memory@84400000 {
|
||||
rmtfs_mem: memory@94600000 {
|
||||
compatible = "qcom,rmtfs-mem";
|
||||
reg = <0x0 0x84400000 0x0 0x200000>;
|
||||
reg = <0x0 0x94600000 0x0 0x200000>;
|
||||
no-map;
|
||||
|
||||
qcom,client-id = <1>;
|
||||
|
||||
@ -22,6 +22,218 @@
|
||||
};
|
||||
};
|
||||
|
||||
&apps_rsc {
|
||||
pm7325-regulators {
|
||||
compatible = "qcom,pm7325-rpmh-regulators";
|
||||
qcom,pmic-id = "b";
|
||||
|
||||
vreg_s1b_1p8: smps1 {
|
||||
regulator-min-microvolt = <1856000>;
|
||||
regulator-max-microvolt = <2040000>;
|
||||
};
|
||||
|
||||
vreg_s7b_0p9: smps7 {
|
||||
regulator-min-microvolt = <535000>;
|
||||
regulator-max-microvolt = <1120000>;
|
||||
};
|
||||
|
||||
vreg_s8b_1p2: smps8 {
|
||||
regulator-min-microvolt = <1256000>;
|
||||
regulator-max-microvolt = <1500000>;
|
||||
};
|
||||
|
||||
vreg_l1b_0p8: ldo1 {
|
||||
regulator-min-microvolt = <825000>;
|
||||
regulator-max-microvolt = <925000>;
|
||||
};
|
||||
|
||||
vreg_l2b_3p0: ldo2 {
|
||||
regulator-min-microvolt = <2700000>;
|
||||
regulator-max-microvolt = <3544000>;
|
||||
};
|
||||
|
||||
vreg_l6b_1p2: ldo6 {
|
||||
regulator-min-microvolt = <1140000>;
|
||||
regulator-max-microvolt = <1260000>;
|
||||
};
|
||||
|
||||
vreg_l7b_2p9: ldo7 {
|
||||
regulator-min-microvolt = <2960000>;
|
||||
regulator-max-microvolt = <2960000>;
|
||||
};
|
||||
|
||||
vreg_l8b_0p9: ldo8 {
|
||||
regulator-min-microvolt = <870000>;
|
||||
regulator-max-microvolt = <970000>;
|
||||
};
|
||||
|
||||
vreg_l9b_1p2: ldo9 {
|
||||
regulator-min-microvolt = <1080000>;
|
||||
regulator-max-microvolt = <1304000>;
|
||||
};
|
||||
|
||||
vreg_l11b_1p7: ldo11 {
|
||||
regulator-min-microvolt = <1504000>;
|
||||
regulator-max-microvolt = <2000000>;
|
||||
};
|
||||
|
||||
vreg_l12b_0p8: ldo12 {
|
||||
regulator-min-microvolt = <751000>;
|
||||
regulator-max-microvolt = <824000>;
|
||||
};
|
||||
|
||||
vreg_l13b_0p8: ldo13 {
|
||||
regulator-min-microvolt = <530000>;
|
||||
regulator-max-microvolt = <824000>;
|
||||
};
|
||||
|
||||
vreg_l14b_1p2: ldo14 {
|
||||
regulator-min-microvolt = <1080000>;
|
||||
regulator-max-microvolt = <1304000>;
|
||||
};
|
||||
|
||||
vreg_l15b_0p8: ldo15 {
|
||||
regulator-min-microvolt = <765000>;
|
||||
regulator-max-microvolt = <1020000>;
|
||||
};
|
||||
|
||||
vreg_l16b_1p2: ldo16 {
|
||||
regulator-min-microvolt = <1100000>;
|
||||
regulator-max-microvolt = <1300000>;
|
||||
};
|
||||
|
||||
vreg_l17b_1p8: ldo17 {
|
||||
regulator-min-microvolt = <1700000>;
|
||||
regulator-max-microvolt = <1900000>;
|
||||
};
|
||||
|
||||
vreg_l18b_1p8: ldo18 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <2000000>;
|
||||
};
|
||||
|
||||
vreg_l19b_1p8: ldo19 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
};
|
||||
};
|
||||
|
||||
pm8350c-regulators {
|
||||
compatible = "qcom,pm8350c-rpmh-regulators";
|
||||
qcom,pmic-id = "c";
|
||||
|
||||
vreg_s1c_2p2: smps1 {
|
||||
regulator-min-microvolt = <2190000>;
|
||||
regulator-max-microvolt = <2210000>;
|
||||
};
|
||||
|
||||
vreg_s9c_1p0: smps9 {
|
||||
regulator-min-microvolt = <1010000>;
|
||||
regulator-max-microvolt = <1170000>;
|
||||
};
|
||||
|
||||
vreg_l1c_1p8: ldo1 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1980000>;
|
||||
};
|
||||
|
||||
vreg_l2c_1p8: ldo2 {
|
||||
regulator-min-microvolt = <1620000>;
|
||||
regulator-max-microvolt = <1980000>;
|
||||
};
|
||||
|
||||
vreg_l3c_3p0: ldo3 {
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <3540000>;
|
||||
};
|
||||
|
||||
vreg_l4c_1p8: ldo4 {
|
||||
regulator-min-microvolt = <1620000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
vreg_l5c_1p8: ldo5 {
|
||||
regulator-min-microvolt = <1620000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
vreg_l6c_2p9: ldo6 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <2950000>;
|
||||
};
|
||||
|
||||
vreg_l7c_3p0: ldo7 {
|
||||
regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <3544000>;
|
||||
};
|
||||
|
||||
vreg_l8c_1p8: ldo8 {
|
||||
regulator-min-microvolt = <1620000>;
|
||||
regulator-max-microvolt = <2000000>;
|
||||
};
|
||||
|
||||
vreg_l9c_2p9: ldo9 {
|
||||
regulator-min-microvolt = <2960000>;
|
||||
regulator-max-microvolt = <2960000>;
|
||||
};
|
||||
|
||||
vreg_l10c_0p8: ldo10 {
|
||||
regulator-min-microvolt = <720000>;
|
||||
regulator-max-microvolt = <1050000>;
|
||||
};
|
||||
|
||||
vreg_l11c_2p8: ldo11 {
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <3544000>;
|
||||
};
|
||||
|
||||
vreg_l12c_1p8: ldo12 {
|
||||
regulator-min-microvolt = <1650000>;
|
||||
regulator-max-microvolt = <2000000>;
|
||||
};
|
||||
|
||||
vreg_l13c_3p0: ldo13 {
|
||||
regulator-min-microvolt = <2700000>;
|
||||
regulator-max-microvolt = <3544000>;
|
||||
};
|
||||
|
||||
vreg_bob: bob {
|
||||
regulator-min-microvolt = <3008000>;
|
||||
regulator-max-microvolt = <3960000>;
|
||||
};
|
||||
};
|
||||
|
||||
pmr735a-regulators {
|
||||
compatible = "qcom,pmr735a-rpmh-regulators";
|
||||
qcom,pmic-id = "e";
|
||||
|
||||
vreg_l2e_1p2: ldo2 {
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
};
|
||||
|
||||
vreg_l3e_0p9: ldo3 {
|
||||
regulator-min-microvolt = <912000>;
|
||||
regulator-max-microvolt = <1020000>;
|
||||
};
|
||||
|
||||
vreg_l4e_1p7: ldo4 {
|
||||
regulator-min-microvolt = <1776000>;
|
||||
regulator-max-microvolt = <1890000>;
|
||||
};
|
||||
|
||||
vreg_l5e_0p8: ldo5 {
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <800000>;
|
||||
};
|
||||
|
||||
vreg_l6e_0p8: ldo6 {
|
||||
regulator-min-microvolt = <480000>;
|
||||
regulator-max-microvolt = <904000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&qupv3_id_0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
@ -8,6 +8,8 @@
|
||||
#include <dt-bindings/clock/qcom,gcc-sc7280.h>
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/mailbox/qcom-ipcc.h>
|
||||
#include <dt-bindings/power/qcom-aoss-qmp.h>
|
||||
#include <dt-bindings/power/qcom-rpmpd.h>
|
||||
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
|
||||
|
||||
@ -282,6 +284,15 @@
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
ipcc: mailbox@408000 {
|
||||
compatible = "qcom,sc7280-ipcc", "qcom,ipcc";
|
||||
reg = <0 0x00408000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
#mbox-cells = <2>;
|
||||
};
|
||||
|
||||
qupv3_id_0: geniqup@9c0000 {
|
||||
compatible = "qcom,geni-se-qup";
|
||||
reg = <0 0x009c0000 0 0x2000>;
|
||||
@ -305,6 +316,502 @@
|
||||
};
|
||||
};
|
||||
|
||||
stm@6002000 {
|
||||
compatible = "arm,coresight-stm", "arm,primecell";
|
||||
reg = <0 0x06002000 0 0x1000>,
|
||||
<0 0x16280000 0 0x180000>;
|
||||
reg-names = "stm-base", "stm-stimulus-base";
|
||||
|
||||
clocks = <&aoss_qmp>;
|
||||
clock-names = "apb_pclk";
|
||||
|
||||
out-ports {
|
||||
port {
|
||||
stm_out: endpoint {
|
||||
remote-endpoint = <&funnel0_in7>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
funnel@6041000 {
|
||||
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
|
||||
reg = <0 0x06041000 0 0x1000>;
|
||||
|
||||
clocks = <&aoss_qmp>;
|
||||
clock-names = "apb_pclk";
|
||||
|
||||
out-ports {
|
||||
port {
|
||||
funnel0_out: endpoint {
|
||||
remote-endpoint = <&merge_funnel_in0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
in-ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@7 {
|
||||
reg = <7>;
|
||||
funnel0_in7: endpoint {
|
||||
remote-endpoint = <&stm_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
funnel@6042000 {
|
||||
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
|
||||
reg = <0 0x06042000 0 0x1000>;
|
||||
|
||||
clocks = <&aoss_qmp>;
|
||||
clock-names = "apb_pclk";
|
||||
|
||||
out-ports {
|
||||
port {
|
||||
funnel1_out: endpoint {
|
||||
remote-endpoint = <&merge_funnel_in1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
in-ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@4 {
|
||||
reg = <4>;
|
||||
funnel1_in4: endpoint {
|
||||
remote-endpoint = <&apss_merge_funnel_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
funnel@6045000 {
|
||||
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
|
||||
reg = <0 0x06045000 0 0x1000>;
|
||||
|
||||
clocks = <&aoss_qmp>;
|
||||
clock-names = "apb_pclk";
|
||||
|
||||
out-ports {
|
||||
port {
|
||||
merge_funnel_out: endpoint {
|
||||
remote-endpoint = <&swao_funnel_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
in-ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
merge_funnel_in0: endpoint {
|
||||
remote-endpoint = <&funnel0_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
merge_funnel_in1: endpoint {
|
||||
remote-endpoint = <&funnel1_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
replicator@6046000 {
|
||||
compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
|
||||
reg = <0 0x06046000 0 0x1000>;
|
||||
|
||||
clocks = <&aoss_qmp>;
|
||||
clock-names = "apb_pclk";
|
||||
|
||||
out-ports {
|
||||
port {
|
||||
replicator_out: endpoint {
|
||||
remote-endpoint = <&etr_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
in-ports {
|
||||
port {
|
||||
replicator_in: endpoint {
|
||||
remote-endpoint = <&swao_replicator_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
etr@6048000 {
|
||||
compatible = "arm,coresight-tmc", "arm,primecell";
|
||||
reg = <0 0x06048000 0 0x1000>;
|
||||
iommus = <&apps_smmu 0x04c0 0>;
|
||||
|
||||
clocks = <&aoss_qmp>;
|
||||
clock-names = "apb_pclk";
|
||||
arm,scatter-gather;
|
||||
|
||||
in-ports {
|
||||
port {
|
||||
etr_in: endpoint {
|
||||
remote-endpoint = <&replicator_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
funnel@6b04000 {
|
||||
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
|
||||
reg = <0 0x06b04000 0 0x1000>;
|
||||
|
||||
clocks = <&aoss_qmp>;
|
||||
clock-names = "apb_pclk";
|
||||
|
||||
out-ports {
|
||||
port {
|
||||
swao_funnel_out: endpoint {
|
||||
remote-endpoint = <&etf_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
in-ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@7 {
|
||||
reg = <7>;
|
||||
swao_funnel_in: endpoint {
|
||||
remote-endpoint = <&merge_funnel_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
etf@6b05000 {
|
||||
compatible = "arm,coresight-tmc", "arm,primecell";
|
||||
reg = <0 0x06b05000 0 0x1000>;
|
||||
|
||||
clocks = <&aoss_qmp>;
|
||||
clock-names = "apb_pclk";
|
||||
|
||||
out-ports {
|
||||
port {
|
||||
etf_out: endpoint {
|
||||
remote-endpoint = <&swao_replicator_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
in-ports {
|
||||
port {
|
||||
etf_in: endpoint {
|
||||
remote-endpoint = <&swao_funnel_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
replicator@6b06000 {
|
||||
compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
|
||||
reg = <0 0x06b06000 0 0x1000>;
|
||||
|
||||
clocks = <&aoss_qmp>;
|
||||
clock-names = "apb_pclk";
|
||||
qcom,replicator-loses-context;
|
||||
|
||||
out-ports {
|
||||
port {
|
||||
swao_replicator_out: endpoint {
|
||||
remote-endpoint = <&replicator_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
in-ports {
|
||||
port {
|
||||
swao_replicator_in: endpoint {
|
||||
remote-endpoint = <&etf_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
etm@7040000 {
|
||||
compatible = "arm,coresight-etm4x", "arm,primecell";
|
||||
reg = <0 0x07040000 0 0x1000>;
|
||||
|
||||
cpu = <&CPU0>;
|
||||
|
||||
clocks = <&aoss_qmp>;
|
||||
clock-names = "apb_pclk";
|
||||
arm,coresight-loses-context-with-cpu;
|
||||
qcom,skip-power-up;
|
||||
|
||||
out-ports {
|
||||
port {
|
||||
etm0_out: endpoint {
|
||||
remote-endpoint = <&apss_funnel_in0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
etm@7140000 {
|
||||
compatible = "arm,coresight-etm4x", "arm,primecell";
|
||||
reg = <0 0x07140000 0 0x1000>;
|
||||
|
||||
cpu = <&CPU1>;
|
||||
|
||||
clocks = <&aoss_qmp>;
|
||||
clock-names = "apb_pclk";
|
||||
arm,coresight-loses-context-with-cpu;
|
||||
qcom,skip-power-up;
|
||||
|
||||
out-ports {
|
||||
port {
|
||||
etm1_out: endpoint {
|
||||
remote-endpoint = <&apss_funnel_in1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
etm@7240000 {
|
||||
compatible = "arm,coresight-etm4x", "arm,primecell";
|
||||
reg = <0 0x07240000 0 0x1000>;
|
||||
|
||||
cpu = <&CPU2>;
|
||||
|
||||
clocks = <&aoss_qmp>;
|
||||
clock-names = "apb_pclk";
|
||||
arm,coresight-loses-context-with-cpu;
|
||||
qcom,skip-power-up;
|
||||
|
||||
out-ports {
|
||||
port {
|
||||
etm2_out: endpoint {
|
||||
remote-endpoint = <&apss_funnel_in2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
etm@7340000 {
|
||||
compatible = "arm,coresight-etm4x", "arm,primecell";
|
||||
reg = <0 0x07340000 0 0x1000>;
|
||||
|
||||
cpu = <&CPU3>;
|
||||
|
||||
clocks = <&aoss_qmp>;
|
||||
clock-names = "apb_pclk";
|
||||
arm,coresight-loses-context-with-cpu;
|
||||
qcom,skip-power-up;
|
||||
|
||||
out-ports {
|
||||
port {
|
||||
etm3_out: endpoint {
|
||||
remote-endpoint = <&apss_funnel_in3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
etm@7440000 {
|
||||
compatible = "arm,coresight-etm4x", "arm,primecell";
|
||||
reg = <0 0x07440000 0 0x1000>;
|
||||
|
||||
cpu = <&CPU4>;
|
||||
|
||||
clocks = <&aoss_qmp>;
|
||||
clock-names = "apb_pclk";
|
||||
arm,coresight-loses-context-with-cpu;
|
||||
qcom,skip-power-up;
|
||||
|
||||
out-ports {
|
||||
port {
|
||||
etm4_out: endpoint {
|
||||
remote-endpoint = <&apss_funnel_in4>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
etm@7540000 {
|
||||
compatible = "arm,coresight-etm4x", "arm,primecell";
|
||||
reg = <0 0x07540000 0 0x1000>;
|
||||
|
||||
cpu = <&CPU5>;
|
||||
|
||||
clocks = <&aoss_qmp>;
|
||||
clock-names = "apb_pclk";
|
||||
arm,coresight-loses-context-with-cpu;
|
||||
qcom,skip-power-up;
|
||||
|
||||
out-ports {
|
||||
port {
|
||||
etm5_out: endpoint {
|
||||
remote-endpoint = <&apss_funnel_in5>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
etm@7640000 {
|
||||
compatible = "arm,coresight-etm4x", "arm,primecell";
|
||||
reg = <0 0x07640000 0 0x1000>;
|
||||
|
||||
cpu = <&CPU6>;
|
||||
|
||||
clocks = <&aoss_qmp>;
|
||||
clock-names = "apb_pclk";
|
||||
arm,coresight-loses-context-with-cpu;
|
||||
qcom,skip-power-up;
|
||||
|
||||
out-ports {
|
||||
port {
|
||||
etm6_out: endpoint {
|
||||
remote-endpoint = <&apss_funnel_in6>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
etm@7740000 {
|
||||
compatible = "arm,coresight-etm4x", "arm,primecell";
|
||||
reg = <0 0x07740000 0 0x1000>;
|
||||
|
||||
cpu = <&CPU7>;
|
||||
|
||||
clocks = <&aoss_qmp>;
|
||||
clock-names = "apb_pclk";
|
||||
arm,coresight-loses-context-with-cpu;
|
||||
qcom,skip-power-up;
|
||||
|
||||
out-ports {
|
||||
port {
|
||||
etm7_out: endpoint {
|
||||
remote-endpoint = <&apss_funnel_in7>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
funnel@7800000 { /* APSS Funnel */
|
||||
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
|
||||
reg = <0 0x07800000 0 0x1000>;
|
||||
|
||||
clocks = <&aoss_qmp>;
|
||||
clock-names = "apb_pclk";
|
||||
|
||||
out-ports {
|
||||
port {
|
||||
apss_funnel_out: endpoint {
|
||||
remote-endpoint = <&apss_merge_funnel_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
in-ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
apss_funnel_in0: endpoint {
|
||||
remote-endpoint = <&etm0_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
apss_funnel_in1: endpoint {
|
||||
remote-endpoint = <&etm1_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
apss_funnel_in2: endpoint {
|
||||
remote-endpoint = <&etm2_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@3 {
|
||||
reg = <3>;
|
||||
apss_funnel_in3: endpoint {
|
||||
remote-endpoint = <&etm3_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@4 {
|
||||
reg = <4>;
|
||||
apss_funnel_in4: endpoint {
|
||||
remote-endpoint = <&etm4_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@5 {
|
||||
reg = <5>;
|
||||
apss_funnel_in5: endpoint {
|
||||
remote-endpoint = <&etm5_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@6 {
|
||||
reg = <6>;
|
||||
apss_funnel_in6: endpoint {
|
||||
remote-endpoint = <&etm6_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@7 {
|
||||
reg = <7>;
|
||||
apss_funnel_in7: endpoint {
|
||||
remote-endpoint = <&etm7_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
funnel@7810000 {
|
||||
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
|
||||
reg = <0 0x07810000 0 0x1000>;
|
||||
|
||||
clocks = <&aoss_qmp>;
|
||||
clock-names = "apb_pclk";
|
||||
|
||||
out-ports {
|
||||
port {
|
||||
apss_merge_funnel_out: endpoint {
|
||||
remote-endpoint = <&funnel1_in4>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
in-ports {
|
||||
port {
|
||||
apss_merge_funnel_in: endpoint {
|
||||
remote-endpoint = <&apss_funnel_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
system-cache-controller@9200000 {
|
||||
compatible = "qcom,sc7280-llcc";
|
||||
reg = <0 0x09200000 0 0xd0000>, <0 0x09600000 0 0x50000>;
|
||||
reg-names = "llcc_base", "llcc_broadcast_base";
|
||||
interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
pdc: interrupt-controller@b220000 {
|
||||
compatible = "qcom,sc7280-pdc", "qcom,pdc";
|
||||
reg = <0 0x0b220000 0 0x30000>;
|
||||
@ -318,6 +825,19 @@
|
||||
interrupt-controller;
|
||||
};
|
||||
|
||||
aoss_qmp: power-controller@c300000 {
|
||||
compatible = "qcom,sc7280-aoss-qmp";
|
||||
reg = <0 0x0c300000 0 0x100000>;
|
||||
interrupts-extended = <&ipcc IPCC_CLIENT_AOP
|
||||
IPCC_MPROC_SIGNAL_GLINK_QMP
|
||||
IRQ_TYPE_EDGE_RISING>;
|
||||
mboxes = <&ipcc IPCC_CLIENT_AOP
|
||||
IPCC_MPROC_SIGNAL_GLINK_QMP>;
|
||||
|
||||
#clock-cells = <0>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
spmi_bus: spmi@c440000 {
|
||||
compatible = "qcom,spmi-pmic-arb";
|
||||
reg = <0 0x0c440000 0 0x1100>,
|
||||
|
||||
@ -244,7 +244,7 @@
|
||||
&adsp_pas {
|
||||
status = "okay";
|
||||
|
||||
firmware-name = "qcom/sdm845/adsp.mdt";
|
||||
firmware-name = "qcom/sdm845/adsp.mbn";
|
||||
};
|
||||
|
||||
&apps_rsc {
|
||||
@ -390,7 +390,7 @@
|
||||
|
||||
&cdsp_pas {
|
||||
status = "okay";
|
||||
firmware-name = "qcom/sdm845/cdsp.mdt";
|
||||
firmware-name = "qcom/sdm845/cdsp.mbn";
|
||||
};
|
||||
|
||||
&dsi0 {
|
||||
|
||||
@ -157,6 +157,14 @@
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l14a_1p8: ldo14 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vreg_l17a_1p3: ldo17 {
|
||||
regulator-min-microvolt = <1304000>;
|
||||
regulator-max-microvolt = <1304000>;
|
||||
@ -191,6 +199,7 @@
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
regulator-boot-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -200,6 +209,43 @@
|
||||
firmware-name = "qcom/sdm845/cdsp.mdt";
|
||||
};
|
||||
|
||||
&dsi0 {
|
||||
status = "okay";
|
||||
vdda-supply = <&vreg_l26a_1p2>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
panel@0 {
|
||||
compatible = "tianma,fhd-video";
|
||||
reg = <0>;
|
||||
vddi0-supply = <&vreg_l14a_1p8>;
|
||||
vddpos-supply = <&lab>;
|
||||
vddneg-supply = <&ibb>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>;
|
||||
|
||||
port {
|
||||
tianma_nt36672a_in_0: endpoint {
|
||||
remote-endpoint = <&dsi0_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi0_out {
|
||||
remote-endpoint = <&tianma_nt36672a_in_0>;
|
||||
data-lanes = <0 1 2 3>;
|
||||
};
|
||||
|
||||
&dsi0_phy {
|
||||
status = "okay";
|
||||
vdds-supply = <&vreg_l1a_0p875>;
|
||||
};
|
||||
|
||||
&gcc {
|
||||
protected-clocks = <GCC_QSPI_CORE_CLK>,
|
||||
<GCC_QSPI_CORE_CLK_SRC>,
|
||||
@ -215,6 +261,31 @@
|
||||
};
|
||||
};
|
||||
|
||||
&ibb {
|
||||
regulator-min-microvolt = <4600000>;
|
||||
regulator-max-microvolt = <6000000>;
|
||||
regulator-over-current-protection;
|
||||
regulator-pull-down;
|
||||
regulator-soft-start;
|
||||
qcom,discharge-resistor-kohms = <300>;
|
||||
};
|
||||
|
||||
&lab {
|
||||
regulator-min-microvolt = <4600000>;
|
||||
regulator-max-microvolt = <6000000>;
|
||||
regulator-over-current-protection;
|
||||
regulator-pull-down;
|
||||
regulator-soft-start;
|
||||
};
|
||||
|
||||
&mdss {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mdss_mdp {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mss_pil {
|
||||
status = "okay";
|
||||
firmware-name = "qcom/sdm845/mba.mbn", "qcom/sdm845/modem.mdt";
|
||||
|
||||
@ -1061,6 +1061,16 @@
|
||||
gcc: clock-controller@100000 {
|
||||
compatible = "qcom,gcc-sdm845";
|
||||
reg = <0 0x00100000 0 0x1f0000>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK_A>,
|
||||
<&sleep_clk>,
|
||||
<&pcie0_lane>,
|
||||
<&pcie1_lane>;
|
||||
clock-names = "bi_tcxo",
|
||||
"bi_tcxo_ao",
|
||||
"sleep_clk",
|
||||
"pcie_0_pipe_clk",
|
||||
"pcie_1_pipe_clk";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
@ -2062,6 +2072,7 @@
|
||||
clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
|
||||
clock-names = "pipe0";
|
||||
|
||||
#clock-cells = <0>;
|
||||
#phy-cells = <0>;
|
||||
clock-output-names = "pcie_0_pipe_clk";
|
||||
};
|
||||
@ -2170,6 +2181,7 @@
|
||||
clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
|
||||
clock-names = "pipe0";
|
||||
|
||||
#clock-cells = <0>;
|
||||
#phy-cells = <0>;
|
||||
clock-output-names = "pcie_1_pipe_clk";
|
||||
};
|
||||
@ -3673,7 +3685,6 @@
|
||||
<0 0x088e8000 0 0x10>;
|
||||
reg-names = "reg-base", "dp_com";
|
||||
status = "disabled";
|
||||
#clock-cells = <1>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
@ -3695,6 +3706,7 @@
|
||||
<0 0x088e9600 0 0x128>,
|
||||
<0 0x088e9800 0 0x200>,
|
||||
<0 0x088e9a00 0 0x100>;
|
||||
#clock-cells = <0>;
|
||||
#phy-cells = <0>;
|
||||
clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
|
||||
clock-names = "pipe0";
|
||||
@ -3706,7 +3718,6 @@
|
||||
compatible = "qcom,sdm845-qmp-usb3-uni-phy";
|
||||
reg = <0 0x088eb000 0 0x18c>;
|
||||
status = "disabled";
|
||||
#clock-cells = <1>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
@ -3726,6 +3737,7 @@
|
||||
<0 0x088eb400 0 0x1fc>,
|
||||
<0 0x088eb800 0 0x218>,
|
||||
<0 0x088eb600 0 0x70>;
|
||||
#clock-cells = <0>;
|
||||
#phy-cells = <0>;
|
||||
clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
|
||||
clock-names = "pipe0";
|
||||
|
||||
@ -577,17 +577,188 @@
|
||||
<&sleep_clk>;
|
||||
};
|
||||
|
||||
qupv3_id_0: geniqup@8c0000 {
|
||||
compatible = "qcom,geni-se-qup";
|
||||
reg = <0x0 0x008c0000 0x0 0x6000>;
|
||||
clock-names = "m-ahb", "s-ahb";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
|
||||
iommus = <&apps_smmu 0xc3 0x0>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
status = "disabled";
|
||||
|
||||
i2c0: i2c@880000 {
|
||||
compatible = "qcom,geni-i2c";
|
||||
reg = <0 0x00880000 0 0x4000>;
|
||||
clock-names = "se";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&qup_i2c0_default>;
|
||||
interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c1: i2c@884000 {
|
||||
compatible = "qcom,geni-i2c";
|
||||
reg = <0 0x00884000 0 0x4000>;
|
||||
clock-names = "se";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&qup_i2c1_default>;
|
||||
interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c2: i2c@888000 {
|
||||
compatible = "qcom,geni-i2c";
|
||||
reg = <0 0x00888000 0 0x4000>;
|
||||
clock-names = "se";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&qup_i2c2_default>;
|
||||
interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c3: i2c@88c000 {
|
||||
compatible = "qcom,geni-i2c";
|
||||
reg = <0 0x0088c000 0 0x4000>;
|
||||
clock-names = "se";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&qup_i2c3_default>;
|
||||
interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c4: i2c@890000 {
|
||||
compatible = "qcom,geni-i2c";
|
||||
reg = <0 0x00890000 0 0x4000>;
|
||||
clock-names = "se";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&qup_i2c4_default>;
|
||||
interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c5: i2c@894000 {
|
||||
compatible = "qcom,geni-i2c";
|
||||
reg = <0 0x00894000 0 0x4000>;
|
||||
clock-names = "se";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&qup_i2c5_default>;
|
||||
interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c6: i2c@898000 {
|
||||
compatible = "qcom,geni-i2c";
|
||||
reg = <0 0x00898000 0 0x4000>;
|
||||
clock-names = "se";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&qup_i2c6_default>;
|
||||
interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c7: i2c@89c000 {
|
||||
compatible = "qcom,geni-i2c";
|
||||
reg = <0 0x0089c000 0 0x4000>;
|
||||
clock-names = "se";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&qup_i2c7_default>;
|
||||
interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
qupv3_id_1: geniqup@ac0000 {
|
||||
compatible = "qcom,geni-se-qup";
|
||||
reg = <0x0 0x00ac0000 0x0 0x6000>;
|
||||
clock-names = "m-ahb", "s-ahb";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
|
||||
iommus = <&apps_smmu 0x603 0x0>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
status = "disabled";
|
||||
|
||||
i2c8: i2c@a80000 {
|
||||
compatible = "qcom,geni-i2c";
|
||||
reg = <0 0x00a80000 0 0x4000>;
|
||||
clock-names = "se";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&qup_i2c8_default>;
|
||||
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c9: i2c@a84000 {
|
||||
compatible = "qcom,geni-i2c";
|
||||
reg = <0 0x00a84000 0 0x4000>;
|
||||
clock-names = "se";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&qup_i2c9_default>;
|
||||
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c10: i2c@a88000 {
|
||||
compatible = "qcom,geni-i2c";
|
||||
reg = <0 0x00a88000 0 0x4000>;
|
||||
clock-names = "se";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&qup_i2c10_default>;
|
||||
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c11: i2c@a8c000 {
|
||||
compatible = "qcom,geni-i2c";
|
||||
reg = <0 0x00a8c000 0 0x4000>;
|
||||
clock-names = "se";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&qup_i2c11_default>;
|
||||
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart2: serial@a90000 {
|
||||
compatible = "qcom,geni-debug-uart";
|
||||
reg = <0x0 0x00a90000 0x0 0x4000>;
|
||||
@ -596,6 +767,124 @@
|
||||
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c12: i2c@a90000 {
|
||||
compatible = "qcom,geni-i2c";
|
||||
reg = <0 0x00a90000 0 0x4000>;
|
||||
clock-names = "se";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&qup_i2c12_default>;
|
||||
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c16: i2c@94000 {
|
||||
compatible = "qcom,geni-i2c";
|
||||
reg = <0 0x0094000 0 0x4000>;
|
||||
clock-names = "se";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&qup_i2c16_default>;
|
||||
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
qupv3_id_2: geniqup@cc0000 {
|
||||
compatible = "qcom,geni-se-qup";
|
||||
reg = <0x0 0x00cc0000 0x0 0x6000>;
|
||||
|
||||
clock-names = "m-ahb", "s-ahb";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
|
||||
iommus = <&apps_smmu 0x7a3 0x0>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
status = "disabled";
|
||||
|
||||
i2c17: i2c@c80000 {
|
||||
compatible = "qcom,geni-i2c";
|
||||
reg = <0 0x00c80000 0 0x4000>;
|
||||
clock-names = "se";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&qup_i2c17_default>;
|
||||
interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c18: i2c@c84000 {
|
||||
compatible = "qcom,geni-i2c";
|
||||
reg = <0 0x00c84000 0 0x4000>;
|
||||
clock-names = "se";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&qup_i2c18_default>;
|
||||
interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c19: i2c@c88000 {
|
||||
compatible = "qcom,geni-i2c";
|
||||
reg = <0 0x00c88000 0 0x4000>;
|
||||
clock-names = "se";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&qup_i2c19_default>;
|
||||
interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c13: i2c@c8c000 {
|
||||
compatible = "qcom,geni-i2c";
|
||||
reg = <0 0x00c8c000 0 0x4000>;
|
||||
clock-names = "se";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&qup_i2c13_default>;
|
||||
interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c14: i2c@c90000 {
|
||||
compatible = "qcom,geni-i2c";
|
||||
reg = <0 0x00c90000 0 0x4000>;
|
||||
clock-names = "se";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&qup_i2c14_default>;
|
||||
interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c15: i2c@c94000 {
|
||||
compatible = "qcom,geni-i2c";
|
||||
reg = <0 0x00c94000 0 0x4000>;
|
||||
clock-names = "se";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&qup_i2c15_default>;
|
||||
interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
config_noc: interconnect@1500000 {
|
||||
@ -919,6 +1208,266 @@
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
|
||||
qup_i2c0_default: qup-i2c0-default {
|
||||
mux {
|
||||
pins = "gpio0", "gpio1";
|
||||
function = "qup0";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio0", "gpio1";
|
||||
drive-strength = <0x02>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
qup_i2c1_default: qup-i2c1-default {
|
||||
mux {
|
||||
pins = "gpio114", "gpio115";
|
||||
function = "qup1";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio114", "gpio115";
|
||||
drive-strength = <0x02>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
qup_i2c2_default: qup-i2c2-default {
|
||||
mux {
|
||||
pins = "gpio126", "gpio127";
|
||||
function = "qup2";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio126", "gpio127";
|
||||
drive-strength = <0x02>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
qup_i2c3_default: qup-i2c3-default {
|
||||
mux {
|
||||
pins = "gpio144", "gpio145";
|
||||
function = "qup3";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio144", "gpio145";
|
||||
drive-strength = <0x02>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
qup_i2c4_default: qup-i2c4-default {
|
||||
mux {
|
||||
pins = "gpio51", "gpio52";
|
||||
function = "qup4";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio51", "gpio52";
|
||||
drive-strength = <0x02>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
qup_i2c5_default: qup-i2c5-default {
|
||||
mux {
|
||||
pins = "gpio121", "gpio122";
|
||||
function = "qup5";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio121", "gpio122";
|
||||
drive-strength = <0x02>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
qup_i2c6_default: qup-i2c6-default {
|
||||
mux {
|
||||
pins = "gpio6", "gpio7";
|
||||
function = "qup6";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio6", "gpio7";
|
||||
drive-strength = <0x02>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
qup_i2c7_default: qup-i2c7-default {
|
||||
mux {
|
||||
pins = "gpio98", "gpio99";
|
||||
function = "qup7";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio98", "gpio99";
|
||||
drive-strength = <0x02>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
qup_i2c8_default: qup-i2c8-default {
|
||||
mux {
|
||||
pins = "gpio88", "gpio89";
|
||||
function = "qup8";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio88", "gpio89";
|
||||
drive-strength = <0x02>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
qup_i2c9_default: qup-i2c9-default {
|
||||
mux {
|
||||
pins = "gpio39", "gpio40";
|
||||
function = "qup9";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio39", "gpio40";
|
||||
drive-strength = <0x02>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
qup_i2c10_default: qup-i2c10-default {
|
||||
mux {
|
||||
pins = "gpio9", "gpio10";
|
||||
function = "qup10";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio9", "gpio10";
|
||||
drive-strength = <0x02>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
qup_i2c11_default: qup-i2c11-default {
|
||||
mux {
|
||||
pins = "gpio94", "gpio95";
|
||||
function = "qup11";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio94", "gpio95";
|
||||
drive-strength = <0x02>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
qup_i2c12_default: qup-i2c12-default {
|
||||
mux {
|
||||
pins = "gpio83", "gpio84";
|
||||
function = "qup12";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio83", "gpio84";
|
||||
drive-strength = <0x02>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
qup_i2c13_default: qup-i2c13-default {
|
||||
mux {
|
||||
pins = "gpio43", "gpio44";
|
||||
function = "qup13";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio43", "gpio44";
|
||||
drive-strength = <0x02>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
qup_i2c14_default: qup-i2c14-default {
|
||||
mux {
|
||||
pins = "gpio47", "gpio48";
|
||||
function = "qup14";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio47", "gpio48";
|
||||
drive-strength = <0x02>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
qup_i2c15_default: qup-i2c15-default {
|
||||
mux {
|
||||
pins = "gpio27", "gpio28";
|
||||
function = "qup15";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio27", "gpio28";
|
||||
drive-strength = <0x02>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
qup_i2c16_default: qup-i2c16-default {
|
||||
mux {
|
||||
pins = "gpio86", "gpio85";
|
||||
function = "qup16";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio86", "gpio85";
|
||||
drive-strength = <0x02>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
qup_i2c17_default: qup-i2c17-default {
|
||||
mux {
|
||||
pins = "gpio55", "gpio56";
|
||||
function = "qup17";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio55", "gpio56";
|
||||
drive-strength = <0x02>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
qup_i2c18_default: qup-i2c18-default {
|
||||
mux {
|
||||
pins = "gpio23", "gpio24";
|
||||
function = "qup18";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio23", "gpio24";
|
||||
drive-strength = <0x02>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
qup_i2c19_default: qup-i2c19-default {
|
||||
mux {
|
||||
pins = "gpio57", "gpio58";
|
||||
function = "qup19";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio57", "gpio58";
|
||||
drive-strength = <0x02>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
remoteproc_mpss: remoteproc@4080000 {
|
||||
@ -1612,7 +2161,6 @@
|
||||
<0 0x088e8000 0 0x10>;
|
||||
reg-names = "reg-base", "dp_com";
|
||||
status = "disabled";
|
||||
#clock-cells = <1>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
@ -1634,6 +2182,7 @@
|
||||
<0 0x088e9600 0 0x200>,
|
||||
<0 0x088e9800 0 0x200>,
|
||||
<0 0x088e9a00 0 0x100>;
|
||||
#clock-cells = <0>;
|
||||
#phy-cells = <0>;
|
||||
clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
|
||||
clock-names = "pipe0";
|
||||
@ -1659,7 +2208,6 @@
|
||||
compatible = "qcom,sm8150-qmp-usb3-uni-phy";
|
||||
reg = <0 0x088eb000 0 0x200>;
|
||||
status = "disabled";
|
||||
#clock-cells = <1>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
@ -1679,6 +2227,7 @@
|
||||
<0 0x088eb400 0 0x200>,
|
||||
<0 0x088eb800 0 0x800>,
|
||||
<0 0x088eb600 0 0x200>;
|
||||
#clock-cells = <0>;
|
||||
#phy-cells = <0>;
|
||||
clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
|
||||
clock-names = "pipe0";
|
||||
|
||||
@ -17,6 +17,7 @@
|
||||
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
|
||||
#include <dt-bindings/sound/qcom,q6afe.h>
|
||||
#include <dt-bindings/thermal/thermal.h>
|
||||
#include <dt-bindings/clock/qcom,videocc-sm8250.h>
|
||||
|
||||
/ {
|
||||
interrupt-parent = <&intc>;
|
||||
@ -2057,12 +2058,11 @@
|
||||
};
|
||||
|
||||
usb_1_qmpphy: phy@88e9000 {
|
||||
compatible = "qcom,sm8250-qmp-usb3-phy";
|
||||
compatible = "qcom,sm8250-qmp-usb3-dp-phy";
|
||||
reg = <0 0x088e9000 0 0x200>,
|
||||
<0 0x088e8000 0 0x20>;
|
||||
reg-names = "reg-base", "dp_com";
|
||||
<0 0x088e8000 0 0x40>,
|
||||
<0 0x088ea000 0 0x200>;
|
||||
status = "disabled";
|
||||
#clock-cells = <1>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
@ -2076,25 +2076,39 @@
|
||||
<&gcc GCC_USB3_PHY_PRIM_BCR>;
|
||||
reset-names = "phy", "common";
|
||||
|
||||
usb_1_ssphy: lanes@88e9200 {
|
||||
usb_1_ssphy: usb3-phy@88e9200 {
|
||||
reg = <0 0x088e9200 0 0x200>,
|
||||
<0 0x088e9400 0 0x200>,
|
||||
<0 0x088e9c00 0 0x400>,
|
||||
<0 0x088e9600 0 0x200>,
|
||||
<0 0x088e9800 0 0x200>,
|
||||
<0 0x088e9a00 0 0x100>;
|
||||
#clock-cells = <0>;
|
||||
#phy-cells = <0>;
|
||||
clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
|
||||
clock-names = "pipe0";
|
||||
clock-output-names = "usb3_phy_pipe_clk_src";
|
||||
};
|
||||
|
||||
dp_phy: dp-phy@88ea200 {
|
||||
reg = <0 0x088ea200 0 0x200>,
|
||||
<0 0x088ea400 0 0x200>,
|
||||
<0 0x088eac00 0 0x400>,
|
||||
<0 0x088ea600 0 0x200>,
|
||||
<0 0x088ea800 0 0x200>,
|
||||
<0 0x088eaa00 0 0x100>;
|
||||
#phy-cells = <0>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
|
||||
clock-names = "pipe0";
|
||||
clock-output-names = "usb3_phy_pipe_clk_src";
|
||||
};
|
||||
};
|
||||
|
||||
usb_2_qmpphy: phy@88eb000 {
|
||||
compatible = "qcom,sm8250-qmp-usb3-uni-phy";
|
||||
reg = <0 0x088eb000 0 0x200>;
|
||||
status = "disabled";
|
||||
#clock-cells = <1>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
@ -2113,6 +2127,7 @@
|
||||
reg = <0 0x088eb200 0 0x200>,
|
||||
<0 0x088eb400 0 0x200>,
|
||||
<0 0x088eb800 0 0x800>;
|
||||
#clock-cells = <0>;
|
||||
#phy-cells = <0>;
|
||||
clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
|
||||
clock-names = "pipe0";
|
||||
@ -2282,15 +2297,86 @@
|
||||
};
|
||||
};
|
||||
|
||||
venus: video-codec@aa00000 {
|
||||
compatible = "qcom,sm8250-venus";
|
||||
reg = <0 0x0aa00000 0 0x100000>;
|
||||
interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
|
||||
power-domains = <&videocc MVS0C_GDSC>,
|
||||
<&videocc MVS0_GDSC>,
|
||||
<&rpmhpd SM8250_MX>;
|
||||
power-domain-names = "venus", "vcodec0", "mx";
|
||||
operating-points-v2 = <&venus_opp_table>;
|
||||
|
||||
clocks = <&gcc GCC_VIDEO_AXI0_CLK>,
|
||||
<&videocc VIDEO_CC_MVS0C_CLK>,
|
||||
<&videocc VIDEO_CC_MVS0_CLK>;
|
||||
clock-names = "iface", "core", "vcodec0_core";
|
||||
|
||||
interconnects = <&gem_noc MASTER_AMPSS_M0 &config_noc SLAVE_VENUS_CFG>,
|
||||
<&mmss_noc MASTER_VIDEO_P0 &mc_virt SLAVE_EBI_CH0>;
|
||||
interconnect-names = "cpu-cfg", "video-mem";
|
||||
|
||||
iommus = <&apps_smmu 0x2100 0x0400>;
|
||||
memory-region = <&video_mem>;
|
||||
|
||||
resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>,
|
||||
<&videocc VIDEO_CC_MVS0C_CLK_ARES>;
|
||||
reset-names = "bus", "core";
|
||||
|
||||
video-decoder {
|
||||
compatible = "venus-decoder";
|
||||
};
|
||||
|
||||
video-encoder {
|
||||
compatible = "venus-encoder";
|
||||
};
|
||||
|
||||
venus_opp_table: venus-opp-table {
|
||||
compatible = "operating-points-v2";
|
||||
|
||||
opp-720000000 {
|
||||
opp-hz = /bits/ 64 <720000000>;
|
||||
required-opps = <&rpmhpd_opp_low_svs>;
|
||||
};
|
||||
|
||||
opp-1014000000 {
|
||||
opp-hz = /bits/ 64 <1014000000>;
|
||||
required-opps = <&rpmhpd_opp_svs>;
|
||||
};
|
||||
|
||||
opp-1098000000 {
|
||||
opp-hz = /bits/ 64 <1098000000>;
|
||||
required-opps = <&rpmhpd_opp_svs_l1>;
|
||||
};
|
||||
|
||||
opp-1332000000 {
|
||||
opp-hz = /bits/ 64 <1332000000>;
|
||||
required-opps = <&rpmhpd_opp_nom>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
videocc: clock-controller@abf0000 {
|
||||
compatible = "qcom,sm8250-videocc";
|
||||
reg = <0 0x0abf0000 0 0x10000>;
|
||||
clocks = <&gcc GCC_VIDEO_AHB_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK_A>;
|
||||
mmcx-supply = <&mmcx_reg>;
|
||||
clock-names = "iface", "bi_tcxo", "bi_tcxo_ao";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
mdss: mdss@ae00000 {
|
||||
compatible = "qcom,sdm845-mdss";
|
||||
reg = <0 0x0ae00000 0 0x1000>;
|
||||
reg-names = "mdss";
|
||||
|
||||
interconnects = <&gem_noc MASTER_AMPSS_M0 &config_noc SLAVE_DISPLAY_CFG>,
|
||||
<&mmss_noc MASTER_MDP_PORT0 &mc_virt SLAVE_EBI_CH0>,
|
||||
interconnects = <&mmss_noc MASTER_MDP_PORT0 &mc_virt SLAVE_EBI_CH0>,
|
||||
<&mmss_noc MASTER_MDP_PORT1 &mc_virt SLAVE_EBI_CH0>;
|
||||
interconnect-names = "notused", "mdp0-mem", "mdp1-mem";
|
||||
interconnect-names = "mdp0-mem", "mdp1-mem";
|
||||
|
||||
power-domains = <&dispcc MDSS_GDSC>;
|
||||
|
||||
@ -2540,36 +2626,22 @@
|
||||
|
||||
dispcc: clock-controller@af00000 {
|
||||
compatible = "qcom,sm8250-dispcc";
|
||||
reg = <0 0x0af00000 0 0x20000>;
|
||||
reg = <0 0x0af00000 0 0x10000>;
|
||||
mmcx-supply = <&mmcx_reg>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
||||
<&dsi0_phy 0>,
|
||||
<&dsi0_phy 1>,
|
||||
<&dsi1_phy 0>,
|
||||
<&dsi1_phy 1>,
|
||||
<0>,
|
||||
<0>,
|
||||
<0>,
|
||||
<0>,
|
||||
<0>,
|
||||
<0>,
|
||||
<0>,
|
||||
<0>,
|
||||
<&sleep_clk>;
|
||||
<&dp_phy 0>,
|
||||
<&dp_phy 1>;
|
||||
clock-names = "bi_tcxo",
|
||||
"dsi0_phy_pll_out_byteclk",
|
||||
"dsi0_phy_pll_out_dsiclk",
|
||||
"dsi1_phy_pll_out_byteclk",
|
||||
"dsi1_phy_pll_out_dsiclk",
|
||||
"dp_link_clk_divsel_ten",
|
||||
"dp_vco_divided_clk_src_mux",
|
||||
"dptx1_phy_pll_link_clk",
|
||||
"dptx1_phy_pll_vco_div_clk",
|
||||
"dptx2_phy_pll_link_clk",
|
||||
"dptx2_phy_pll_vco_div_clk",
|
||||
"edp_phy_pll_link_clk",
|
||||
"edp_phy_pll_vco_div_clk",
|
||||
"sleep_clk";
|
||||
"dp_phy_pll_link_clk",
|
||||
"dp_phy_pll_vco_div_clk";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue
Block a user