ARM: dts: oxnas: remove obsolete device tree files
Due to lack of maintainance and stall of development for a few years now, and since no new features will ever be added upstream, remove support for OX810 and OX820 devices. Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Daniel Golle <daniel@makrotopia.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Neil Armstrong
Arnd Bergmann
parent
63d2b92754
commit
a9414bef86
@ -1041,9 +1041,6 @@ dtb-$(CONFIG_ARCH_PXA) += \
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pxa300-raumfeld-speaker-m.dtb \
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pxa300-raumfeld-speaker-one.dtb \
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pxa300-raumfeld-speaker-s.dtb
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dtb-$(CONFIG_ARCH_OXNAS) += \
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ox810se-wd-mbwe.dtb \
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ox820-cloudengines-pogoplug-series-3.dtb
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dtb-$(CONFIG_ARCH_QCOM) += \
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qcom-apq8016-sbc.dtb \
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qcom-apq8026-asus-sparrow.dtb \
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@ -1,115 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* wd-mbwe.dtsi - Device tree file for Western Digital My Book World Edition
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*
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* Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com>
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*/
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/dts-v1/;
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#include "ox810se.dtsi"
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/ {
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model = "Western Digital My Book World Edition";
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compatible = "wd,mbwe", "oxsemi,ox810se";
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chosen {
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bootargs = "console=ttyS1,115200n8 earlyprintk=serial";
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};
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memory {
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/* 128Mbytes DDR */
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reg = <0x48000000 0x8000000>;
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};
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aliases {
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serial1 = &uart1;
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gpio0 = &gpio0;
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gpio1 = &gpio1;
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};
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gpio-keys-polled {
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compatible = "gpio-keys-polled";
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#address-cells = <1>;
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#size-cells = <0>;
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poll-interval = <100>;
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power {
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label = "power";
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gpios = <&gpio0 0 1>;
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linux,code = <0x198>;
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};
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recovery {
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label = "recovery";
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gpios = <&gpio0 4 1>;
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linux,code = <0xab>;
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};
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};
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leds {
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compatible = "gpio-leds";
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a0 {
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label = "activity0";
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gpios = <&gpio0 25 0>;
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default-state = "keep";
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};
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a1 {
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label = "activity1";
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gpios = <&gpio0 26 0>;
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default-state = "keep";
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};
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a2 {
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label = "activity2";
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gpios = <&gpio0 5 0>;
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default-state = "keep";
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};
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a3 {
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label = "activity3";
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gpios = <&gpio0 6 0>;
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default-state = "keep";
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};
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a4 {
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label = "activity4";
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gpios = <&gpio0 7 0>;
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default-state = "keep";
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};
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a5 {
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label = "activity5";
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gpios = <&gpio1 2 0>;
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default-state = "keep";
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};
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};
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i2c-gpio {
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compatible = "i2c-gpio";
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gpios = <&gpio0 3 0 /* sda */
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&gpio0 2 0 /* scl */
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>;
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i2c-gpio,delay-us = <2>; /* ~100 kHz */
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#address-cells = <1>;
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#size-cells = <0>;
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rtc0: rtc@48 {
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compatible = "st,m41t00";
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reg = <0x68>;
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};
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};
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};
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ða {
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status = "okay";
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};
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&uart1 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1>;
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};
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@ -1,357 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* ox810se.dtsi - Device tree file for Oxford Semiconductor OX810SE SoC
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*
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* Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com>
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*/
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#include <dt-bindings/clock/oxsemi,ox810se.h>
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#include <dt-bindings/reset/oxsemi,ox810se.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "oxsemi,ox810se";
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cpus {
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#address-cells = <0>;
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#size-cells = <0>;
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cpu {
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device_type = "cpu";
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compatible = "arm,arm926ej-s";
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clocks = <&armclk>;
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};
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};
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memory {
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device_type = "memory";
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/* Max 256MB @ 0x48000000 */
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reg = <0x48000000 0x10000000>;
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};
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clocks {
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osc: oscillator {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <25000000>;
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};
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gmacclk: gmacclk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <125000000>;
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};
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rpsclk: rpsclk {
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compatible = "fixed-factor-clock";
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#clock-cells = <0>;
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clock-div = <1>;
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clock-mult = <1>;
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clocks = <&osc>;
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};
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pll400: pll400 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <733333333>;
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};
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sysclk: sysclk {
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compatible = "fixed-factor-clock";
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#clock-cells = <0>;
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clock-div = <4>;
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clock-mult = <1>;
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clocks = <&pll400>;
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};
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armclk: armclk {
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compatible = "fixed-factor-clock";
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#clock-cells = <0>;
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clock-div = <2>;
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clock-mult = <1>;
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clocks = <&pll400>;
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};
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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ranges;
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interrupt-parent = <&intc>;
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etha: ethernet@40400000 {
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compatible = "oxsemi,ox810se-dwmac", "snps,dwmac";
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reg = <0x40400000 0x2000>;
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interrupts = <8>;
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interrupt-names = "macirq";
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mac-address = [000000000000]; /* Filled in by U-Boot */
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phy-mode = "rgmii";
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clocks = <&stdclk 6>, <&gmacclk>;
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clock-names = "gmac", "stmmaceth";
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resets = <&reset 6>;
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/* Regmap for sys registers */
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oxsemi,sys-ctrl = <&sys>;
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status = "disabled";
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};
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apb-bridge@44000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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ranges = <0 0x44000000 0x1000000>;
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pinctrl: pinctrl {
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compatible = "oxsemi,ox810se-pinctrl";
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/* Regmap for sys registers */
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oxsemi,sys-ctrl = <&sys>;
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pinctrl_uart0: uart0 {
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uart0a {
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pins = "gpio31";
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function = "fct3";
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};
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uart0b {
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pins = "gpio32";
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function = "fct3";
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};
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};
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pinctrl_uart0_modem: uart0_modem {
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uart0c {
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pins = "gpio27";
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function = "fct3";
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};
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uart0d {
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pins = "gpio28";
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function = "fct3";
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};
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uart0e {
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pins = "gpio29";
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function = "fct3";
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};
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uart0f {
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pins = "gpio30";
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function = "fct3";
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};
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uart0g {
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pins = "gpio33";
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function = "fct3";
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};
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uart0h {
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pins = "gpio34";
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function = "fct3";
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};
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};
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pinctrl_uart1: uart1 {
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uart1a {
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pins = "gpio20";
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function = "fct3";
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};
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uart1b {
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pins = "gpio22";
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function = "fct3";
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};
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};
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pinctrl_uart1_modem: uart1_modem {
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uart1c {
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pins = "gpio8";
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function = "fct3";
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};
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uart1d {
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pins = "gpio9";
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function = "fct3";
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};
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uart1e {
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pins = "gpio23";
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function = "fct3";
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};
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uart1f {
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pins = "gpio24";
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function = "fct3";
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};
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uart1g {
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pins = "gpio25";
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function = "fct3";
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};
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uart1h {
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pins = "gpio26";
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function = "fct3";
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};
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};
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pinctrl_uart2: uart2 {
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uart2a {
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pins = "gpio6";
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function = "fct3";
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};
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uart2b {
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pins = "gpio7";
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function = "fct3";
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};
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};
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pinctrl_uart2_modem: uart2_modem {
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uart2c {
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pins = "gpio0";
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function = "fct3";
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};
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uart2d {
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pins = "gpio1";
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function = "fct3";
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};
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uart2e {
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pins = "gpio2";
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function = "fct3";
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};
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uart2f {
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pins = "gpio3";
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function = "fct3";
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};
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uart2g {
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pins = "gpio4";
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function = "fct3";
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};
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uart2h {
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pins = "gpio5";
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function = "fct3";
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};
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};
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};
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gpio0: gpio@0 {
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compatible = "oxsemi,ox810se-gpio";
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reg = <0x000000 0x100000>;
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interrupts = <21>;
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#gpio-cells = <2>;
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gpio-controller;
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interrupt-controller;
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#interrupt-cells = <2>;
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ngpios = <32>;
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oxsemi,gpio-bank = <0>;
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gpio-ranges = <&pinctrl 0 0 32>;
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};
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gpio1: gpio@100000 {
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compatible = "oxsemi,ox810se-gpio";
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reg = <0x100000 0x100000>;
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interrupts = <22>;
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#gpio-cells = <2>;
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gpio-controller;
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interrupt-controller;
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#interrupt-cells = <2>;
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ngpios = <3>;
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oxsemi,gpio-bank = <1>;
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gpio-ranges = <&pinctrl 0 32 3>;
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};
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uart0: serial@200000 {
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compatible = "ns16550a";
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reg = <0x200000 0x100000>;
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clocks = <&sysclk>;
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interrupts = <23>;
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reg-shift = <0>;
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fifo-size = <16>;
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reg-io-width = <1>;
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current-speed = <115200>;
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no-loopback-test;
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status = "disabled";
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resets = <&reset RESET_UART1>;
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};
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uart1: serial@300000 {
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compatible = "ns16550a";
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reg = <0x300000 0x100000>;
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clocks = <&sysclk>;
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interrupts = <24>;
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reg-shift = <0>;
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fifo-size = <16>;
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reg-io-width = <1>;
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current-speed = <115200>;
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no-loopback-test;
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status = "disabled";
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resets = <&reset RESET_UART2>;
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};
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uart2: serial@900000 {
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compatible = "ns16550a";
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reg = <0x900000 0x100000>;
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clocks = <&sysclk>;
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interrupts = <29>;
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reg-shift = <0>;
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fifo-size = <16>;
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reg-io-width = <1>;
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current-speed = <115200>;
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no-loopback-test;
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status = "disabled";
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resets = <&reset RESET_UART3>;
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};
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uart3: serial@a00000 {
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compatible = "ns16550a";
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reg = <0xa00000 0x100000>;
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clocks = <&sysclk>;
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interrupts = <30>;
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reg-shift = <0>;
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fifo-size = <16>;
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reg-io-width = <1>;
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current-speed = <115200>;
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no-loopback-test;
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status = "disabled";
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resets = <&reset RESET_UART4>;
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};
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};
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apb-bridge@45000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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ranges = <0 0x45000000 0x1000000>;
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sys: sys-ctrl@0 {
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compatible = "oxsemi,ox810se-sys-ctrl", "syscon", "simple-mfd";
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reg = <0x000000 0x100000>;
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reset: reset-controller {
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compatible = "oxsemi,ox810se-reset";
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#reset-cells = <1>;
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};
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stdclk: stdclk {
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compatible = "oxsemi,ox810se-stdclk";
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#clock-cells = <1>;
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};
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};
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rps@300000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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ranges = <0 0x300000 0x100000>;
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intc: interrupt-controller@0 {
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compatible = "oxsemi,ox810se-rps-irq";
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interrupt-controller;
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reg = <0 0x200>;
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#interrupt-cells = <1>;
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valid-mask = <0xffffffff>;
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clear-mask = <0xffffffff>;
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};
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timer0: timer@200 {
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compatible = "oxsemi,ox810se-rps-timer";
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reg = <0x200 0x40>;
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clocks = <&rpsclk>;
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interrupts = <4 5>;
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};
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};
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};
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};
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};
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@ -1,93 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* cloudengines-pogoplug-series-3.dtsi - Device tree file for Cloud Engines PogoPlug Series 3
|
||||
*
|
||||
* Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com>
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*/
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/dts-v1/;
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#include "ox820.dtsi"
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/ {
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model = "Cloud Engines PogoPlug Series 3";
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compatible = "cloudengines,pogoplugv3", "oxsemi,ox820";
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chosen {
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bootargs = "earlyprintk";
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stdout-path = "serial0:115200n8";
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};
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memory {
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/* 128Mbytes DDR */
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reg = <0x60000000 0x8000000>;
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};
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aliases {
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serial0 = &uart0;
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gpio0 = &gpio0;
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gpio1 = &gpio1;
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};
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leds {
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compatible = "gpio-leds";
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blue {
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label = "pogoplug:blue";
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gpios = <&gpio0 2 0>;
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default-state = "keep";
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};
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orange {
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label = "pogoplug:orange";
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gpios = <&gpio1 16 1>;
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default-state = "keep";
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};
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green {
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label = "pogoplug:green";
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gpios = <&gpio1 17 1>;
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default-state = "keep";
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};
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};
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};
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&uart0 {
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status = "okay";
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pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart0>;
|
||||
};
|
||||
|
||||
&nandc {
|
||||
status = "okay";
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_nand>;
|
||||
|
||||
nand@0 {
|
||||
reg = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
nand-ecc-mode = "soft";
|
||||
nand-ecc-algo = "hamming";
|
||||
|
||||
partition@0 {
|
||||
label = "boot";
|
||||
reg = <0x00000000 0x00e00000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@e00000 {
|
||||
label = "ubi";
|
||||
reg = <0x00e00000 0x07200000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ða {
|
||||
status = "okay";
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_etha_mdio>;
|
||||
};
|
||||
@ -1,299 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||
/*
|
||||
* ox820.dtsi - Device tree file for Oxford Semiconductor OX820 SoC
|
||||
*
|
||||
* Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com>
|
||||
*/
|
||||
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/clock/oxsemi,ox820.h>
|
||||
#include <dt-bindings/reset/oxsemi,ox820.h>
|
||||
|
||||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "oxsemi,ox820";
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
enable-method = "oxsemi,ox820-smp";
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,arm11mpcore";
|
||||
clocks = <&armclk>;
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,arm11mpcore";
|
||||
clocks = <&armclk>;
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
/* Max 512MB @ 0x60000000 */
|
||||
reg = <0x60000000 0x20000000>;
|
||||
};
|
||||
|
||||
clocks {
|
||||
osc: oscillator {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <25000000>;
|
||||
};
|
||||
|
||||
gmacclk: gmacclk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <125000000>;
|
||||
};
|
||||
|
||||
sysclk: sysclk {
|
||||
compatible = "fixed-factor-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-div = <4>;
|
||||
clock-mult = <1>;
|
||||
clocks = <&osc>;
|
||||
};
|
||||
|
||||
plla: plla {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <850000000>;
|
||||
};
|
||||
|
||||
armclk: armclk {
|
||||
compatible = "fixed-factor-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-div = <2>;
|
||||
clock-mult = <1>;
|
||||
clocks = <&plla>;
|
||||
};
|
||||
};
|
||||
|
||||
soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "simple-bus";
|
||||
ranges;
|
||||
interrupt-parent = <&gic>;
|
||||
|
||||
nandc: nand-controller@41000000 {
|
||||
compatible = "oxsemi,ox820-nand";
|
||||
reg = <0x41000000 0x100000>;
|
||||
clocks = <&stdclk CLK_820_NAND>;
|
||||
resets = <&reset RESET_NAND>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
etha: ethernet@40400000 {
|
||||
compatible = "oxsemi,ox820-dwmac", "snps,dwmac";
|
||||
reg = <0x40400000 0x2000>;
|
||||
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "macirq", "eth_wake_irq";
|
||||
mac-address = [000000000000]; /* Filled in by U-Boot */
|
||||
phy-mode = "rgmii";
|
||||
|
||||
clocks = <&stdclk CLK_820_ETHA>, <&gmacclk>;
|
||||
clock-names = "gmac", "stmmaceth";
|
||||
resets = <&reset RESET_MAC>;
|
||||
|
||||
/* Regmap for sys registers */
|
||||
oxsemi,sys-ctrl = <&sys>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
apb-bridge@44000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "simple-bus";
|
||||
ranges = <0 0x44000000 0x1000000>;
|
||||
|
||||
pinctrl: pinctrl {
|
||||
compatible = "oxsemi,ox820-pinctrl";
|
||||
|
||||
/* Regmap for sys registers */
|
||||
oxsemi,sys-ctrl = <&sys>;
|
||||
|
||||
pinctrl_uart0: uart0 {
|
||||
uart0 {
|
||||
pins = "gpio30", "gpio31";
|
||||
function = "fct5";
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_uart0_modem: uart0_modem {
|
||||
uart0_modem_a {
|
||||
pins = "gpio24", "gpio24", "gpio26", "gpio27";
|
||||
function = "fct4";
|
||||
};
|
||||
uart0_modem_b {
|
||||
pins = "gpio28", "gpio29";
|
||||
function = "fct5";
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_uart1: uart1 {
|
||||
uart1 {
|
||||
pins = "gpio7", "gpio8";
|
||||
function = "fct4";
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_uart1_modem: uart1_modem {
|
||||
uart1_modem {
|
||||
pins = "gpio5", "gpio6", "gpio40", "gpio41", "gpio42", "gpio43";
|
||||
function = "fct4";
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_etha_mdio: etha_mdio {
|
||||
etha_mdio {
|
||||
pins = "gpio3", "gpio4";
|
||||
function = "fct1";
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_nand: nand {
|
||||
nand {
|
||||
pins = "gpio12", "gpio13", "gpio14", "gpio15",
|
||||
"gpio16", "gpio17", "gpio18", "gpio19",
|
||||
"gpio20", "gpio21", "gpio22", "gpio23",
|
||||
"gpio24";
|
||||
function = "fct1";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
gpio0: gpio@0 {
|
||||
compatible = "oxsemi,ox820-gpio";
|
||||
reg = <0x000000 0x100000>;
|
||||
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
ngpios = <32>;
|
||||
oxsemi,gpio-bank = <0>;
|
||||
gpio-ranges = <&pinctrl 0 0 32>;
|
||||
};
|
||||
|
||||
gpio1: gpio@100000 {
|
||||
compatible = "oxsemi,ox820-gpio";
|
||||
reg = <0x100000 0x100000>;
|
||||
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
ngpios = <18>;
|
||||
oxsemi,gpio-bank = <1>;
|
||||
gpio-ranges = <&pinctrl 0 32 18>;
|
||||
};
|
||||
|
||||
uart0: serial@200000 {
|
||||
compatible = "ns16550a";
|
||||
reg = <0x200000 0x100000>;
|
||||
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <0>;
|
||||
fifo-size = <16>;
|
||||
reg-io-width = <1>;
|
||||
current-speed = <115200>;
|
||||
no-loopback-test;
|
||||
status = "disabled";
|
||||
clocks = <&sysclk>;
|
||||
resets = <&reset RESET_UART1>;
|
||||
};
|
||||
|
||||
uart1: serial@300000 {
|
||||
compatible = "ns16550a";
|
||||
reg = <0x200000 0x100000>;
|
||||
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <0>;
|
||||
fifo-size = <16>;
|
||||
reg-io-width = <1>;
|
||||
current-speed = <115200>;
|
||||
no-loopback-test;
|
||||
status = "disabled";
|
||||
clocks = <&sysclk>;
|
||||
resets = <&reset RESET_UART2>;
|
||||
};
|
||||
|
||||
rps@400000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "simple-bus";
|
||||
ranges = <0 0x400000 0x100000>;
|
||||
|
||||
intc: interrupt-controller@0 {
|
||||
compatible = "oxsemi,ox820-rps-irq", "oxsemi,ox810se-rps-irq";
|
||||
interrupt-controller;
|
||||
reg = <0 0x200>;
|
||||
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#interrupt-cells = <1>;
|
||||
valid-mask = <0xffffffff>;
|
||||
clear-mask = <0xffffffff>;
|
||||
};
|
||||
|
||||
timer0: timer@200 {
|
||||
compatible = "oxsemi,ox820-rps-timer";
|
||||
reg = <0x200 0x40>;
|
||||
clocks = <&sysclk>;
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <4>;
|
||||
};
|
||||
};
|
||||
|
||||
sys: sys-ctrl@e00000 {
|
||||
compatible = "oxsemi,ox820-sys-ctrl", "syscon", "simple-mfd";
|
||||
reg = <0xe00000 0x200000>;
|
||||
|
||||
reset: reset-controller {
|
||||
compatible = "oxsemi,ox820-reset", "oxsemi,ox810se-reset";
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
stdclk: stdclk {
|
||||
compatible = "oxsemi,ox820-stdclk", "oxsemi,ox810se-stdclk";
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
apb-bridge@47000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "simple-bus";
|
||||
ranges = <0 0x47000000 0x1000000>;
|
||||
|
||||
scu: scu@0 {
|
||||
compatible = "arm,arm11mp-scu";
|
||||
reg = <0x0 0x100>;
|
||||
};
|
||||
|
||||
local-timer@600 {
|
||||
compatible = "arm,arm11mp-twd-timer";
|
||||
reg = <0x600 0x20>;
|
||||
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3)|IRQ_TYPE_LEVEL_HIGH)>;
|
||||
clocks = <&armclk>;
|
||||
};
|
||||
|
||||
gic: interrupt-controller@1000 {
|
||||
compatible = "arm,arm11mp-gic";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
reg = <0x1000 0x1000>,
|
||||
<0x100 0x500>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
Loading…
x
Reference in New Issue
Block a user