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spi: cadence-quadspi: Provide a capability structure

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This controller has DTR support, so advertize it with a capability now
that the spi-controller structure contains this new field. This will
later be used by the core to discriminate whether an operation is
supported or not, in a more generic way than having different helpers.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Mark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/linux-mtd/20220127091808.1043392-4-miquel.raynal@bootlin.com
This commit is contained in:
Miquel Raynal 2022-01-27 10:17:58 +01:00
parent cb7e96ee81
commit a9be454927
1 changed files with 5 additions and 0 deletions
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5
drivers/spi/spi-cadence-quadspi.c
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@ -1595,6 +1595,10 @@ static const struct spi_controller_mem_ops cqspi_mem_ops = {
.supports_op = cqspi_supports_mem_op, .supports_op = cqspi_supports_mem_op,
}; };
static const struct spi_controller_mem_caps cqspi_mem_caps = {
.dtr = true,
};
static int cqspi_setup_flash(struct cqspi_st *cqspi) static int cqspi_setup_flash(struct cqspi_st *cqspi)
{ {
struct platform_device *pdev = cqspi->pdev; struct platform_device *pdev = cqspi->pdev;
@ -1652,6 +1656,7 @@ static int cqspi_probe(struct platform_device *pdev)
} }
master->mode_bits = SPI_RX_QUAD | SPI_RX_DUAL; master->mode_bits = SPI_RX_QUAD | SPI_RX_DUAL;
master->mem_ops = &cqspi_mem_ops; master->mem_ops = &cqspi_mem_ops;
master->mem_caps = &cqspi_mem_caps;
master->dev.of_node = pdev->dev.of_node; master->dev.of_node = pdev->dev.of_node;
cqspi = spi_master_get_devdata(master); cqspi = spi_master_get_devdata(master);