RDMA/mlx5: Order num_pending_prefetch properly with synchronize_srcu
During destroy setting live = 0 and then synchronize_srcu() prevents num_pending_prefetch from incrementing, and also, ensures that all work holding that count is queued on the WQ. Testing before causes races of the form: CPU0 CPU1 dereg_mr() mlx5_ib_advise_mr_prefetch() srcu_read_lock() num_pending_prefetch_inc() if (!live) live = 0 atomic_read() == 0 // skip flush_workqueue() atomic_inc() queue_work(); srcu_read_unlock() WARN_ON(atomic_read()) // Fails Swap the order so that the synchronize_srcu() prevents this. Fixes: a6bc3875f176 ("IB/mlx5: Protect against prefetch of invalid MR") Link: https://lore.kernel.org/r/20191001153821.23621-5-jgg@ziepe.ca Reviewed-by: Artemy Kovalyov <artemyko@mellanox.com> Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
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@ -1609,13 +1609,14 @@ static void dereg_mr(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr)
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*/
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mr->live = 0;
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/* Wait for all running page-fault handlers to finish. */
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synchronize_srcu(&dev->mr_srcu);
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/* dequeue pending prefetch requests for the mr */
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if (atomic_read(&mr->num_pending_prefetch))
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flush_workqueue(system_unbound_wq);
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WARN_ON(atomic_read(&mr->num_pending_prefetch));
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/* Wait for all running page-fault handlers to finish. */
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synchronize_srcu(&dev->mr_srcu);
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/* Destroy all page mappings */
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if (!umem_odp->is_implicit_odp)
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mlx5_ib_invalidate_range(umem_odp,
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