STM32 DT updates for v4.18, round 1
Highlights: ----------- -MCU platforms updates: -Update pwm-cells for stm32h743 -Add I2C support on stm32f7xx-disco boards and on stm32h743i-eval board -Add new stm32f469 dtsi file -Add display support on stm32f469-disco (LTDC/DSI) + pannel orisetech (otm8009a) -MPU STM32MP157 platform updates: -Fix DTC (W=12) warnings -Fix IRQ type definition for usart -Add QSPI & NOR flash support on EV1 board -Add CEC support -Add USB host -Add USBPHYC support and enable it on EV1 board -Add LTDC and DSI support -Add I2C support and enable it on ED1 and EV1 boards -Add CRC support -Add RNG support -Add CRYP support -Add DAC support -Add LPTIMER support -Add VREFBUFF support -Add timers supports and enable timer trigger 6 on ED1 board -Add MDMA, DMA and DMAMUX support and enable it -Enable clock driver -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJa7GCpAAoJEH+ayWryHnCFiiYP+wVXqprIgrS3N2qKWzrlsV5e f2HCYi2WKE4gtaU6yLsB5Bouxbk3I94t/G+lZJmkqvPkkG1cGZ4TWlNFiK0TwlrO 3pVcLpZFK//tNacvkjIMSHbI33AxPQ6+vf+KYkq775gNKgydB9avEeVlft/f0FKt 5LlBb4BH2SMoKKEZ4+3TbcXOW6H3C0hFiMo1vbIn0Sz9Cj6Rp/arMiubzXoK0YE5 rrxKEvWnf3hpyWmnernv7CSMf4TlNKEaNs/EXKu+Q1ydR/TjvF2q12uCNI37DvWK VL0OEPDirGSqvU2ZOh/Zi684cJi9Z2iqDKa1bA0c1vYrfryrDszyKTItvYgBpEzL HDxqfCOyj9fhLZXnmLS7WWliS0qwOsWAgzTFPNpekffFc16Xz2Zu7VsAXp3/UkmE wwQu/Spv7/r7S4tXfVgN6fzV6OROkeq4nOaOHAYzwEX9qFc7ksZ0hDh/It3JV1Mp fxx969O73OWCiCxP7n15hU6wPpZYjVgGbWFDbRY2Npgp/rU+G0O8P8kKJpnKddxI likVQsKhioTFSWuzks3DUrL84SSHlGZXeMdNmqJIPR9gBDOK7aZZD6ushck0KZ7n ndAQH2/pzZh12ikrcp435QRufF3+mLzBed8HF1b0/PmvZh0W+qqRe+BQmTCYFH2v NEW4yXqNhs2jMZ+JDW14 =V7P6 -----END PGP SIGNATURE----- Merge tag 'stm32-dt-for-v4.18-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into next/dt STM32 DT updates for v4.18, round 1 Highlights: ----------- -MCU platforms updates: -Update pwm-cells for stm32h743 -Add I2C support on stm32f7xx-disco boards and on stm32h743i-eval board -Add new stm32f469 dtsi file -Add display support on stm32f469-disco (LTDC/DSI) + pannel orisetech (otm8009a) -MPU STM32MP157 platform updates: -Fix DTC (W=12) warnings -Fix IRQ type definition for usart -Add QSPI & NOR flash support on EV1 board -Add CEC support -Add USB host -Add USBPHYC support and enable it on EV1 board -Add LTDC and DSI support -Add I2C support and enable it on ED1 and EV1 boards -Add CRC support -Add RNG support -Add CRYP support -Add DAC support -Add LPTIMER support -Add VREFBUFF support -Add timers supports and enable timer trigger 6 on ED1 board -Add MDMA, DMA and DMAMUX support and enable it -Enable clock driver * tag 'stm32-dt-for-v4.18-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32: (42 commits) ARM: dts: stm32: update pwm-cells for LPTimer on stm32h743 ARM: dts: stm32: Add I2C1 support for stm32h743i-eval Board ARM: dts: stm32: Add I2C support for STM32H743 SoC ARM: dts: stm32: Add I2C1 support for stm32f746-disco Board ARM: dts: stm32: Add I2C1 support for stm32f769-disco Board ARM: dts: stm32: Append additional I2Cs for STM32F746 SoC ARM: dts: stm32: Add display support on stm32f469-disco ARM: dts: stm32: Add new stm32f469 dtsi file with mipi dsi ARM: dts: stm32: Use gpio bindings in stm32f469-disco ARM: dts: stm32: Fix IRQ_TYPE_NONE warnings on stm32mp157c ARM: dts: stm32: Fix DTC warnings for stm32mp157 ARM: dts: stm32: add flash nor support on stm32mp157c eval board ARM: dts: stm32: add qspi support for stm32mp157c ARM: dts: stm32: add cec support on stm32mp157c-ev1 ARM: dts: stm32: add cec pins to stm32mp157c ARM: dts: stm32: add cec support on stm32mp157c ARM: dts: stm32: add USB Host (USBH) support to stm32mp157c ARM: dts: stm32: enable USBPHYC on stm32mp157c-ev1 ARM: dts: stm32: add supplies to usbphyc ports on stm32mp157c-ed1 ARM: dts: stm32: add USBPHYC support to stm32mp157c ... Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
aa264238ef
@ -46,7 +46,7 @@
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*/
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/dts-v1/;
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#include "stm32f429.dtsi"
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#include "stm32f469.dtsi"
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#include "stm32f469-pinctrl.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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@ -112,7 +112,7 @@
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vcc5v_otg: vcc5v-otg-regulator {
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compatible = "regulator-fixed";
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enable-active-high;
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gpio = <&gpiob 2 0>;
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gpio = <&gpiob 2 GPIO_ACTIVE_HIGH>;
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regulator-name = "vcc5_host1";
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regulator-always-on;
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};
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@ -126,6 +126,55 @@
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clock-frequency = <8000000>;
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};
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&dsi {
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#address-cells = <1>;
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#size-cells = <0>;
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status = "okay";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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dsi_in: endpoint {
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remote-endpoint = <<dc_out_dsi>;
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};
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};
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port@1 {
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reg = <1>;
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dsi_out: endpoint {
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remote-endpoint = <&dsi_panel_in>;
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};
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};
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};
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panel-dsi@0 {
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compatible = "orisetech,otm8009a";
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reg = <0>; /* dsi virtual channel (0..3) */
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reset-gpios = <&gpioh 7 GPIO_ACTIVE_LOW>;
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status = "okay";
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port {
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dsi_panel_in: endpoint {
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remote-endpoint = <&dsi_out>;
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};
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};
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};
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};
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<dc {
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dma-ranges;
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status = "okay";
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port {
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ltdc_out_dsi: endpoint@0 {
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remote-endpoint = <&dsi_in>;
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};
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};
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};
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&rtc {
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status = "okay";
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};
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19
arch/arm/boot/dts/stm32f469.dtsi
Normal file
19
arch/arm/boot/dts/stm32f469.dtsi
Normal file
@ -0,0 +1,19 @@
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/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
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/* Copyright (C) STMicroelectronics 2017 - All Rights Reserved */
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#include "stm32f429.dtsi"
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/ {
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soc {
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dsi: dsi@40016c00 {
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compatible = "st,stm32-dsi";
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reg = <0x40016c00 0x800>;
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interrupts = <92>;
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resets = <&rcc STM32F4_APB2_RESET(DSI)>;
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reset-names = "apb";
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clocks = <&rcc 1 CLK_F469_DSI>, <&clk_hse>;
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clock-names = "pclk", "ref";
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status = "disabled";
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};
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};
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};
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@ -90,6 +90,14 @@
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clock-frequency = <25000000>;
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};
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&i2c1 {
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pinctrl-0 = <&i2c1_pins_b>;
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pinctrl-names = "default";
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i2c-scl-rising-time-ns = <185>;
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i2c-scl-falling-time-ns = <20>;
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status = "okay";
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};
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&sdio1 {
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status = "okay";
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vmmc-supply = <&mmc_vcard>;
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@ -345,6 +345,42 @@
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status = "disabled";
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};
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i2c2: i2c@40005800 {
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compatible = "st,stm32f7-i2c";
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reg = <0x40005800 0x400>;
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interrupts = <33>,
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<34>;
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resets = <&rcc STM32F7_APB1_RESET(I2C2)>;
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clocks = <&rcc 1 CLK_I2C2>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c3: i2c@40005C00 {
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compatible = "st,stm32f7-i2c";
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reg = <0x40005C00 0x400>;
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interrupts = <72>,
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<73>;
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resets = <&rcc STM32F7_APB1_RESET(I2C3)>;
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clocks = <&rcc 1 CLK_I2C3>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c4: i2c@40006000 {
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compatible = "st,stm32f7-i2c";
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reg = <0x40006000 0x400>;
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interrupts = <95>,
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<96>;
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resets = <&rcc STM32F7_APB1_RESET(I2C4)>;
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clocks = <&rcc 1 CLK_I2C4>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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cec: cec@40006c00 {
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compatible = "st,stm32-cec";
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reg = <0x40006C00 0x400>;
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@ -111,6 +111,14 @@
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clock-frequency = <25000000>;
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};
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&i2c1 {
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pinctrl-0 = <&i2c1_pins_b>;
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pinctrl-names = "default";
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i2c-scl-rising-time-ns = <185>;
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i2c-scl-falling-time-ns = <20>;
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status = "okay";
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};
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&rtc {
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status = "okay";
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};
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@ -163,6 +163,16 @@
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#interrupt-cells = <2>;
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};
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i2c1_pins_a: i2c1@0 {
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pins {
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pinmux = <STM32_PINMUX('B', 6, AF4)>, /* I2C1_SCL */
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<STM32_PINMUX('B', 7, AF4)>; /* I2C1_SDA */
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bias-disable;
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drive-open-drain;
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slew-rate = <0>;
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};
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};
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usart1_pins: usart1@0 {
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pins1 {
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pinmux = <STM32_PINMUX('B', 14, AF4)>; /* USART1_TX */
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@ -86,6 +86,7 @@
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pwm {
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compatible = "st,stm32-pwm-lp";
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#pwm-cells = <3>;
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status = "disabled";
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};
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@ -130,6 +131,42 @@
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clocks = <&rcc USART2_CK>;
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};
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i2c1: i2c@40005400 {
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compatible = "st,stm32f7-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40005400 0x400>;
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interrupts = <31>,
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<32>;
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resets = <&rcc STM32H7_APB1L_RESET(I2C1)>;
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clocks = <&rcc I2C1_CK>;
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status = "disabled";
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};
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i2c2: i2c@40005800 {
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compatible = "st,stm32f7-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40005800 0x400>;
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interrupts = <33>,
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<34>;
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resets = <&rcc STM32H7_APB1L_RESET(I2C2)>;
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clocks = <&rcc I2C2_CK>;
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status = "disabled";
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};
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i2c3: i2c@40005C00 {
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compatible = "st,stm32f7-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40005C00 0x400>;
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interrupts = <72>,
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<73>;
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resets = <&rcc STM32H7_APB1L_RESET(I2C3)>;
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clocks = <&rcc I2C3_CK>;
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status = "disabled";
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};
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dac: dac@40007400 {
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compatible = "st,stm32h7-dac-core";
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reg = <0x40007400 0x400>;
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@ -323,6 +360,18 @@
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status = "disabled";
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};
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i2c4: i2c@58001C00 {
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compatible = "st,stm32f7-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x58001C00 0x400>;
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interrupts = <95>,
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<96>;
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resets = <&rcc STM32H7_APB4_RESET(I2C4)>;
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clocks = <&rcc I2C4_CK>;
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status = "disabled";
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};
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lptimer2: timer@58002400 {
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#address-cells = <1>;
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#size-cells = <0>;
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@ -334,6 +383,7 @@
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pwm {
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compatible = "st,stm32-pwm-lp";
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#pwm-cells = <3>;
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status = "disabled";
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};
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@ -360,6 +410,7 @@
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pwm {
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compatible = "st,stm32-pwm-lp";
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#pwm-cells = <3>;
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status = "disabled";
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};
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@ -381,6 +432,7 @@
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pwm {
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compatible = "st,stm32-pwm-lp";
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#pwm-cells = <3>;
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status = "disabled";
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};
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};
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@ -396,6 +448,7 @@
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pwm {
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compatible = "st,stm32-pwm-lp";
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#pwm-cells = <3>;
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status = "disabled";
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};
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};
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@ -92,6 +92,14 @@
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clock-frequency = <25000000>;
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};
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&i2c1 {
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pinctrl-0 = <&i2c1_pins_a>;
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pinctrl-names = "default";
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i2c-scl-rising-time-ns = <185>;
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i2c-scl-falling-time-ns = <20>;
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status = "okay";
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};
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&rtc {
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status = "okay";
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};
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@ -7,7 +7,7 @@
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/ {
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soc {
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pinctrl: pin-controller {
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pinctrl: pin-controller@50002000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "st,stm32mp157-pinctrl";
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@ -20,7 +20,7 @@
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x0 0x400>;
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clocks = <&clk_pll3_p>;
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clocks = <&rcc GPIOA>;
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st,bank-name = "GPIOA";
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ngpios = <16>;
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gpio-ranges = <&pinctrl 0 0 16>;
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@ -32,7 +32,7 @@
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x1000 0x400>;
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clocks = <&clk_pll3_p>;
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clocks = <&rcc GPIOB>;
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st,bank-name = "GPIOB";
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ngpios = <16>;
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gpio-ranges = <&pinctrl 0 16 16>;
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@ -44,7 +44,7 @@
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x2000 0x400>;
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clocks = <&clk_pll3_p>;
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clocks = <&rcc GPIOC>;
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st,bank-name = "GPIOC";
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ngpios = <16>;
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gpio-ranges = <&pinctrl 0 32 16>;
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@ -56,7 +56,7 @@
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x3000 0x400>;
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clocks = <&clk_pll3_p>;
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clocks = <&rcc GPIOD>;
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st,bank-name = "GPIOD";
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ngpios = <16>;
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gpio-ranges = <&pinctrl 0 48 16>;
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@ -68,7 +68,7 @@
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x4000 0x400>;
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clocks = <&clk_pll3_p>;
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clocks = <&rcc GPIOE>;
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st,bank-name = "GPIOE";
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ngpios = <16>;
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gpio-ranges = <&pinctrl 0 64 16>;
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@ -80,7 +80,7 @@
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x5000 0x400>;
|
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clocks = <&clk_pll3_p>;
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clocks = <&rcc GPIOF>;
|
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st,bank-name = "GPIOF";
|
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ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 80 16>;
|
||||
@ -92,7 +92,7 @@
|
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interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x6000 0x400>;
|
||||
clocks = <&clk_pll3_p>;
|
||||
clocks = <&rcc GPIOG>;
|
||||
st,bank-name = "GPIOG";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 96 16>;
|
||||
@ -104,7 +104,7 @@
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x7000 0x400>;
|
||||
clocks = <&clk_pll3_p>;
|
||||
clocks = <&rcc GPIOH>;
|
||||
st,bank-name = "GPIOH";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 112 16>;
|
||||
@ -116,7 +116,7 @@
|
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interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x8000 0x400>;
|
||||
clocks = <&clk_pll3_p>;
|
||||
clocks = <&rcc GPIOI>;
|
||||
st,bank-name = "GPIOI";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 128 16>;
|
||||
@ -128,7 +128,7 @@
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x9000 0x400>;
|
||||
clocks = <&clk_pll3_p>;
|
||||
clocks = <&rcc GPIOJ>;
|
||||
st,bank-name = "GPIOJ";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 144 16>;
|
||||
@ -140,13 +140,124 @@
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0xa000 0x400>;
|
||||
clocks = <&clk_pll3_p>;
|
||||
clocks = <&rcc GPIOK>;
|
||||
st,bank-name = "GPIOK";
|
||||
ngpios = <8>;
|
||||
gpio-ranges = <&pinctrl 0 160 8>;
|
||||
};
|
||||
|
||||
uart4_pins_a: uart4@0 {
|
||||
cec_pins_a: cec-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('A', 15, AF4)>;
|
||||
bias-disable;
|
||||
drive-open-drain;
|
||||
slew-rate = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c1_pins_a: i2c1-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('D', 12, AF5)>, /* I2C1_SCL */
|
||||
<STM32_PINMUX('F', 15, AF5)>; /* I2C1_SDA */
|
||||
bias-disable;
|
||||
drive-open-drain;
|
||||
slew-rate = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c2_pins_a: i2c2-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('H', 4, AF4)>, /* I2C2_SCL */
|
||||
<STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */
|
||||
bias-disable;
|
||||
drive-open-drain;
|
||||
slew-rate = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c5_pins_a: i2c5-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('A', 11, AF4)>, /* I2C5_SCL */
|
||||
<STM32_PINMUX('A', 12, AF4)>; /* I2C5_SDA */
|
||||
bias-disable;
|
||||
drive-open-drain;
|
||||
slew-rate = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
pwm2_pins_a: pwm2-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('A', 3, AF1)>; /* TIM2_CH4 */
|
||||
bias-pull-down;
|
||||
drive-push-pull;
|
||||
slew-rate = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
pwm8_pins_a: pwm8-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('I', 2, AF3)>; /* TIM8_CH4 */
|
||||
bias-pull-down;
|
||||
drive-push-pull;
|
||||
slew-rate = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
pwm12_pins_a: pwm12-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('H', 6, AF2)>; /* TIM12_CH1 */
|
||||
bias-pull-down;
|
||||
drive-push-pull;
|
||||
slew-rate = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
qspi_clk_pins_a: qspi-clk-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('F', 10, AF9)>; /* QSPI_CLK */
|
||||
bias-disable;
|
||||
drive-push-pull;
|
||||
slew-rate = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
qspi_bk1_pins_a: qspi-bk1-0 {
|
||||
pins1 {
|
||||
pinmux = <STM32_PINMUX('F', 8, AF10)>, /* QSPI_BK1_IO0 */
|
||||
<STM32_PINMUX('F', 9, AF10)>, /* QSPI_BK1_IO1 */
|
||||
<STM32_PINMUX('F', 7, AF9)>, /* QSPI_BK1_IO2 */
|
||||
<STM32_PINMUX('F', 6, AF9)>; /* QSPI_BK1_IO3 */
|
||||
bias-disable;
|
||||
drive-push-pull;
|
||||
slew-rate = <3>;
|
||||
};
|
||||
pins2 {
|
||||
pinmux = <STM32_PINMUX('B', 6, AF10)>; /* QSPI_BK1_NCS */
|
||||
bias-pull-up;
|
||||
drive-push-pull;
|
||||
slew-rate = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
qspi_bk2_pins_a: qspi-bk2-0 {
|
||||
pins1 {
|
||||
pinmux = <STM32_PINMUX('H', 2, AF9)>, /* QSPI_BK2_IO0 */
|
||||
<STM32_PINMUX('H', 3, AF9)>, /* QSPI_BK2_IO1 */
|
||||
<STM32_PINMUX('G', 10, AF11)>, /* QSPI_BK2_IO2 */
|
||||
<STM32_PINMUX('G', 7, AF11)>; /* QSPI_BK2_IO3 */
|
||||
bias-disable;
|
||||
drive-push-pull;
|
||||
slew-rate = <3>;
|
||||
};
|
||||
pins2 {
|
||||
pinmux = <STM32_PINMUX('C', 0, AF10)>; /* QSPI_BK2_NCS */
|
||||
bias-pull-up;
|
||||
drive-push-pull;
|
||||
slew-rate = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
uart4_pins_a: uart4-0 {
|
||||
pins1 {
|
||||
pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */
|
||||
bias-disable;
|
||||
@ -160,7 +271,7 @@
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_z: pin-controller-z {
|
||||
pinctrl_z: pin-controller-z@54004000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "st,stm32mp157-z-pinctrl";
|
||||
@ -174,12 +285,22 @@
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0 0x400>;
|
||||
clocks = <&clk_pll2_p>;
|
||||
clocks = <&rcc GPIOZ>;
|
||||
st,bank-name = "GPIOZ";
|
||||
st,bank-ioport = <11>;
|
||||
ngpios = <8>;
|
||||
gpio-ranges = <&pinctrl_z 0 400 8>;
|
||||
};
|
||||
|
||||
i2c4_pins_a: i2c4-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('Z', 4, AF6)>, /* I2C4_SCL */
|
||||
<STM32_PINMUX('Z', 5, AF6)>; /* I2C4_SDA */
|
||||
bias-disable;
|
||||
drive-open-drain;
|
||||
slew-rate = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@ -16,13 +16,56 @@
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory {
|
||||
memory@c0000000 {
|
||||
reg = <0xC0000000 0x40000000>;
|
||||
};
|
||||
|
||||
aliases {
|
||||
serial0 = &uart4;
|
||||
};
|
||||
|
||||
reg11: reg11 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "reg11";
|
||||
regulator-min-microvolt = <1100000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg18: reg18 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "reg18";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vdd_usb: vdd-usb {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vdd_usb";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
|
||||
&rng1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&timers6 {
|
||||
status = "okay";
|
||||
timer@5 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
&i2c4 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c4_pins_a>;
|
||||
i2c-scl-rising-time-ns = <185>;
|
||||
i2c-scl-falling-time-ns = <20>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart4 {
|
||||
@ -30,3 +73,15 @@
|
||||
pinctrl-0 = <&uart4_pins_a>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbphyc_port0 {
|
||||
phy-supply = <&vdd_usb>;
|
||||
vdda1v1-supply = <®11>;
|
||||
vdda1v8-supply = <®18>;
|
||||
};
|
||||
|
||||
&usbphyc_port1 {
|
||||
phy-supply = <&vdd_usb>;
|
||||
vdda1v1-supply = <®11>;
|
||||
vdda1v8-supply = <®18>;
|
||||
};
|
||||
|
||||
@ -19,3 +19,90 @@
|
||||
serial0 = &uart4;
|
||||
};
|
||||
};
|
||||
|
||||
&cec {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cec_pins_a>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c2_pins_a>;
|
||||
i2c-scl-rising-time-ns = <185>;
|
||||
i2c-scl-falling-time-ns = <20>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c5 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c5_pins_a>;
|
||||
i2c-scl-rising-time-ns = <185>;
|
||||
i2c-scl-falling-time-ns = <20>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&qspi {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a &qspi_bk2_pins_a>;
|
||||
reg = <0x58003000 0x1000>, <0x70000000 0x4000000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "okay";
|
||||
|
||||
flash0: mx66l51235l@0 {
|
||||
reg = <0>;
|
||||
spi-rx-bus-width = <4>;
|
||||
spi-max-frequency = <108000000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
};
|
||||
|
||||
flash1: mx66l51235l@1 {
|
||||
reg = <1>;
|
||||
spi-rx-bus-width = <4>;
|
||||
spi-max-frequency = <108000000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
&timers2 {
|
||||
status = "disabled";
|
||||
pwm {
|
||||
pinctrl-0 = <&pwm2_pins_a>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
timer@1 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
&timers8 {
|
||||
status = "disabled";
|
||||
pwm {
|
||||
pinctrl-0 = <&pwm8_pins_a>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
timer@7 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
&timers12 {
|
||||
status = "disabled";
|
||||
pwm {
|
||||
pinctrl-0 = <&pwm12_pins_a>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
timer@11 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
&usbphyc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
@ -4,6 +4,8 @@
|
||||
* Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
|
||||
*/
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/clock/stm32mp1-clks.h>
|
||||
#include <dt-bindings/reset/stm32mp1-resets.h>
|
||||
|
||||
/ {
|
||||
#address-cells = <1>;
|
||||
@ -71,12 +73,6 @@
|
||||
clock-frequency = <24000000>;
|
||||
};
|
||||
|
||||
clk_pll_per: clk-pll-per {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <64000000>;
|
||||
};
|
||||
|
||||
clk_hsi: clk-hsi {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
@ -100,24 +96,6 @@
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <4000000>;
|
||||
};
|
||||
|
||||
clk_pclk1: clk-pclk1 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <86000000>;
|
||||
};
|
||||
|
||||
clk_pll3_p: clk-pll3_p {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <172000000>;
|
||||
};
|
||||
|
||||
clk_pll2_p: clk-pll2_p {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <264000000>;
|
||||
};
|
||||
};
|
||||
|
||||
soc {
|
||||
@ -127,67 +105,729 @@
|
||||
interrupt-parent = <&intc>;
|
||||
ranges;
|
||||
|
||||
timers2: timer@40000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40000000 0x400>;
|
||||
clocks = <&rcc TIM2_K>;
|
||||
clock-names = "int";
|
||||
status = "disabled";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
timer@1 {
|
||||
compatible = "st,stm32h7-timer-trigger";
|
||||
reg = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
timers3: timer@40001000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40001000 0x400>;
|
||||
clocks = <&rcc TIM3_K>;
|
||||
clock-names = "int";
|
||||
status = "disabled";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
timer@2 {
|
||||
compatible = "st,stm32h7-timer-trigger";
|
||||
reg = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
timers4: timer@40002000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40002000 0x400>;
|
||||
clocks = <&rcc TIM4_K>;
|
||||
clock-names = "int";
|
||||
status = "disabled";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
timer@3 {
|
||||
compatible = "st,stm32h7-timer-trigger";
|
||||
reg = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
timers5: timer@40003000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40003000 0x400>;
|
||||
clocks = <&rcc TIM5_K>;
|
||||
clock-names = "int";
|
||||
status = "disabled";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
timer@4 {
|
||||
compatible = "st,stm32h7-timer-trigger";
|
||||
reg = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
timers6: timer@40004000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40004000 0x400>;
|
||||
clocks = <&rcc TIM6_K>;
|
||||
clock-names = "int";
|
||||
status = "disabled";
|
||||
|
||||
timer@5 {
|
||||
compatible = "st,stm32h7-timer-trigger";
|
||||
reg = <5>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
timers7: timer@40005000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40005000 0x400>;
|
||||
clocks = <&rcc TIM7_K>;
|
||||
clock-names = "int";
|
||||
status = "disabled";
|
||||
|
||||
timer@6 {
|
||||
compatible = "st,stm32h7-timer-trigger";
|
||||
reg = <6>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
timers12: timer@40006000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40006000 0x400>;
|
||||
clocks = <&rcc TIM12_K>;
|
||||
clock-names = "int";
|
||||
status = "disabled";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
timer@11 {
|
||||
compatible = "st,stm32h7-timer-trigger";
|
||||
reg = <11>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
timers13: timer@40007000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40007000 0x400>;
|
||||
clocks = <&rcc TIM13_K>;
|
||||
clock-names = "int";
|
||||
status = "disabled";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
timer@12 {
|
||||
compatible = "st,stm32h7-timer-trigger";
|
||||
reg = <12>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
timers14: timer@40008000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40008000 0x400>;
|
||||
clocks = <&rcc TIM14_K>;
|
||||
clock-names = "int";
|
||||
status = "disabled";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
timer@13 {
|
||||
compatible = "st,stm32h7-timer-trigger";
|
||||
reg = <13>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
lptimer1: timer@40009000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "st,stm32-lptimer";
|
||||
reg = <0x40009000 0x400>;
|
||||
clocks = <&rcc LPTIM1_K>;
|
||||
clock-names = "mux";
|
||||
status = "disabled";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm-lp";
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
trigger@0 {
|
||||
compatible = "st,stm32-lptimer-trigger";
|
||||
reg = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
counter {
|
||||
compatible = "st,stm32-lptimer-counter";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
usart2: serial@4000e000 {
|
||||
compatible = "st,stm32h7-uart";
|
||||
reg = <0x4000e000 0x400>;
|
||||
interrupts = <GIC_SPI 38 IRQ_TYPE_NONE>;
|
||||
clocks = <&clk_pclk1>;
|
||||
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&rcc USART2_K>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usart3: serial@4000f000 {
|
||||
compatible = "st,stm32h7-uart";
|
||||
reg = <0x4000f000 0x400>;
|
||||
interrupts = <GIC_SPI 39 IRQ_TYPE_NONE>;
|
||||
clocks = <&clk_pclk1>;
|
||||
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&rcc USART3_K>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart4: serial@40010000 {
|
||||
compatible = "st,stm32h7-uart";
|
||||
reg = <0x40010000 0x400>;
|
||||
interrupts = <GIC_SPI 52 IRQ_TYPE_NONE>;
|
||||
clocks = <&clk_pclk1>;
|
||||
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&rcc UART4_K>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart5: serial@40011000 {
|
||||
compatible = "st,stm32h7-uart";
|
||||
reg = <0x40011000 0x400>;
|
||||
interrupts = <GIC_SPI 53 IRQ_TYPE_NONE>;
|
||||
clocks = <&clk_pclk1>;
|
||||
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&rcc UART5_K>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c1: i2c@40012000 {
|
||||
compatible = "st,stm32f7-i2c";
|
||||
reg = <0x40012000 0x400>;
|
||||
interrupt-names = "event", "error";
|
||||
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&rcc I2C1_K>;
|
||||
resets = <&rcc I2C1_R>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c2: i2c@40013000 {
|
||||
compatible = "st,stm32f7-i2c";
|
||||
reg = <0x40013000 0x400>;
|
||||
interrupt-names = "event", "error";
|
||||
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&rcc I2C2_K>;
|
||||
resets = <&rcc I2C2_R>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c3: i2c@40014000 {
|
||||
compatible = "st,stm32f7-i2c";
|
||||
reg = <0x40014000 0x400>;
|
||||
interrupt-names = "event", "error";
|
||||
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&rcc I2C3_K>;
|
||||
resets = <&rcc I2C3_R>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c5: i2c@40015000 {
|
||||
compatible = "st,stm32f7-i2c";
|
||||
reg = <0x40015000 0x400>;
|
||||
interrupt-names = "event", "error";
|
||||
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&rcc I2C5_K>;
|
||||
resets = <&rcc I2C5_R>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
cec: cec@40016000 {
|
||||
compatible = "st,stm32-cec";
|
||||
reg = <0x40016000 0x400>;
|
||||
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&rcc CEC_K>, <&clk_lse>;
|
||||
clock-names = "cec", "hdmi-cec";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
dac: dac@40017000 {
|
||||
compatible = "st,stm32h7-dac-core";
|
||||
reg = <0x40017000 0x400>;
|
||||
clocks = <&rcc DAC12>;
|
||||
clock-names = "pclk";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
|
||||
dac1: dac@1 {
|
||||
compatible = "st,stm32-dac";
|
||||
#io-channels-cells = <1>;
|
||||
reg = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
dac2: dac@2 {
|
||||
compatible = "st,stm32-dac";
|
||||
#io-channels-cells = <1>;
|
||||
reg = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
uart7: serial@40018000 {
|
||||
compatible = "st,stm32h7-uart";
|
||||
reg = <0x40018000 0x400>;
|
||||
interrupts = <GIC_SPI 82 IRQ_TYPE_NONE>;
|
||||
clocks = <&clk_pclk1>;
|
||||
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&rcc UART7_K>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart8: serial@40019000 {
|
||||
compatible = "st,stm32h7-uart";
|
||||
reg = <0x40019000 0x400>;
|
||||
interrupts = <GIC_SPI 83 IRQ_TYPE_NONE>;
|
||||
clocks = <&clk_pclk1>;
|
||||
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&rcc UART8_K>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
timers1: timer@44000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x44000000 0x400>;
|
||||
clocks = <&rcc TIM1_K>;
|
||||
clock-names = "int";
|
||||
status = "disabled";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
timer@0 {
|
||||
compatible = "st,stm32h7-timer-trigger";
|
||||
reg = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
timers8: timer@44001000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x44001000 0x400>;
|
||||
clocks = <&rcc TIM8_K>;
|
||||
clock-names = "int";
|
||||
status = "disabled";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
timer@7 {
|
||||
compatible = "st,stm32h7-timer-trigger";
|
||||
reg = <7>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
usart6: serial@44003000 {
|
||||
compatible = "st,stm32h7-uart";
|
||||
reg = <0x44003000 0x400>;
|
||||
interrupts = <GIC_SPI 71 IRQ_TYPE_NONE>;
|
||||
clocks = <&clk_pclk1>;
|
||||
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&rcc USART6_K>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
timers15: timer@44006000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x44006000 0x400>;
|
||||
clocks = <&rcc TIM15_K>;
|
||||
clock-names = "int";
|
||||
status = "disabled";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
timer@14 {
|
||||
compatible = "st,stm32h7-timer-trigger";
|
||||
reg = <14>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
timers16: timer@44007000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x44007000 0x400>;
|
||||
clocks = <&rcc TIM16_K>;
|
||||
clock-names = "int";
|
||||
status = "disabled";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm";
|
||||
status = "disabled";
|
||||
};
|
||||
timer@15 {
|
||||
compatible = "st,stm32h7-timer-trigger";
|
||||
reg = <15>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
timers17: timer@44008000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x44008000 0x400>;
|
||||
clocks = <&rcc TIM17_K>;
|
||||
clock-names = "int";
|
||||
status = "disabled";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
timer@16 {
|
||||
compatible = "st,stm32h7-timer-trigger";
|
||||
reg = <16>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
dma1: dma@48000000 {
|
||||
compatible = "st,stm32-dma";
|
||||
reg = <0x48000000 0x400>;
|
||||
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&rcc DMA1>;
|
||||
#dma-cells = <4>;
|
||||
st,mem2mem;
|
||||
dma-requests = <8>;
|
||||
};
|
||||
|
||||
dma2: dma@48001000 {
|
||||
compatible = "st,stm32-dma";
|
||||
reg = <0x48001000 0x400>;
|
||||
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&rcc DMA2>;
|
||||
#dma-cells = <4>;
|
||||
st,mem2mem;
|
||||
dma-requests = <8>;
|
||||
};
|
||||
|
||||
dmamux1: dma-router@48002000 {
|
||||
compatible = "st,stm32h7-dmamux";
|
||||
reg = <0x48002000 0x1c>;
|
||||
#dma-cells = <3>;
|
||||
dma-requests = <128>;
|
||||
dma-masters = <&dma1 &dma2>;
|
||||
dma-channels = <16>;
|
||||
clocks = <&rcc DMAMUX>;
|
||||
};
|
||||
|
||||
rcc: rcc@50000000 {
|
||||
compatible = "st,stm32mp1-rcc", "syscon";
|
||||
reg = <0x50000000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
lptimer2: timer@50021000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "st,stm32-lptimer";
|
||||
reg = <0x50021000 0x400>;
|
||||
clocks = <&rcc LPTIM2_K>;
|
||||
clock-names = "mux";
|
||||
status = "disabled";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm-lp";
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
trigger@1 {
|
||||
compatible = "st,stm32-lptimer-trigger";
|
||||
reg = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
counter {
|
||||
compatible = "st,stm32-lptimer-counter";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
lptimer3: timer@50022000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "st,stm32-lptimer";
|
||||
reg = <0x50022000 0x400>;
|
||||
clocks = <&rcc LPTIM3_K>;
|
||||
clock-names = "mux";
|
||||
status = "disabled";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm-lp";
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
trigger@2 {
|
||||
compatible = "st,stm32-lptimer-trigger";
|
||||
reg = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
lptimer4: timer@50023000 {
|
||||
compatible = "st,stm32-lptimer";
|
||||
reg = <0x50023000 0x400>;
|
||||
clocks = <&rcc LPTIM4_K>;
|
||||
clock-names = "mux";
|
||||
status = "disabled";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm-lp";
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
lptimer5: timer@50024000 {
|
||||
compatible = "st,stm32-lptimer";
|
||||
reg = <0x50024000 0x400>;
|
||||
clocks = <&rcc LPTIM5_K>;
|
||||
clock-names = "mux";
|
||||
status = "disabled";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm-lp";
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
vrefbuf: vrefbuf@50025000 {
|
||||
compatible = "st,stm32-vrefbuf";
|
||||
reg = <0x50025000 0x8>;
|
||||
regulator-min-microvolt = <1500000>;
|
||||
regulator-max-microvolt = <2500000>;
|
||||
clocks = <&rcc VREF>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
cryp1: cryp@54001000 {
|
||||
compatible = "st,stm32mp1-cryp";
|
||||
reg = <0x54001000 0x400>;
|
||||
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&rcc CRYP1>;
|
||||
resets = <&rcc CRYP1_R>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
rng1: rng@54003000 {
|
||||
compatible = "st,stm32-rng";
|
||||
reg = <0x54003000 0x400>;
|
||||
clocks = <&rcc RNG1_K>;
|
||||
resets = <&rcc RNG1_R>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mdma1: dma@58000000 {
|
||||
compatible = "st,stm32h7-mdma";
|
||||
reg = <0x58000000 0x1000>;
|
||||
interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&rcc MDMA>;
|
||||
#dma-cells = <5>;
|
||||
dma-channels = <32>;
|
||||
dma-requests = <48>;
|
||||
};
|
||||
|
||||
qspi: qspi@58003000 {
|
||||
compatible = "st,stm32f469-qspi";
|
||||
reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
|
||||
reg-names = "qspi", "qspi_mm";
|
||||
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&rcc QSPI_K>;
|
||||
resets = <&rcc QSPI_R>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
crc1: crc@58009000 {
|
||||
compatible = "st,stm32f7-crc";
|
||||
reg = <0x58009000 0x400>;
|
||||
clocks = <&rcc CRC1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usbh_ohci: usbh-ohci@5800c000 {
|
||||
compatible = "generic-ohci";
|
||||
reg = <0x5800c000 0x1000>;
|
||||
clocks = <&rcc USBH>;
|
||||
resets = <&rcc USBH_R>;
|
||||
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usbh_ehci: usbh-ehci@5800d000 {
|
||||
compatible = "generic-ehci";
|
||||
reg = <0x5800d000 0x1000>;
|
||||
clocks = <&rcc USBH>;
|
||||
resets = <&rcc USBH_R>;
|
||||
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
|
||||
companion = <&usbh_ohci>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
dsi: dsi@5a000000 {
|
||||
compatible = "st,stm32-dsi";
|
||||
reg = <0x5a000000 0x800>;
|
||||
clocks = <&rcc DSI_K>, <&clk_hse>, <&rcc DSI_PX>;
|
||||
clock-names = "pclk", "ref", "px_clk";
|
||||
resets = <&rcc DSI_R>;
|
||||
reset-names = "apb";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ltdc: display-controller@5a001000 {
|
||||
compatible = "st,stm32-ltdc";
|
||||
reg = <0x5a001000 0x400>;
|
||||
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&rcc LTDC_PX>;
|
||||
clock-names = "lcd";
|
||||
resets = <&rcc LTDC_R>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usbphyc: usbphyc@5a006000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "st,stm32mp1-usbphyc";
|
||||
reg = <0x5a006000 0x1000>;
|
||||
clocks = <&rcc USBPHY_K>;
|
||||
resets = <&rcc USBPHY_R>;
|
||||
status = "disabled";
|
||||
|
||||
usbphyc_port0: usb-phy@0 {
|
||||
#phy-cells = <0>;
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
usbphyc_port1: usb-phy@1 {
|
||||
#phy-cells = <1>;
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
usart1: serial@5c000000 {
|
||||
compatible = "st,stm32h7-uart";
|
||||
reg = <0x5c000000 0x400>;
|
||||
interrupts = <GIC_SPI 37 IRQ_TYPE_NONE>;
|
||||
clocks = <&clk_pclk1>;
|
||||
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&rcc USART1_K>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c4: i2c@5c002000 {
|
||||
compatible = "st,stm32f7-i2c";
|
||||
reg = <0x5c002000 0x400>;
|
||||
interrupt-names = "event", "error";
|
||||
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&rcc I2C4_K>;
|
||||
resets = <&rcc I2C4_R>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c6: i2c@5c009000 {
|
||||
compatible = "st,stm32f7-i2c";
|
||||
reg = <0x5c009000 0x400>;
|
||||
interrupt-names = "event", "error";
|
||||
interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&rcc I2C6_K>;
|
||||
resets = <&rcc I2C6_R>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user