[MTD] [NAND] GPIO NAND flash driver
The patch adds support for NAND flashes connected to GPIOs. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Mike Rapoport <mike@compulab.co.il> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
This commit is contained in:
Mike Rapoport
David Woodhouse
parent
a0ee24a03b
commit
aaf7ea2000
@ -56,6 +56,12 @@ config MTD_NAND_H1900
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help
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This enables the driver for the iPAQ h1900 flash.
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config MTD_NAND_GPIO
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tristate "GPIO NAND Flash driver"
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depends on GENERIC_GPIO
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help
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This enables a GPIO based NAND flash driver.
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config MTD_NAND_SPIA
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tristate "NAND Flash device on SPIA board"
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depends on ARCH_P720T
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@ -23,6 +23,7 @@ obj-$(CONFIG_MTD_NAND_NANDSIM) += nandsim.o
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obj-$(CONFIG_MTD_NAND_CS553X) += cs553x_nand.o
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obj-$(CONFIG_MTD_NAND_NDFC) += ndfc.o
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obj-$(CONFIG_MTD_NAND_ATMEL) += atmel_nand.o
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obj-$(CONFIG_MTD_NAND_GPIO) += gpio.o
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obj-$(CONFIG_MTD_NAND_CM_X270) += cmx270_nand.o
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obj-$(CONFIG_MTD_NAND_BASLER_EXCITE) += excite_nandflash.o
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obj-$(CONFIG_MTD_NAND_PXA3xx) += pxa3xx_nand.o
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375
drivers/mtd/nand/gpio.c
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375
drivers/mtd/nand/gpio.c
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@ -0,0 +1,375 @@
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/*
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* drivers/mtd/nand/gpio.c
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*
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* Updated, and converted to generic GPIO based driver by Russell King.
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*
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* Written by Ben Dooks <ben@simtec.co.uk>
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* Based on 2.4 version by Mark Whittaker
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*
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* © 2004 Simtec Electronics
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*
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* Device driver for NAND connected via GPIO
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/slab.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/gpio.h>
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#include <linux/io.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/nand.h>
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#include <linux/mtd/partitions.h>
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#include <linux/mtd/nand-gpio.h>
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struct gpiomtd {
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void __iomem *io_sync;
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struct mtd_info mtd_info;
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struct nand_chip nand_chip;
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struct gpio_nand_platdata plat;
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};
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#define gpio_nand_getpriv(x) container_of(x, struct gpiomtd, mtd_info)
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#ifdef CONFIG_ARM
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/* gpio_nand_dosync()
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*
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* Make sure the GPIO state changes occur in-order with writes to NAND
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* memory region.
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* Needed on PXA due to bus-reordering within the SoC itself (see section on
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* I/O ordering in PXA manual (section 2.3, p35)
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*/
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static void gpio_nand_dosync(struct gpiomtd *gpiomtd)
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{
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unsigned long tmp;
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if (gpiomtd->io_sync) {
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/*
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* Linux memory barriers don't cater for what's required here.
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* What's required is what's here - a read from a separate
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* region with a dependency on that read.
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*/
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tmp = readl(gpiomtd->io_sync);
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asm volatile("mov %1, %0\n" : "=r" (tmp) : "r" (tmp));
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}
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}
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#else
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static inline void gpio_nand_dosync(struct gpiomtd *gpiomtd) {}
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#endif
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static void gpio_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
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{
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struct gpiomtd *gpiomtd = gpio_nand_getpriv(mtd);
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gpio_nand_dosync(gpiomtd);
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if (ctrl & NAND_CTRL_CHANGE) {
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gpio_set_value(gpiomtd->plat.gpio_nce, !(ctrl & NAND_NCE));
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gpio_set_value(gpiomtd->plat.gpio_cle, !!(ctrl & NAND_CLE));
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gpio_set_value(gpiomtd->plat.gpio_ale, !!(ctrl & NAND_ALE));
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gpio_nand_dosync(gpiomtd);
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}
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if (cmd == NAND_CMD_NONE)
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return;
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writeb(cmd, gpiomtd->nand_chip.IO_ADDR_W);
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gpio_nand_dosync(gpiomtd);
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}
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static void gpio_nand_writebuf(struct mtd_info *mtd, const u_char *buf, int len)
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{
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struct nand_chip *this = mtd->priv;
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writesb(this->IO_ADDR_W, buf, len);
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}
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static void gpio_nand_readbuf(struct mtd_info *mtd, u_char *buf, int len)
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{
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struct nand_chip *this = mtd->priv;
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readsb(this->IO_ADDR_R, buf, len);
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}
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static int gpio_nand_verifybuf(struct mtd_info *mtd, const u_char *buf, int len)
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{
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struct nand_chip *this = mtd->priv;
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unsigned char read, *p = (unsigned char *) buf;
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int i, err = 0;
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for (i = 0; i < len; i++) {
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read = readb(this->IO_ADDR_R);
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if (read != p[i]) {
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pr_debug("%s: err at %d (read %04x vs %04x)\n",
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__func__, i, read, p[i]);
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err = -EFAULT;
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}
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}
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return err;
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}
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static void gpio_nand_writebuf16(struct mtd_info *mtd, const u_char *buf,
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int len)
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{
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struct nand_chip *this = mtd->priv;
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if (IS_ALIGNED((unsigned long)buf, 2)) {
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writesw(this->IO_ADDR_W, buf, len>>1);
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} else {
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int i;
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unsigned short *ptr = (unsigned short *)buf;
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for (i = 0; i < len; i += 2, ptr++)
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writew(*ptr, this->IO_ADDR_W);
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}
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}
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static void gpio_nand_readbuf16(struct mtd_info *mtd, u_char *buf, int len)
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{
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struct nand_chip *this = mtd->priv;
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if (IS_ALIGNED((unsigned long)buf, 2)) {
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readsw(this->IO_ADDR_R, buf, len>>1);
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} else {
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int i;
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unsigned short *ptr = (unsigned short *)buf;
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for (i = 0; i < len; i += 2, ptr++)
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*ptr = readw(this->IO_ADDR_R);
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}
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}
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static int gpio_nand_verifybuf16(struct mtd_info *mtd, const u_char *buf,
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int len)
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{
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struct nand_chip *this = mtd->priv;
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unsigned short read, *p = (unsigned short *) buf;
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int i, err = 0;
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len >>= 1;
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for (i = 0; i < len; i++) {
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read = readw(this->IO_ADDR_R);
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if (read != p[i]) {
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pr_debug("%s: err at %d (read %04x vs %04x)\n",
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__func__, i, read, p[i]);
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err = -EFAULT;
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}
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}
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return err;
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}
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static int gpio_nand_devready(struct mtd_info *mtd)
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{
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struct gpiomtd *gpiomtd = gpio_nand_getpriv(mtd);
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return gpio_get_value(gpiomtd->plat.gpio_rdy);
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}
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static int __devexit gpio_nand_remove(struct platform_device *dev)
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{
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struct gpiomtd *gpiomtd = platform_get_drvdata(dev);
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struct resource *res;
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nand_release(&gpiomtd->mtd_info);
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res = platform_get_resource(dev, IORESOURCE_MEM, 1);
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iounmap(gpiomtd->io_sync);
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if (res)
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release_mem_region(res->start, res->end - res->start + 1);
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res = platform_get_resource(dev, IORESOURCE_MEM, 0);
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iounmap(gpiomtd->nand_chip.IO_ADDR_R);
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release_mem_region(res->start, res->end - res->start + 1);
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if (gpio_is_valid(gpiomtd->plat.gpio_nwp))
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gpio_set_value(gpiomtd->plat.gpio_nwp, 0);
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gpio_set_value(gpiomtd->plat.gpio_nce, 1);
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gpio_free(gpiomtd->plat.gpio_cle);
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gpio_free(gpiomtd->plat.gpio_ale);
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gpio_free(gpiomtd->plat.gpio_nce);
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if (gpio_is_valid(gpiomtd->plat.gpio_nwp))
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gpio_free(gpiomtd->plat.gpio_nwp);
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gpio_free(gpiomtd->plat.gpio_rdy);
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kfree(gpiomtd);
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return 0;
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}
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static void __iomem *request_and_remap(struct resource *res, size_t size,
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const char *name, int *err)
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{
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void __iomem *ptr;
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if (!request_mem_region(res->start, res->end - res->start + 1, name)) {
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*err = -EBUSY;
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return NULL;
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}
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ptr = ioremap(res->start, size);
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if (!ptr) {
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release_mem_region(res->start, res->end - res->start + 1);
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*err = -ENOMEM;
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}
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return ptr;
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}
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static int __devinit gpio_nand_probe(struct platform_device *dev)
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{
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struct gpiomtd *gpiomtd;
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struct nand_chip *this;
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struct resource *res0, *res1;
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int ret;
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if (!dev->dev.platform_data)
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return -EINVAL;
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res0 = platform_get_resource(dev, IORESOURCE_MEM, 0);
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if (!res0)
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return -EINVAL;
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gpiomtd = kzalloc(sizeof(*gpiomtd), GFP_KERNEL);
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if (gpiomtd == NULL) {
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dev_err(&dev->dev, "failed to create NAND MTD\n");
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return -ENOMEM;
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}
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this = &gpiomtd->nand_chip;
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this->IO_ADDR_R = request_and_remap(res0, 2, "NAND", &ret);
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if (!this->IO_ADDR_R) {
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dev_err(&dev->dev, "unable to map NAND\n");
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goto err_map;
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}
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res1 = platform_get_resource(dev, IORESOURCE_MEM, 1);
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if (res1) {
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gpiomtd->io_sync = request_and_remap(res1, 4, "NAND sync", &ret);
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if (!gpiomtd->io_sync) {
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dev_err(&dev->dev, "unable to map sync NAND\n");
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goto err_sync;
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}
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}
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memcpy(&gpiomtd->plat, dev->dev.platform_data, sizeof(gpiomtd->plat));
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ret = gpio_request(gpiomtd->plat.gpio_nce, "NAND NCE");
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if (ret)
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goto err_nce;
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gpio_direction_output(gpiomtd->plat.gpio_nce, 1);
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if (gpio_is_valid(gpiomtd->plat.gpio_nwp)) {
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ret = gpio_request(gpiomtd->plat.gpio_nwp, "NAND NWP");
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if (ret)
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goto err_nwp;
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gpio_direction_output(gpiomtd->plat.gpio_nwp, 1);
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}
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ret = gpio_request(gpiomtd->plat.gpio_ale, "NAND ALE");
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if (ret)
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goto err_ale;
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gpio_direction_output(gpiomtd->plat.gpio_ale, 0);
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ret = gpio_request(gpiomtd->plat.gpio_cle, "NAND CLE");
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if (ret)
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goto err_cle;
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gpio_direction_output(gpiomtd->plat.gpio_cle, 0);
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ret = gpio_request(gpiomtd->plat.gpio_rdy, "NAND RDY");
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if (ret)
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goto err_rdy;
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gpio_direction_input(gpiomtd->plat.gpio_rdy);
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this->IO_ADDR_W = this->IO_ADDR_R;
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this->ecc.mode = NAND_ECC_SOFT;
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this->options = gpiomtd->plat.options;
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this->chip_delay = gpiomtd->plat.chip_delay;
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/* install our routines */
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this->cmd_ctrl = gpio_nand_cmd_ctrl;
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this->dev_ready = gpio_nand_devready;
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if (this->options & NAND_BUSWIDTH_16) {
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this->read_buf = gpio_nand_readbuf16;
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this->write_buf = gpio_nand_writebuf16;
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this->verify_buf = gpio_nand_verifybuf16;
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} else {
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this->read_buf = gpio_nand_readbuf;
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this->write_buf = gpio_nand_writebuf;
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this->verify_buf = gpio_nand_verifybuf;
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}
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/* set the mtd private data for the nand driver */
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gpiomtd->mtd_info.priv = this;
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gpiomtd->mtd_info.owner = THIS_MODULE;
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if (nand_scan(&gpiomtd->mtd_info, 1)) {
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dev_err(&dev->dev, "no nand chips found?\n");
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ret = -ENXIO;
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goto err_wp;
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}
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if (gpiomtd->plat.adjust_parts)
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gpiomtd->plat.adjust_parts(&gpiomtd->plat,
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gpiomtd->mtd_info.size);
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add_mtd_partitions(&gpiomtd->mtd_info, gpiomtd->plat.parts,
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gpiomtd->plat.num_parts);
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platform_set_drvdata(dev, gpiomtd);
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return 0;
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err_wp:
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if (gpio_is_valid(gpiomtd->plat.gpio_nwp))
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gpio_set_value(gpiomtd->plat.gpio_nwp, 0);
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gpio_free(gpiomtd->plat.gpio_rdy);
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err_rdy:
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gpio_free(gpiomtd->plat.gpio_cle);
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err_cle:
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gpio_free(gpiomtd->plat.gpio_ale);
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err_ale:
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if (gpio_is_valid(gpiomtd->plat.gpio_nwp))
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gpio_free(gpiomtd->plat.gpio_nwp);
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err_nwp:
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gpio_free(gpiomtd->plat.gpio_nce);
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err_nce:
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iounmap(gpiomtd->io_sync);
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if (res1)
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release_mem_region(res1->start, res1->end - res1->start + 1);
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err_sync:
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iounmap(gpiomtd->nand_chip.IO_ADDR_R);
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release_mem_region(res0->start, res0->end - res0->start + 1);
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err_map:
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kfree(gpiomtd);
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return ret;
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}
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static struct platform_driver gpio_nand_driver = {
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.probe = gpio_nand_probe,
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.remove = gpio_nand_remove,
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.driver = {
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.name = "gpio-nand",
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},
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};
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static int __init gpio_nand_init(void)
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{
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printk(KERN_INFO "GPIO NAND driver, © 2004 Simtec Electronics\n");
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return platform_driver_register(&gpio_nand_driver);
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}
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static void __exit gpio_nand_exit(void)
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{
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platform_driver_unregister(&gpio_nand_driver);
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}
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module_init(gpio_nand_init);
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module_exit(gpio_nand_exit);
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MODULE_LICENSE("GPL");
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MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
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MODULE_DESCRIPTION("GPIO NAND Driver");
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19
include/linux/mtd/nand-gpio.h
Normal file
19
include/linux/mtd/nand-gpio.h
Normal file
@ -0,0 +1,19 @@
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#ifndef __LINUX_MTD_NAND_GPIO_H
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#define __LINUX_MTD_NAND_GPIO_H
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#include <linux/mtd/nand.h>
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struct gpio_nand_platdata {
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int gpio_nce;
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int gpio_nwp;
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int gpio_cle;
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int gpio_ale;
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int gpio_rdy;
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void (*adjust_parts)(struct gpio_nand_platdata *, size_t);
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struct mtd_partition *parts;
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unsigned int num_parts;
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unsigned int options;
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int chip_delay;
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};
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#endif
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