spi: Fixes for v6.11
The bulk of this is a series of fixes for the microchip-core driver mostly originating from one of their customers, I also applied an additional patch adding support for controlling the word size which came along with it since it's still the merge window and clearly had a bunch of fairly thorough testing. We also have a fix for the compatible used to bind spidev to the BH2228FV. -----BEGIN PGP SIGNATURE----- iQEzBAABCgAdFiEEreZoqmdXGLWf4p/qJNaLcl1Uh9AFAmajpbAACgkQJNaLcl1U h9BK3gf6A/EoyfNTbY7eqnGtghg6PXqBzWHkfHtdqxMNvlf2YBYPu0Zj4i/1Tqde 3UcDCZnKdYBIH3GX0wzRlTa/OUZmfZ6i5oyUAfqRCYFj8w9AydTLrfm6d9MizgWf ZrRcBLRxMqUvlADH4odWqXBo8+Eyx2A2n98bVhIEDPieJDaRtlUz1oym5AKmInP+ AuiF43N8HSoumv/zmwMZWit9TugUnyqGeeKiUBoW5SDDsvCUGy/2hCkyoJDGZDCg NpEllllMNz1Weggt3e3q52mEV9bfjoyefRg/z9/TEIEyuYFWCqZ1ilbrKKaVVXF8 JKicvFtVDErk5iVx7a5090JXcgh15Q== =CfDJ -----END PGP SIGNATURE----- Merge tag 'spi-fix-v6.11-merge-window' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi Pull spi fixes from Mark Brown: "The bulk of this is a series of fixes for the microchip-core driver mostly originating from one of their customers, I also applied an additional patch adding support for controlling the word size which came along with it since it's still the merge window and clearly had a bunch of fairly thorough testing. We also have a fix for the compatible used to bind spidev to the BH2228FV" * tag 'spi-fix-v6.11-merge-window' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: spi: spidev: add correct compatible for Rohm BH2228FV dt-bindings: trivial-devices: fix Rohm BH2228FV compatible string spi: microchip-core: add support for word sizes of 1 to 32 bits spi: microchip-core: ensure TX and RX FIFOs are empty at start of a transfer spi: microchip-core: fix init function not setting the master and motorola modes spi: microchip-core: only disable SPI controller when register value change requires it spi: microchip-core: defer asserting chip select until just before write to TX FIFO spi: microchip-core: fix the issues in the isr
This commit is contained in:
Linus Torvalds
commit
ab11658f26
@ -328,7 +328,9 @@ properties:
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- renesas,hs3001
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# Renesas ISL29501 time-of-flight sensor
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- renesas,isl29501
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# Rohm DH2228FV
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# Rohm BH2228FV 8 channel DAC
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- rohm,bh2228fv
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# Rohm DH2228FV - This device does not exist, use rohm,bh2228fv instead.
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- rohm,dh2228fv
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# S524AD0XF1 (128K/256K-bit Serial EEPROM for Low Power)
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- samsung,24ad0xd1
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@ -75,6 +75,7 @@
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#define REG_CONTROL (0x00)
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#define REG_FRAME_SIZE (0x04)
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#define FRAME_SIZE_MASK GENMASK(5, 0)
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#define REG_STATUS (0x08)
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#define REG_INT_CLEAR (0x0c)
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#define REG_RX_DATA (0x10)
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@ -89,6 +90,9 @@
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#define REG_RIS (0x24)
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#define REG_CONTROL2 (0x28)
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#define REG_COMMAND (0x2c)
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#define COMMAND_CLRFRAMECNT BIT(4)
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#define COMMAND_TXFIFORST BIT(3)
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#define COMMAND_RXFIFORST BIT(2)
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#define REG_PKTSIZE (0x30)
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#define REG_CMD_SIZE (0x34)
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#define REG_HWSTATUS (0x38)
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@ -103,10 +107,11 @@ struct mchp_corespi {
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u8 *rx_buf;
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u32 clk_gen; /* divider for spi output clock generated by the controller */
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u32 clk_mode;
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u32 pending_slave_select;
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int irq;
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int tx_len;
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int rx_len;
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int pending;
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int n_bytes;
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};
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static inline u32 mchp_corespi_read(struct mchp_corespi *spi, unsigned int reg)
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@ -130,113 +135,126 @@ static inline void mchp_corespi_disable(struct mchp_corespi *spi)
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static inline void mchp_corespi_read_fifo(struct mchp_corespi *spi)
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{
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u8 data;
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int fifo_max, i = 0;
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while (spi->rx_len >= spi->n_bytes && !(mchp_corespi_read(spi, REG_STATUS) & STATUS_RXFIFO_EMPTY)) {
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u32 data = mchp_corespi_read(spi, REG_RX_DATA);
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fifo_max = min(spi->rx_len, FIFO_DEPTH);
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spi->rx_len -= spi->n_bytes;
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while ((i < fifo_max) && !(mchp_corespi_read(spi, REG_STATUS) & STATUS_RXFIFO_EMPTY)) {
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data = mchp_corespi_read(spi, REG_RX_DATA);
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if (!spi->rx_buf)
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continue;
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if (spi->rx_buf)
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*spi->rx_buf++ = data;
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i++;
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if (spi->n_bytes == 4)
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*((u32 *)spi->rx_buf) = data;
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else if (spi->n_bytes == 2)
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*((u16 *)spi->rx_buf) = data;
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else
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*spi->rx_buf = data;
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spi->rx_buf += spi->n_bytes;
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}
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spi->rx_len -= i;
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spi->pending -= i;
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}
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static void mchp_corespi_enable_ints(struct mchp_corespi *spi)
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{
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u32 control, mask = INT_ENABLE_MASK;
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u32 control = mchp_corespi_read(spi, REG_CONTROL);
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mchp_corespi_disable(spi);
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control = mchp_corespi_read(spi, REG_CONTROL);
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control |= mask;
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mchp_corespi_write(spi, REG_CONTROL, control);
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control |= CONTROL_ENABLE;
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control |= INT_ENABLE_MASK;
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mchp_corespi_write(spi, REG_CONTROL, control);
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}
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static void mchp_corespi_disable_ints(struct mchp_corespi *spi)
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{
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u32 control, mask = INT_ENABLE_MASK;
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u32 control = mchp_corespi_read(spi, REG_CONTROL);
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mchp_corespi_disable(spi);
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control = mchp_corespi_read(spi, REG_CONTROL);
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control &= ~mask;
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mchp_corespi_write(spi, REG_CONTROL, control);
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control |= CONTROL_ENABLE;
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control &= ~INT_ENABLE_MASK;
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mchp_corespi_write(spi, REG_CONTROL, control);
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}
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static inline void mchp_corespi_set_xfer_size(struct mchp_corespi *spi, int len)
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{
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u32 control;
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u16 lenpart;
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u32 lenpart;
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u32 frames = mchp_corespi_read(spi, REG_FRAMESUP);
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/*
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* Disable the SPI controller. Writes to transfer length have
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* no effect when the controller is enabled.
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* Writing to FRAMECNT in REG_CONTROL will reset the frame count, taking
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* a shortcut requires an explicit clear.
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*/
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mchp_corespi_disable(spi);
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if (frames == len) {
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mchp_corespi_write(spi, REG_COMMAND, COMMAND_CLRFRAMECNT);
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return;
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}
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/*
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* The lower 16 bits of the frame count are stored in the control reg
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* for legacy reasons, but the upper 16 written to a different register:
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* FRAMESUP. While both the upper and lower bits can be *READ* from the
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* FRAMESUP register, writing to the lower 16 bits is a NOP
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* FRAMESUP register, writing to the lower 16 bits is (supposedly) a NOP.
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*
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* The driver used to disable the controller while modifying the frame
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* count, and mask off the lower 16 bits of len while writing to
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* FRAMES_UP. When the driver was changed to disable the controller as
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* infrequently as possible, it was discovered that the logic of
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* lenpart = len & 0xffff_0000
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* write(REG_FRAMESUP, lenpart)
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* would actually write zeros into the lower 16 bits on an mpfs250t-es,
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* despite documentation stating these bits were read-only.
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* Writing len unmasked into FRAMES_UP ensures those bits aren't zeroed
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* on an mpfs250t-es and will be a NOP for the lower 16 bits on hardware
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* that matches the documentation.
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*/
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lenpart = len & 0xffff;
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control = mchp_corespi_read(spi, REG_CONTROL);
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control &= ~CONTROL_FRAMECNT_MASK;
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control |= lenpart << CONTROL_FRAMECNT_SHIFT;
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mchp_corespi_write(spi, REG_CONTROL, control);
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lenpart = len & 0xffff0000;
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mchp_corespi_write(spi, REG_FRAMESUP, lenpart);
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control |= CONTROL_ENABLE;
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mchp_corespi_write(spi, REG_CONTROL, control);
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mchp_corespi_write(spi, REG_FRAMESUP, len);
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}
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static inline void mchp_corespi_write_fifo(struct mchp_corespi *spi)
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{
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u8 byte;
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int fifo_max, i = 0;
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fifo_max = min(spi->tx_len, FIFO_DEPTH);
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fifo_max = DIV_ROUND_UP(min(spi->tx_len, FIFO_DEPTH), spi->n_bytes);
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mchp_corespi_set_xfer_size(spi, fifo_max);
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while ((i < fifo_max) && !(mchp_corespi_read(spi, REG_STATUS) & STATUS_TXFIFO_FULL)) {
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byte = spi->tx_buf ? *spi->tx_buf++ : 0xaa;
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mchp_corespi_write(spi, REG_TX_DATA, byte);
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u32 word;
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if (spi->n_bytes == 4)
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word = spi->tx_buf ? *((u32 *)spi->tx_buf) : 0xaa;
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else if (spi->n_bytes == 2)
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word = spi->tx_buf ? *((u16 *)spi->tx_buf) : 0xaa;
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else
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word = spi->tx_buf ? *spi->tx_buf : 0xaa;
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mchp_corespi_write(spi, REG_TX_DATA, word);
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if (spi->tx_buf)
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spi->tx_buf += spi->n_bytes;
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i++;
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}
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spi->tx_len -= i;
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spi->pending += i;
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spi->tx_len -= i * spi->n_bytes;
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}
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static inline void mchp_corespi_set_framesize(struct mchp_corespi *spi, int bt)
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{
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u32 frame_size = mchp_corespi_read(spi, REG_FRAME_SIZE);
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u32 control;
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if ((frame_size & FRAME_SIZE_MASK) == bt)
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return;
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/*
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* Disable the SPI controller. Writes to the frame size have
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* no effect when the controller is enabled.
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*/
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mchp_corespi_disable(spi);
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control = mchp_corespi_read(spi, REG_CONTROL);
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control &= ~CONTROL_ENABLE;
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mchp_corespi_write(spi, REG_CONTROL, control);
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mchp_corespi_write(spi, REG_FRAME_SIZE, bt);
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control = mchp_corespi_read(spi, REG_CONTROL);
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control |= CONTROL_ENABLE;
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mchp_corespi_write(spi, REG_CONTROL, control);
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}
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@ -249,7 +267,17 @@ static void mchp_corespi_set_cs(struct spi_device *spi, bool disable)
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reg = mchp_corespi_read(corespi, REG_SLAVE_SELECT);
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reg &= ~BIT(spi_get_chipselect(spi, 0));
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reg |= !disable << spi_get_chipselect(spi, 0);
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corespi->pending_slave_select = reg;
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/*
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* Only deassert chip select immediately. Writing to some registers
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* requires the controller to be disabled, which results in the
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* output pins being tristated and can cause the SCLK and MOSI lines
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* to transition. Therefore asserting the chip select is deferred
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* until just before writing to the TX FIFO, to ensure the device
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* doesn't see any spurious clock transitions whilst CS is enabled.
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*/
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if (((spi->mode & SPI_CS_HIGH) == 0) == disable)
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mchp_corespi_write(corespi, REG_SLAVE_SELECT, reg);
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}
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@ -269,6 +297,7 @@ static int mchp_corespi_setup(struct spi_device *spi)
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if (spi->mode & SPI_CS_HIGH) {
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reg = mchp_corespi_read(corespi, REG_SLAVE_SELECT);
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reg |= BIT(spi_get_chipselect(spi, 0));
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corespi->pending_slave_select = reg;
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mchp_corespi_write(corespi, REG_SLAVE_SELECT, reg);
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}
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return 0;
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@ -279,17 +308,13 @@ static void mchp_corespi_init(struct spi_controller *host, struct mchp_corespi *
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unsigned long clk_hz;
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u32 control = mchp_corespi_read(spi, REG_CONTROL);
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control |= CONTROL_MASTER;
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control &= ~CONTROL_ENABLE;
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mchp_corespi_write(spi, REG_CONTROL, control);
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control |= CONTROL_MASTER;
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control &= ~CONTROL_MODE_MASK;
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control |= MOTOROLA_MODE;
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mchp_corespi_set_framesize(spi, DEFAULT_FRAMESIZE);
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/* max. possible spi clock rate is the apb clock rate */
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clk_hz = clk_get_rate(spi->clk);
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host->max_speed_hz = clk_hz;
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/*
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* The controller must be configured so that it doesn't remove Chip
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* Select until the entire message has been transferred, even if at
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@ -298,11 +323,16 @@ static void mchp_corespi_init(struct spi_controller *host, struct mchp_corespi *
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* BIGFIFO mode is also enabled, which sets the fifo depth to 32 frames
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* for the 8 bit transfers that this driver uses.
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*/
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control = mchp_corespi_read(spi, REG_CONTROL);
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control |= CONTROL_SPS | CONTROL_BIGFIFO;
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mchp_corespi_write(spi, REG_CONTROL, control);
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mchp_corespi_set_framesize(spi, DEFAULT_FRAMESIZE);
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/* max. possible spi clock rate is the apb clock rate */
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clk_hz = clk_get_rate(spi->clk);
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host->max_speed_hz = clk_hz;
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mchp_corespi_enable_ints(spi);
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/*
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@ -310,7 +340,8 @@ static void mchp_corespi_init(struct spi_controller *host, struct mchp_corespi *
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* select is relinquished to the hardware. SSELOUT is enabled too so we
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* can deal with active high targets.
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*/
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mchp_corespi_write(spi, REG_SLAVE_SELECT, SSELOUT | SSEL_DIRECT);
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spi->pending_slave_select = SSELOUT | SSEL_DIRECT;
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mchp_corespi_write(spi, REG_SLAVE_SELECT, spi->pending_slave_select);
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control = mchp_corespi_read(spi, REG_CONTROL);
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@ -324,8 +355,6 @@ static inline void mchp_corespi_set_clk_gen(struct mchp_corespi *spi)
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{
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u32 control;
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mchp_corespi_disable(spi);
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control = mchp_corespi_read(spi, REG_CONTROL);
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if (spi->clk_mode)
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control |= CONTROL_CLKMODE;
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@ -334,12 +363,12 @@ static inline void mchp_corespi_set_clk_gen(struct mchp_corespi *spi)
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mchp_corespi_write(spi, REG_CLK_GEN, spi->clk_gen);
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mchp_corespi_write(spi, REG_CONTROL, control);
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mchp_corespi_write(spi, REG_CONTROL, control | CONTROL_ENABLE);
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}
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static inline void mchp_corespi_set_mode(struct mchp_corespi *spi, unsigned int mode)
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{
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u32 control, mode_val;
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u32 mode_val;
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u32 control = mchp_corespi_read(spi, REG_CONTROL);
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switch (mode & SPI_MODE_X_MASK) {
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case SPI_MODE_0:
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@ -357,12 +386,13 @@ static inline void mchp_corespi_set_mode(struct mchp_corespi *spi, unsigned int
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}
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/*
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* Disable the SPI controller. Writes to the frame size have
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* Disable the SPI controller. Writes to the frame protocol have
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* no effect when the controller is enabled.
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*/
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mchp_corespi_disable(spi);
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control = mchp_corespi_read(spi, REG_CONTROL);
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control &= ~CONTROL_ENABLE;
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mchp_corespi_write(spi, REG_CONTROL, control);
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control &= ~(SPI_MODE_X_MASK << MODE_X_MASK_SHIFT);
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control |= mode_val;
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@ -383,21 +413,18 @@ static irqreturn_t mchp_corespi_interrupt(int irq, void *dev_id)
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if (intfield == 0)
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return IRQ_NONE;
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if (intfield & INT_TXDONE) {
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if (intfield & INT_TXDONE)
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mchp_corespi_write(spi, REG_INT_CLEAR, INT_TXDONE);
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if (intfield & INT_RXRDY) {
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mchp_corespi_write(spi, REG_INT_CLEAR, INT_RXRDY);
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if (spi->rx_len)
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mchp_corespi_read_fifo(spi);
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if (spi->tx_len)
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mchp_corespi_write_fifo(spi);
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if (!spi->rx_len)
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finalise = true;
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}
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if (intfield & INT_RXRDY)
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mchp_corespi_write(spi, REG_INT_CLEAR, INT_RXRDY);
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if (!spi->rx_len && !spi->tx_len)
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finalise = true;
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if (intfield & INT_RX_CHANNEL_OVERFLOW) {
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mchp_corespi_write(spi, REG_INT_CLEAR, INT_RX_CHANNEL_OVERFLOW);
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@ -477,13 +504,17 @@ static int mchp_corespi_transfer_one(struct spi_controller *host,
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spi->rx_buf = xfer->rx_buf;
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spi->tx_len = xfer->len;
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spi->rx_len = xfer->len;
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spi->pending = 0;
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spi->n_bytes = roundup_pow_of_two(DIV_ROUND_UP(xfer->bits_per_word, BITS_PER_BYTE));
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mchp_corespi_set_xfer_size(spi, (spi->tx_len > FIFO_DEPTH)
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? FIFO_DEPTH : spi->tx_len);
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mchp_corespi_set_framesize(spi, xfer->bits_per_word);
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if (spi->tx_len)
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mchp_corespi_write(spi, REG_COMMAND, COMMAND_RXFIFORST | COMMAND_TXFIFORST);
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mchp_corespi_write(spi, REG_SLAVE_SELECT, spi->pending_slave_select);
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while (spi->tx_len)
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mchp_corespi_write_fifo(spi);
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return 1;
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}
|
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|
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@ -493,7 +524,6 @@ static int mchp_corespi_prepare_message(struct spi_controller *host,
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struct spi_device *spi_dev = msg->spi;
|
||||
struct mchp_corespi *spi = spi_controller_get_devdata(host);
|
||||
|
||||
mchp_corespi_set_framesize(spi, DEFAULT_FRAMESIZE);
|
||||
mchp_corespi_set_mode(spi, spi_dev->mode);
|
||||
|
||||
return 0;
|
||||
@ -521,7 +551,7 @@ static int mchp_corespi_probe(struct platform_device *pdev)
|
||||
host->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
|
||||
host->use_gpio_descriptors = true;
|
||||
host->setup = mchp_corespi_setup;
|
||||
host->bits_per_word_mask = SPI_BPW_MASK(8);
|
||||
host->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32);
|
||||
host->transfer_one = mchp_corespi_transfer_one;
|
||||
host->prepare_message = mchp_corespi_prepare_message;
|
||||
host->set_cs = mchp_corespi_set_cs;
|
||||
|
||||
@ -734,6 +734,7 @@ static const struct of_device_id spidev_dt_ids[] = {
|
||||
{ .compatible = "lwn,bk4", .data = &spidev_of_check },
|
||||
{ .compatible = "menlo,m53cpld", .data = &spidev_of_check },
|
||||
{ .compatible = "micron,spi-authenta", .data = &spidev_of_check },
|
||||
{ .compatible = "rohm,bh2228fv", .data = &spidev_of_check },
|
||||
{ .compatible = "rohm,dh2228fv", .data = &spidev_of_check },
|
||||
{ .compatible = "semtech,sx1301", .data = &spidev_of_check },
|
||||
{ .compatible = "silabs,em3581", .data = &spidev_of_check },
|
||||
|
||||
Loading…
Reference in New Issue
Block a user