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alx: add a simple AR816x/AR817x device driver

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This is a very simple driver, based on the original vendor
driver that Qualcomm/Atheros published/submitted previously,
but reworked to make the code saner. However, it also lost
a number of features (TSO/GSO, VLAN acceleration and multi-
queue support) in the process, as well as debugging support
features I didn't have any use for. The only thing I left
is checksum offload.

More features can obviously be added, but this seemed like
a good start for having a driver in mainline at all.

Johannes Stezenbach has verified that the driver works on
AR8161, I have a AR8171 myself. The E2200 device ID I found
on github in somebody's repository.

Signed-off-by: Johannes Berg <johannes@sipsolutions.net>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Johannes Berg 2013-06-17 22:44:02 +02:00 committed by David S. Miller
parent 93725cbd22
commit ab69bde6b2
9 changed files with 4568 additions and 0 deletions
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18
drivers/net/ethernet/atheros/Kconfig
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@ -67,4 +67,22 @@ config ATL1C
To compile this driver as a module, choose M here. The module
will be called atl1c.
config ALX
tristate "Qualcomm Atheros AR816x/AR817x support"
depends on PCI
select CRC32
select NET_CORE
select MDIO
help
This driver supports the Qualcomm Atheros L1F ethernet adapter,
i.e. the following chipsets:
1969:1091 - AR8161 Gigabit Ethernet
1969:1090 - AR8162 Fast Ethernet
1969:10A1 - AR8171 Gigabit Ethernet
1969:10A0 - AR8172 Fast Ethernet
To compile this driver as a module, choose M here. The module
will be called alx.
endif # NET_VENDOR_ATHEROS

1
drivers/net/ethernet/atheros/Makefile
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@ -6,3 +6,4 @@ obj-$(CONFIG_ATL1) += atlx/
obj-$(CONFIG_ATL2) += atlx/
obj-$(CONFIG_ATL1E) += atl1e/
obj-$(CONFIG_ATL1C) += atl1c/
obj-$(CONFIG_ALX) += alx/

3
drivers/net/ethernet/atheros/alx/Makefile Normal file
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@ -0,0 +1,3 @@
obj-$(CONFIG_ALX) += alx.o
alx-objs := main.o ethtool.o hw.o
ccflags-y += -D__CHECK_ENDIAN__

114
drivers/net/ethernet/atheros/alx/alx.h Normal file
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@ -0,0 +1,114 @@
/*
* Copyright (c) 2013 Johannes Berg <johannes@sipsolutions.net>
*
* This file is free software: you may copy, redistribute and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation, either version 2 of the License, or (at your
* option) any later version.
*
* This file is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
* This file incorporates work covered by the following copyright and
* permission notice:
*
* Copyright (c) 2012 Qualcomm Atheros, Inc.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _ALX_H_
#define _ALX_H_
#include <linux/types.h>
#include <linux/etherdevice.h>
#include <linux/dma-mapping.h>
#include <linux/spinlock.h>
#include "hw.h"
#define ALX_WATCHDOG_TIME (5 * HZ)
struct alx_buffer {
struct sk_buff *skb;
DEFINE_DMA_UNMAP_ADDR(dma);
DEFINE_DMA_UNMAP_LEN(size);
};
struct alx_rx_queue {
struct alx_rrd *rrd;
dma_addr_t rrd_dma;
struct alx_rfd *rfd;
dma_addr_t rfd_dma;
struct alx_buffer *bufs;
u16 write_idx, read_idx;
u16 rrd_read_idx;
};
#define ALX_RX_ALLOC_THRESH 32
struct alx_tx_queue {
struct alx_txd *tpd;
dma_addr_t tpd_dma;
struct alx_buffer *bufs;
u16 write_idx, read_idx;
};
#define ALX_DEFAULT_TX_WORK 128
enum alx_device_quirks {
ALX_DEV_QUIRK_MSI_INTX_DISABLE_BUG = BIT(0),
};
struct alx_priv {
struct net_device *dev;
struct alx_hw hw;
/* all descriptor memory */
struct {
dma_addr_t dma;
void *virt;
int size;
} descmem;
/* protect int_mask updates */
spinlock_t irq_lock;
u32 int_mask;
int tx_ringsz;
int rx_ringsz;
int rxbuf_size;
struct napi_struct napi;
struct alx_tx_queue txq;
struct alx_rx_queue rxq;
struct work_struct link_check_wk;
struct work_struct reset_wk;
u16 msg_enable;
bool msi;
};
extern const struct ethtool_ops alx_ethtool_ops;
extern const char alx_drv_name[];
#endif

272
drivers/net/ethernet/atheros/alx/ethtool.c Normal file
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@ -0,0 +1,272 @@
/*
* Copyright (c) 2013 Johannes Berg <johannes@sipsolutions.net>
*
* This file is free software: you may copy, redistribute and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation, either version 2 of the License, or (at your
* option) any later version.
*
* This file is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
* This file incorporates work covered by the following copyright and
* permission notice:
*
* Copyright (c) 2012 Qualcomm Atheros, Inc.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#include <linux/pci.h>
#include <linux/ip.h>
#include <linux/tcp.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/ethtool.h>
#include <linux/mdio.h>
#include <linux/interrupt.h>
#include <asm/byteorder.h>
#include "alx.h"
#include "reg.h"
#include "hw.h"
static int alx_get_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
{
struct alx_priv *alx = netdev_priv(netdev);
struct alx_hw *hw = &alx->hw;
ecmd->supported = SUPPORTED_10baseT_Half |
SUPPORTED_10baseT_Full |
SUPPORTED_100baseT_Half |
SUPPORTED_100baseT_Full |
SUPPORTED_Autoneg |
SUPPORTED_TP |
SUPPORTED_Pause;
if (alx_hw_giga(hw))
ecmd->supported |= SUPPORTED_1000baseT_Full;
ecmd->advertising = ADVERTISED_TP;
if (hw->adv_cfg & ADVERTISED_Autoneg)
ecmd->advertising |= hw->adv_cfg;
ecmd->port = PORT_TP;
ecmd->phy_address = 0;
if (hw->adv_cfg & ADVERTISED_Autoneg)
ecmd->autoneg = AUTONEG_ENABLE;
else
ecmd->autoneg = AUTONEG_DISABLE;
ecmd->transceiver = XCVR_INTERNAL;
if (hw->flowctrl & ALX_FC_ANEG && hw->adv_cfg & ADVERTISED_Autoneg) {
if (hw->flowctrl & ALX_FC_RX) {
ecmd->advertising |= ADVERTISED_Pause;
if (!(hw->flowctrl & ALX_FC_TX))
ecmd->advertising |= ADVERTISED_Asym_Pause;
} else if (hw->flowctrl & ALX_FC_TX) {
ecmd->advertising |= ADVERTISED_Asym_Pause;
}
}
if (hw->link_speed != SPEED_UNKNOWN) {
ethtool_cmd_speed_set(ecmd,
hw->link_speed - hw->link_speed % 10);
ecmd->duplex = hw->link_speed % 10;
} else {
ethtool_cmd_speed_set(ecmd, SPEED_UNKNOWN);
ecmd->duplex = DUPLEX_UNKNOWN;
}
return 0;
}
static int alx_set_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
{
struct alx_priv *alx = netdev_priv(netdev);
struct alx_hw *hw = &alx->hw;
u32 adv_cfg;
ASSERT_RTNL();
if (ecmd->autoneg == AUTONEG_ENABLE) {
if (ecmd->advertising & ADVERTISED_1000baseT_Half)
return -EINVAL;
adv_cfg = ecmd->advertising | ADVERTISED_Autoneg;
} else {
int speed = ethtool_cmd_speed(ecmd);
switch (speed + ecmd->duplex) {
case SPEED_10 + DUPLEX_HALF:
adv_cfg = ADVERTISED_10baseT_Half;
break;
case SPEED_10 + DUPLEX_FULL:
adv_cfg = ADVERTISED_10baseT_Full;
break;
case SPEED_100 + DUPLEX_HALF:
adv_cfg = ADVERTISED_100baseT_Half;
break;
case SPEED_100 + DUPLEX_FULL:
adv_cfg = ADVERTISED_100baseT_Full;
break;
default:
return -EINVAL;
}
}
hw->adv_cfg = adv_cfg;
return alx_setup_speed_duplex(hw, adv_cfg, hw->flowctrl);
}
static void alx_get_pauseparam(struct net_device *netdev,
struct ethtool_pauseparam *pause)
{
struct alx_priv *alx = netdev_priv(netdev);
struct alx_hw *hw = &alx->hw;
if (hw->flowctrl & ALX_FC_ANEG &&
hw->adv_cfg & ADVERTISED_Autoneg)
pause->autoneg = AUTONEG_ENABLE;
else
pause->autoneg = AUTONEG_DISABLE;
if (hw->flowctrl & ALX_FC_TX)
pause->tx_pause = 1;
else
pause->tx_pause = 0;
if (hw->flowctrl & ALX_FC_RX)
pause->rx_pause = 1;
else
pause->rx_pause = 0;
}
static int alx_set_pauseparam(struct net_device *netdev,
struct ethtool_pauseparam *pause)
{
struct alx_priv *alx = netdev_priv(netdev);
struct alx_hw *hw = &alx->hw;
int err = 0;
bool reconfig_phy = false;
u8 fc = 0;
if (pause->tx_pause)
fc |= ALX_FC_TX;
if (pause->rx_pause)
fc |= ALX_FC_RX;
if (pause->autoneg)
fc |= ALX_FC_ANEG;
ASSERT_RTNL();
/* restart auto-neg for auto-mode */
if (hw->adv_cfg & ADVERTISED_Autoneg) {
if (!((fc ^ hw->flowctrl) & ALX_FC_ANEG))
reconfig_phy = true;
if (fc & hw->flowctrl & ALX_FC_ANEG &&
(fc ^ hw->flowctrl) & (ALX_FC_RX | ALX_FC_TX))
reconfig_phy = true;
}
if (reconfig_phy) {
err = alx_setup_speed_duplex(hw, hw->adv_cfg, fc);
return err;
}
/* flow control on mac */
if ((fc ^ hw->flowctrl) & (ALX_FC_RX | ALX_FC_TX))
alx_cfg_mac_flowcontrol(hw, fc);
hw->flowctrl = fc;
return 0;
}
static u32 alx_get_msglevel(struct net_device *netdev)
{
struct alx_priv *alx = netdev_priv(netdev);
return alx->msg_enable;
}
static void alx_set_msglevel(struct net_device *netdev, u32 data)
{
struct alx_priv *alx = netdev_priv(netdev);
alx->msg_enable = data;
}
static void alx_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
{
struct alx_priv *alx = netdev_priv(netdev);
struct alx_hw *hw = &alx->hw;
wol->supported = WAKE_MAGIC | WAKE_PHY;
wol->wolopts = 0;
if (hw->sleep_ctrl & ALX_SLEEP_WOL_MAGIC)
wol->wolopts |= WAKE_MAGIC;
if (hw->sleep_ctrl & ALX_SLEEP_WOL_PHY)
wol->wolopts |= WAKE_PHY;
}
static int alx_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
{
struct alx_priv *alx = netdev_priv(netdev);
struct alx_hw *hw = &alx->hw;
if (wol->wolopts & (WAKE_ARP | WAKE_MAGICSECURE |
WAKE_UCAST | WAKE_BCAST | WAKE_MCAST))
return -EOPNOTSUPP;
hw->sleep_ctrl = 0;
if (wol->wolopts & WAKE_MAGIC)
hw->sleep_ctrl |= ALX_SLEEP_WOL_MAGIC;
if (wol->wolopts & WAKE_PHY)
hw->sleep_ctrl |= ALX_SLEEP_WOL_PHY;
device_set_wakeup_enable(&alx->hw.pdev->dev, hw->sleep_ctrl);
return 0;
}
static void alx_get_drvinfo(struct net_device *netdev,
struct ethtool_drvinfo *drvinfo)
{
struct alx_priv *alx = netdev_priv(netdev);
strlcpy(drvinfo->driver, alx_drv_name, sizeof(drvinfo->driver));
strlcpy(drvinfo->bus_info, pci_name(alx->hw.pdev),
sizeof(drvinfo->bus_info));
}
const struct ethtool_ops alx_ethtool_ops = {
.get_settings = alx_get_settings,
.set_settings = alx_set_settings,
.get_pauseparam = alx_get_pauseparam,
.set_pauseparam = alx_set_pauseparam,
.get_drvinfo = alx_get_drvinfo,
.get_msglevel = alx_get_msglevel,
.set_msglevel = alx_set_msglevel,
.get_wol = alx_get_wol,
.set_wol = alx_set_wol,
.get_link = ethtool_op_get_link,
};

1226
drivers/net/ethernet/atheros/alx/hw.c Normal file
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499
drivers/net/ethernet/atheros/alx/hw.h Normal file
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@ -0,0 +1,499 @@
/*
* Copyright (c) 2013 Johannes Berg <johannes@sipsolutions.net>
*
* This file is free software: you may copy, redistribute and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation, either version 2 of the License, or (at your
* option) any later version.
*
* This file is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
* This file incorporates work covered by the following copyright and
* permission notice:
*
* Copyright (c) 2012 Qualcomm Atheros, Inc.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef ALX_HW_H_
#define ALX_HW_H_
#include <linux/types.h>
#include <linux/mdio.h>
#include <linux/pci.h>
#include "reg.h"
/* Transmit Packet Descriptor, contains 4 32-bit words.
*
* 31 16 0
* +----------------+----------------+
* | vlan-tag | buf length |
* +----------------+----------------+
* | Word 1 |
* +----------------+----------------+
* | Word 2: buf addr lo |
* +----------------+----------------+
* | Word 3: buf addr hi |
* +----------------+----------------+
*
* Word 2 and 3 combine to form a 64-bit buffer address
*
* Word 1 has three forms, depending on the state of bit 8/12/13:
* if bit8 =='1', the definition is just for custom checksum offload.
* if bit8 == '0' && bit12 == '1' && bit13 == '1', the *FIRST* descriptor
* for the skb is special for LSO V2, Word 2 become total skb length ,
* Word 3 is meaningless.
* other condition, the definition is for general skb or ip/tcp/udp
* checksum or LSO(TSO) offload.
*
* Here is the depiction:
*
* 0-+ 0-+
* 1 | 1 |
* 2 | 2 |
* 3 | Payload offset 3 | L4 header offset
* 4 | (7:0) 4 | (7:0)
* 5 | 5 |
* 6 | 6 |
* 7-+ 7-+
* 8 Custom csum enable = 1 8 Custom csum enable = 0
* 9 General IPv4 checksum 9 General IPv4 checksum
* 10 General TCP checksum 10 General TCP checksum
* 11 General UDP checksum 11 General UDP checksum
* 12 Large Send Segment enable 12 Large Send Segment enable
* 13 Large Send Segment type 13 Large Send Segment type
* 14 VLAN tagged 14 VLAN tagged
* 15 Insert VLAN tag 15 Insert VLAN tag
* 16 IPv4 packet 16 IPv4 packet
* 17 Ethernet frame type 17 Ethernet frame type
* 18-+ 18-+
* 19 | 19 |
* 20 | 20 |
* 21 | Custom csum offset 21 |
* 22 | (25:18) 22 |
* 23 | 23 | MSS (30:18)
* 24 | 24 |
* 25-+ 25 |
* 26-+ 26 |
* 27 | 27 |
* 28 | Reserved 28 |
* 29 | 29 |
* 30-+ 30-+
* 31 End of packet 31 End of packet
*/
struct alx_txd {
__le16 len;
__le16 vlan_tag;
__le32 word1;
union {
__le64 addr;
struct {
__le32 pkt_len;
__le32 resvd;
} l;
} adrl;
} __packed;
/* tpd word 1 */
#define TPD_CXSUMSTART_MASK 0x00FF
#define TPD_CXSUMSTART_SHIFT 0
#define TPD_L4HDROFFSET_MASK 0x00FF
#define TPD_L4HDROFFSET_SHIFT 0
#define TPD_CXSUM_EN_MASK 0x0001
#define TPD_CXSUM_EN_SHIFT 8
#define TPD_IP_XSUM_MASK 0x0001
#define TPD_IP_XSUM_SHIFT 9
#define TPD_TCP_XSUM_MASK 0x0001
#define TPD_TCP_XSUM_SHIFT 10
#define TPD_UDP_XSUM_MASK 0x0001
#define TPD_UDP_XSUM_SHIFT 11
#define TPD_LSO_EN_MASK 0x0001
#define TPD_LSO_EN_SHIFT 12
#define TPD_LSO_V2_MASK 0x0001
#define TPD_LSO_V2_SHIFT 13
#define TPD_VLTAGGED_MASK 0x0001
#define TPD_VLTAGGED_SHIFT 14
#define TPD_INS_VLTAG_MASK 0x0001
#define TPD_INS_VLTAG_SHIFT 15
#define TPD_IPV4_MASK 0x0001
#define TPD_IPV4_SHIFT 16
#define TPD_ETHTYPE_MASK 0x0001
#define TPD_ETHTYPE_SHIFT 17
#define TPD_CXSUMOFFSET_MASK 0x00FF
#define TPD_CXSUMOFFSET_SHIFT 18
#define TPD_MSS_MASK 0x1FFF
#define TPD_MSS_SHIFT 18
#define TPD_EOP_MASK 0x0001
#define TPD_EOP_SHIFT 31
#define DESC_GET(_x, _name) ((_x) >> _name##SHIFT & _name##MASK)
/* Receive Free Descriptor */
struct alx_rfd {
__le64 addr; /* data buffer address, length is
* declared in register --- every
* buffer has the same size
*/
} __packed;
/* Receive Return Descriptor, contains 4 32-bit words.
*
* 31 16 0
* +----------------+----------------+
* | Word 0 |
* +----------------+----------------+
* | Word 1: RSS Hash value |
* +----------------+----------------+
* | Word 2 |
* +----------------+----------------+
* | Word 3 |
* +----------------+----------------+
*
* Word 0 depiction & Word 2 depiction:
*
* 0--+ 0--+
* 1 | 1 |
* 2 | 2 |
* 3 | 3 |
* 4 | 4 |
* 5 | 5 |
* 6 | 6 |
* 7 | IP payload checksum 7 | VLAN tag
* 8 | (15:0) 8 | (15:0)
* 9 | 9 |
* 10 | 10 |
* 11 | 11 |
* 12 | 12 |
* 13 | 13 |
* 14 | 14 |
* 15-+ 15-+
* 16-+ 16-+
* 17 | Number of RFDs 17 |
* 18 | (19:16) 18 |
* 19-+ 19 | Protocol ID
* 20-+ 20 | (23:16)
* 21 | 21 |
* 22 | 22 |
* 23 | 23-+
* 24 | 24 | Reserved
* 25 | Start index of RFD-ring 25-+
* 26 | (31:20) 26 | RSS Q-num (27:25)
* 27 | 27-+
* 28 | 28-+
* 29 | 29 | RSS Hash algorithm
* 30 | 30 | (31:28)
* 31-+ 31-+
*
* Word 3 depiction:
*
* 0--+
* 1 |
* 2 |
* 3 |
* 4 |
* 5 |
* 6 |
* 7 | Packet length (include FCS)
* 8 | (13:0)
* 9 |
* 10 |
* 11 |
* 12 |
* 13-+
* 14 L4 Header checksum error
* 15 IPv4 checksum error
* 16 VLAN tagged
* 17-+
* 18 | Protocol ID (19:17)
* 19-+
* 20 Receive error summary
* 21 FCS(CRC) error
* 22 Frame alignment error
* 23 Truncated packet
* 24 Runt packet
* 25 Incomplete packet due to insufficient rx-desc
* 26 Broadcast packet
* 27 Multicast packet
* 28 Ethernet type (EII or 802.3)
* 29 FIFO overflow
* 30 Length error (for 802.3, length field mismatch with actual len)
* 31 Updated, indicate to driver that this RRD is refreshed.
*/
struct alx_rrd {
__le32 word0;
__le32 rss_hash;
__le32 word2;
__le32 word3;
} __packed;
/* rrd word 0 */
#define RRD_XSUM_MASK 0xFFFF
#define RRD_XSUM_SHIFT 0
#define RRD_NOR_MASK 0x000F
#define RRD_NOR_SHIFT 16
#define RRD_SI_MASK 0x0FFF
#define RRD_SI_SHIFT 20
/* rrd word 2 */
#define RRD_VLTAG_MASK 0xFFFF
#define RRD_VLTAG_SHIFT 0
#define RRD_PID_MASK 0x00FF
#define RRD_PID_SHIFT 16
/* non-ip packet */
#define RRD_PID_NONIP 0
/* ipv4(only) */
#define RRD_PID_IPV4 1
/* tcp/ipv6 */
#define RRD_PID_IPV6TCP 2
/* tcp/ipv4 */
#define RRD_PID_IPV4TCP 3
/* udp/ipv6 */
#define RRD_PID_IPV6UDP 4
/* udp/ipv4 */
#define RRD_PID_IPV4UDP 5
/* ipv6(only) */
#define RRD_PID_IPV6 6
/* LLDP packet */
#define RRD_PID_LLDP 7
/* 1588 packet */
#define RRD_PID_1588 8
#define RRD_RSSQ_MASK 0x0007
#define RRD_RSSQ_SHIFT 25
#define RRD_RSSALG_MASK 0x000F
#define RRD_RSSALG_SHIFT 28
#define RRD_RSSALG_TCPV6 0x1
#define RRD_RSSALG_IPV6 0x2
#define RRD_RSSALG_TCPV4 0x4
#define RRD_RSSALG_IPV4 0x8
/* rrd word 3 */
#define RRD_PKTLEN_MASK 0x3FFF
#define RRD_PKTLEN_SHIFT 0
#define RRD_ERR_L4_MASK 0x0001
#define RRD_ERR_L4_SHIFT 14
#define RRD_ERR_IPV4_MASK 0x0001
#define RRD_ERR_IPV4_SHIFT 15
#define RRD_VLTAGGED_MASK 0x0001
#define RRD_VLTAGGED_SHIFT 16
#define RRD_OLD_PID_MASK 0x0007
#define RRD_OLD_PID_SHIFT 17
#define RRD_ERR_RES_MASK 0x0001
#define RRD_ERR_RES_SHIFT 20
#define RRD_ERR_FCS_MASK 0x0001
#define RRD_ERR_FCS_SHIFT 21
#define RRD_ERR_FAE_MASK 0x0001
#define RRD_ERR_FAE_SHIFT 22
#define RRD_ERR_TRUNC_MASK 0x0001
#define RRD_ERR_TRUNC_SHIFT 23
#define RRD_ERR_RUNT_MASK 0x0001
#define RRD_ERR_RUNT_SHIFT 24
#define RRD_ERR_ICMP_MASK 0x0001
#define RRD_ERR_ICMP_SHIFT 25
#define RRD_BCAST_MASK 0x0001
#define RRD_BCAST_SHIFT 26
#define RRD_MCAST_MASK 0x0001
#define RRD_MCAST_SHIFT 27
#define RRD_ETHTYPE_MASK 0x0001
#define RRD_ETHTYPE_SHIFT 28
#define RRD_ERR_FIFOV_MASK 0x0001
#define RRD_ERR_FIFOV_SHIFT 29
#define RRD_ERR_LEN_MASK 0x0001
#define RRD_ERR_LEN_SHIFT 30
#define RRD_UPDATED_MASK 0x0001
#define RRD_UPDATED_SHIFT 31
#define ALX_MAX_SETUP_LNK_CYCLE 50
/* for FlowControl */
#define ALX_FC_RX 0x01
#define ALX_FC_TX 0x02
#define ALX_FC_ANEG 0x04
/* for sleep control */
#define ALX_SLEEP_WOL_PHY 0x00000001
#define ALX_SLEEP_WOL_MAGIC 0x00000002
#define ALX_SLEEP_CIFS 0x00000004
#define ALX_SLEEP_ACTIVE (ALX_SLEEP_WOL_PHY | \
ALX_SLEEP_WOL_MAGIC | \
ALX_SLEEP_CIFS)
/* for RSS hash type */
#define ALX_RSS_HASH_TYPE_IPV4 0x1
#define ALX_RSS_HASH_TYPE_IPV4_TCP 0x2
#define ALX_RSS_HASH_TYPE_IPV6 0x4
#define ALX_RSS_HASH_TYPE_IPV6_TCP 0x8
#define ALX_RSS_HASH_TYPE_ALL (ALX_RSS_HASH_TYPE_IPV4 | \
ALX_RSS_HASH_TYPE_IPV4_TCP | \
ALX_RSS_HASH_TYPE_IPV6 | \
ALX_RSS_HASH_TYPE_IPV6_TCP)
#define ALX_DEF_RXBUF_SIZE 1536
#define ALX_MAX_JUMBO_PKT_SIZE (9*1024)
#define ALX_MAX_TSO_PKT_SIZE (7*1024)
#define ALX_MAX_FRAME_SIZE ALX_MAX_JUMBO_PKT_SIZE
#define ALX_MIN_FRAME_SIZE 68
#define ALX_RAW_MTU(_mtu) (_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN)
#define ALX_MAX_RX_QUEUES 8
#define ALX_MAX_TX_QUEUES 4
#define ALX_MAX_HANDLED_INTRS 5
#define ALX_ISR_MISC (ALX_ISR_PCIE_LNKDOWN | \
ALX_ISR_DMAW | \
ALX_ISR_DMAR | \
ALX_ISR_SMB | \
ALX_ISR_MANU | \
ALX_ISR_TIMER)
#define ALX_ISR_FATAL (ALX_ISR_PCIE_LNKDOWN | \
ALX_ISR_DMAW | ALX_ISR_DMAR)
#define ALX_ISR_ALERT (ALX_ISR_RXF_OV | \
ALX_ISR_TXF_UR | \
ALX_ISR_RFD_UR)
#define ALX_ISR_ALL_QUEUES (ALX_ISR_TX_Q0 | \
ALX_ISR_TX_Q1 | \
ALX_ISR_TX_Q2 | \
ALX_ISR_TX_Q3 | \
ALX_ISR_RX_Q0 | \
ALX_ISR_RX_Q1 | \
ALX_ISR_RX_Q2 | \
ALX_ISR_RX_Q3 | \
ALX_ISR_RX_Q4 | \
ALX_ISR_RX_Q5 | \
ALX_ISR_RX_Q6 | \
ALX_ISR_RX_Q7)
/* maximum interrupt vectors for msix */
#define ALX_MAX_MSIX_INTRS 16
#define ALX_GET_FIELD(_data, _field) \
(((_data) >> _field ## _SHIFT) & _field ## _MASK)
#define ALX_SET_FIELD(_data, _field, _value) do { \
(_data) &= ~(_field ## _MASK << _field ## _SHIFT); \
(_data) |= ((_value) & _field ## _MASK) << _field ## _SHIFT;\
} while (0)
struct alx_hw {
struct pci_dev *pdev;
u8 __iomem *hw_addr;
/* current & permanent mac addr */
u8 mac_addr[ETH_ALEN];
u8 perm_addr[ETH_ALEN];
u16 mtu;
u16 imt;
u8 dma_chnl;
u8 max_dma_chnl;
/* tpd threshold to trig INT */
u32 ith_tpd;
u32 rx_ctrl;
u32 mc_hash[2];
u32 smb_timer;
/* SPEED_* + DUPLEX_*, SPEED_UNKNOWN if link is down */
int link_speed;
/* auto-neg advertisement or force mode config */
u32 adv_cfg;
u8 flowctrl;
u32 sleep_ctrl;
spinlock_t mdio_lock;
struct mdio_if_info mdio;
u16 phy_id[2];
/* PHY link patch flag */
bool lnk_patch;
};
static inline int alx_hw_revision(struct alx_hw *hw)
{
return hw->pdev->revision >> ALX_PCI_REVID_SHIFT;
}
static inline bool alx_hw_with_cr(struct alx_hw *hw)
{
return hw->pdev->revision & 1;
}
static inline bool alx_hw_giga(struct alx_hw *hw)
{
return hw->pdev->device & 1;
}
static inline void alx_write_mem8(struct alx_hw *hw, u32 reg, u8 val)
{
writeb(val, hw->hw_addr + reg);
}
static inline void alx_write_mem16(struct alx_hw *hw, u32 reg, u16 val)
{
writew(val, hw->hw_addr + reg);
}
static inline u16 alx_read_mem16(struct alx_hw *hw, u32 reg)
{
return readw(hw->hw_addr + reg);
}
static inline void alx_write_mem32(struct alx_hw *hw, u32 reg, u32 val)
{
writel(val, hw->hw_addr + reg);
}
static inline u32 alx_read_mem32(struct alx_hw *hw, u32 reg)
{
return readl(hw->hw_addr + reg);
}
static inline void alx_post_write(struct alx_hw *hw)
{
readl(hw->hw_addr);
}
int alx_get_perm_macaddr(struct alx_hw *hw, u8 *addr);
void alx_reset_phy(struct alx_hw *hw);
void alx_reset_pcie(struct alx_hw *hw);
void alx_enable_aspm(struct alx_hw *hw, bool l0s_en, bool l1_en);
int alx_setup_speed_duplex(struct alx_hw *hw, u32 ethadv, u8 flowctrl);
void alx_post_phy_link(struct alx_hw *hw);
int alx_pre_suspend(struct alx_hw *hw, int speed);
int alx_read_phy_reg(struct alx_hw *hw, u16 reg, u16 *phy_data);
int alx_write_phy_reg(struct alx_hw *hw, u16 reg, u16 phy_data);
int alx_read_phy_ext(struct alx_hw *hw, u8 dev, u16 reg, u16 *pdata);
int alx_write_phy_ext(struct alx_hw *hw, u8 dev, u16 reg, u16 data);
int alx_get_phy_link(struct alx_hw *hw, int *speed);
int alx_clear_phy_intr(struct alx_hw *hw);
int alx_config_wol(struct alx_hw *hw);
void alx_cfg_mac_flowcontrol(struct alx_hw *hw, u8 fc);
void alx_start_mac(struct alx_hw *hw);
int alx_reset_mac(struct alx_hw *hw);
void alx_set_macaddr(struct alx_hw *hw, const u8 *addr);
bool alx_phy_configured(struct alx_hw *hw);
void alx_configure_basic(struct alx_hw *hw);
void alx_disable_rss(struct alx_hw *hw);
int alx_select_powersaving_speed(struct alx_hw *hw, int *speed);
bool alx_get_phy_info(struct alx_hw *hw);
#endif

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/*
* Copyright (c) 2013 Johannes Berg <johannes@sipsolutions.net>
*
* This file is free software: you may copy, redistribute and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation, either version 2 of the License, or (at your
* option) any later version.
*
* This file is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
* This file incorporates work covered by the following copyright and
* permission notice:
*
* Copyright (c) 2012 Qualcomm Atheros, Inc.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef ALX_REG_H
#define ALX_REG_H
#define ALX_DEV_ID_AR8161 0x1091
#define ALX_DEV_ID_E2200 0xe091
#define ALX_DEV_ID_AR8162 0x1090
#define ALX_DEV_ID_AR8171 0x10A1
#define ALX_DEV_ID_AR8172 0x10A0
/* rev definition,
* bit(0): with xD support
* bit(1): with Card Reader function
* bit(7:2): real revision
*/
#define ALX_PCI_REVID_SHIFT 3
#define ALX_REV_A0 0
#define ALX_REV_A1 1
#define ALX_REV_B0 2
#define ALX_REV_C0 3
#define ALX_DEV_CTRL 0x0060
#define ALX_DEV_CTRL_MAXRRS_MIN 2
#define ALX_MSIX_MASK 0x0090
#define ALX_UE_SVRT 0x010C
#define ALX_UE_SVRT_FCPROTERR BIT(13)
#define ALX_UE_SVRT_DLPROTERR BIT(4)
/* eeprom & flash load register */
#define ALX_EFLD 0x0204
#define ALX_EFLD_F_EXIST BIT(10)
#define ALX_EFLD_E_EXIST BIT(9)
#define ALX_EFLD_STAT BIT(5)
#define ALX_EFLD_START BIT(0)
/* eFuse load register */
#define ALX_SLD 0x0218
#define ALX_SLD_STAT BIT(12)
#define ALX_SLD_START BIT(11)
#define ALX_SLD_MAX_TO 100
#define ALX_PDLL_TRNS1 0x1104
#define ALX_PDLL_TRNS1_D3PLLOFF_EN BIT(11)
#define ALX_PMCTRL 0x12F8
#define ALX_PMCTRL_HOTRST_WTEN BIT(31)
/* bit30: L0s/L1 controlled by MAC based on throughput(setting in 15A0) */
#define ALX_PMCTRL_ASPM_FCEN BIT(30)
#define ALX_PMCTRL_SADLY_EN BIT(29)
#define ALX_PMCTRL_LCKDET_TIMER_MASK 0xF
#define ALX_PMCTRL_LCKDET_TIMER_SHIFT 24
#define ALX_PMCTRL_LCKDET_TIMER_DEF 0xC
/* bit[23:20] if pm_request_l1 time > @, then enter L0s not L1 */
#define ALX_PMCTRL_L1REQ_TO_MASK 0xF
#define ALX_PMCTRL_L1REQ_TO_SHIFT 20
#define ALX_PMCTRL_L1REG_TO_DEF 0xF
#define ALX_PMCTRL_TXL1_AFTER_L0S BIT(19)
#define ALX_PMCTRL_L1_TIMER_MASK 0x7
#define ALX_PMCTRL_L1_TIMER_SHIFT 16
#define ALX_PMCTRL_L1_TIMER_16US 4
#define ALX_PMCTRL_RCVR_WT_1US BIT(15)
/* bit13: enable pcie clk switch in L1 state */
#define ALX_PMCTRL_L1_CLKSW_EN BIT(13)
#define ALX_PMCTRL_L0S_EN BIT(12)
#define ALX_PMCTRL_RXL1_AFTER_L0S BIT(11)
#define ALX_PMCTRL_L1_BUFSRX_EN BIT(7)
/* bit6: power down serdes RX */
#define ALX_PMCTRL_L1_SRDSRX_PWD BIT(6)
#define ALX_PMCTRL_L1_SRDSPLL_EN BIT(5)
#define ALX_PMCTRL_L1_SRDS_EN BIT(4)
#define ALX_PMCTRL_L1_EN BIT(3)
/*******************************************************/
/* following registers are mapped only to memory space */
/*******************************************************/
#define ALX_MASTER 0x1400
/* bit12: 1:alwys select pclk from serdes, not sw to 25M */
#define ALX_MASTER_PCLKSEL_SRDS BIT(12)
/* bit11: irq moduration for rx */
#define ALX_MASTER_IRQMOD2_EN BIT(11)
/* bit10: irq moduration for tx/rx */
#define ALX_MASTER_IRQMOD1_EN BIT(10)
#define ALX_MASTER_SYSALVTIMER_EN BIT(7)
#define ALX_MASTER_OOB_DIS BIT(6)
/* bit5: wakeup without pcie clk */
#define ALX_MASTER_WAKEN_25M BIT(5)
/* bit0: MAC & DMA reset */
#define ALX_MASTER_DMA_MAC_RST BIT(0)
#define ALX_DMA_MAC_RST_TO 50
#define ALX_IRQ_MODU_TIMER 0x1408
#define ALX_IRQ_MODU_TIMER1_MASK 0xFFFF
#define ALX_IRQ_MODU_TIMER1_SHIFT 0
#define ALX_PHY_CTRL 0x140C
#define ALX_PHY_CTRL_100AB_EN BIT(17)
/* bit14: affect MAC & PHY, go to low power sts */
#define ALX_PHY_CTRL_POWER_DOWN BIT(14)
/* bit13: 1:pll always ON, 0:can switch in lpw */
#define ALX_PHY_CTRL_PLL_ON BIT(13)
#define ALX_PHY_CTRL_RST_ANALOG BIT(12)
#define ALX_PHY_CTRL_HIB_PULSE BIT(11)
#define ALX_PHY_CTRL_HIB_EN BIT(10)
#define ALX_PHY_CTRL_IDDQ BIT(7)
#define ALX_PHY_CTRL_GATE_25M BIT(5)
#define ALX_PHY_CTRL_LED_MODE BIT(2)
/* bit0: out of dsp RST state */
#define ALX_PHY_CTRL_DSPRST_OUT BIT(0)
#define ALX_PHY_CTRL_DSPRST_TO 80
#define ALX_PHY_CTRL_CLS (ALX_PHY_CTRL_LED_MODE | \
ALX_PHY_CTRL_100AB_EN | \
ALX_PHY_CTRL_PLL_ON)
#define ALX_MAC_STS 0x1410
#define ALX_MAC_STS_TXQ_BUSY BIT(3)
#define ALX_MAC_STS_RXQ_BUSY BIT(2)
#define ALX_MAC_STS_TXMAC_BUSY BIT(1)
#define ALX_MAC_STS_RXMAC_BUSY BIT(0)
#define ALX_MAC_STS_IDLE (ALX_MAC_STS_TXQ_BUSY | \
ALX_MAC_STS_RXQ_BUSY | \
ALX_MAC_STS_TXMAC_BUSY | \
ALX_MAC_STS_RXMAC_BUSY)
#define ALX_MDIO 0x1414
#define ALX_MDIO_MODE_EXT BIT(30)
#define ALX_MDIO_BUSY BIT(27)
#define ALX_MDIO_CLK_SEL_MASK 0x7
#define ALX_MDIO_CLK_SEL_SHIFT 24
#define ALX_MDIO_CLK_SEL_25MD4 0
#define ALX_MDIO_CLK_SEL_25MD128 7
#define ALX_MDIO_START BIT(23)
#define ALX_MDIO_SPRES_PRMBL BIT(22)
/* bit21: 1:read,0:write */
#define ALX_MDIO_OP_READ BIT(21)
#define ALX_MDIO_REG_MASK 0x1F
#define ALX_MDIO_REG_SHIFT 16
#define ALX_MDIO_DATA_MASK 0xFFFF
#define ALX_MDIO_DATA_SHIFT 0
#define ALX_MDIO_MAX_AC_TO 120
#define ALX_MDIO_EXTN 0x1448
#define ALX_MDIO_EXTN_DEVAD_MASK 0x1F
#define ALX_MDIO_EXTN_DEVAD_SHIFT 16
#define ALX_MDIO_EXTN_REG_MASK 0xFFFF
#define ALX_MDIO_EXTN_REG_SHIFT 0
#define ALX_SERDES 0x1424
#define ALX_SERDES_PHYCLK_SLWDWN BIT(18)
#define ALX_SERDES_MACCLK_SLWDWN BIT(17)
#define ALX_LPI_CTRL 0x1440
#define ALX_LPI_CTRL_EN BIT(0)
/* for B0+, bit[13..] for C0+ */
#define ALX_HRTBT_EXT_CTRL 0x1AD0
#define L1F_HRTBT_EXT_CTRL_PERIOD_HIGH_MASK 0x3F
#define L1F_HRTBT_EXT_CTRL_PERIOD_HIGH_SHIFT 24
#define L1F_HRTBT_EXT_CTRL_SWOI_STARTUP_PKT_EN BIT(23)
#define L1F_HRTBT_EXT_CTRL_IOAC_2_FRAGMENTED BIT(22)
#define L1F_HRTBT_EXT_CTRL_IOAC_1_FRAGMENTED BIT(21)
#define L1F_HRTBT_EXT_CTRL_IOAC_1_KEEPALIVE_EN BIT(20)
#define L1F_HRTBT_EXT_CTRL_IOAC_1_HAS_VLAN BIT(19)
#define L1F_HRTBT_EXT_CTRL_IOAC_1_IS_8023 BIT(18)
#define L1F_HRTBT_EXT_CTRL_IOAC_1_IS_IPV6 BIT(17)
#define L1F_HRTBT_EXT_CTRL_IOAC_2_KEEPALIVE_EN BIT(16)
#define L1F_HRTBT_EXT_CTRL_IOAC_2_HAS_VLAN BIT(15)
#define L1F_HRTBT_EXT_CTRL_IOAC_2_IS_8023 BIT(14)
#define L1F_HRTBT_EXT_CTRL_IOAC_2_IS_IPV6 BIT(13)
#define ALX_HRTBT_EXT_CTRL_NS_EN BIT(12)
#define ALX_HRTBT_EXT_CTRL_FRAG_LEN_MASK 0xFF
#define ALX_HRTBT_EXT_CTRL_FRAG_LEN_SHIFT 4
#define ALX_HRTBT_EXT_CTRL_IS_8023 BIT(3)
#define ALX_HRTBT_EXT_CTRL_IS_IPV6 BIT(2)
#define ALX_HRTBT_EXT_CTRL_WAKEUP_EN BIT(1)
#define ALX_HRTBT_EXT_CTRL_ARP_EN BIT(0)
#define ALX_HRTBT_REM_IPV4_ADDR 0x1AD4
#define ALX_HRTBT_HOST_IPV4_ADDR 0x1478
#define ALX_HRTBT_REM_IPV6_ADDR3 0x1AD8
#define ALX_HRTBT_REM_IPV6_ADDR2 0x1ADC
#define ALX_HRTBT_REM_IPV6_ADDR1 0x1AE0
#define ALX_HRTBT_REM_IPV6_ADDR0 0x1AE4
/* 1B8C ~ 1B94 for C0+ */
#define ALX_SWOI_ACER_CTRL 0x1B8C
#define ALX_SWOI_ORIG_ACK_NAK_EN BIT(20)
#define ALX_SWOI_ORIG_ACK_NAK_PKT_LEN_MASK 0XFF
#define ALX_SWOI_ORIG_ACK_NAK_PKT_LEN_SHIFT 12
#define ALX_SWOI_ORIG_ACK_ADDR_MASK 0XFFF
#define ALX_SWOI_ORIG_ACK_ADDR_SHIFT 0
#define ALX_SWOI_IOAC_CTRL_2 0x1B90
#define ALX_SWOI_IOAC_CTRL_2_SWOI_1_FRAG_LEN_MASK 0xFF
#define ALX_SWOI_IOAC_CTRL_2_SWOI_1_FRAG_LEN_SHIFT 24
#define ALX_SWOI_IOAC_CTRL_2_SWOI_1_PKT_LEN_MASK 0xFFF
#define ALX_SWOI_IOAC_CTRL_2_SWOI_1_PKT_LEN_SHIFT 12
#define ALX_SWOI_IOAC_CTRL_2_SWOI_1_HDR_ADDR_MASK 0xFFF
#define ALX_SWOI_IOAC_CTRL_2_SWOI_1_HDR_ADDR_SHIFT 0
#define ALX_SWOI_IOAC_CTRL_3 0x1B94
#define ALX_SWOI_IOAC_CTRL_3_SWOI_2_FRAG_LEN_MASK 0xFF
#define ALX_SWOI_IOAC_CTRL_3_SWOI_2_FRAG_LEN_SHIFT 24
#define ALX_SWOI_IOAC_CTRL_3_SWOI_2_PKT_LEN_MASK 0xFFF
#define ALX_SWOI_IOAC_CTRL_3_SWOI_2_PKT_LEN_SHIFT 12
#define ALX_SWOI_IOAC_CTRL_3_SWOI_2_HDR_ADDR_MASK 0xFFF
#define ALX_SWOI_IOAC_CTRL_3_SWOI_2_HDR_ADDR_SHIFT 0
/* for B0 */
#define ALX_IDLE_DECISN_TIMER 0x1474
/* 1ms */
#define ALX_IDLE_DECISN_TIMER_DEF 0x400
#define ALX_MAC_CTRL 0x1480
#define ALX_MAC_CTRL_FAST_PAUSE BIT(31)
#define ALX_MAC_CTRL_WOLSPED_SWEN BIT(30)
/* bit29: 1:legacy(hi5b), 0:marvl(lo5b)*/
#define ALX_MAC_CTRL_MHASH_ALG_HI5B BIT(29)
#define ALX_MAC_CTRL_BRD_EN BIT(26)
#define ALX_MAC_CTRL_MULTIALL_EN BIT(25)
#define ALX_MAC_CTRL_SPEED_MASK 0x3
#define ALX_MAC_CTRL_SPEED_SHIFT 20
#define ALX_MAC_CTRL_SPEED_10_100 1
#define ALX_MAC_CTRL_SPEED_1000 2
#define ALX_MAC_CTRL_PROMISC_EN BIT(15)
#define ALX_MAC_CTRL_VLANSTRIP BIT(14)
#define ALX_MAC_CTRL_PRMBLEN_MASK 0xF
#define ALX_MAC_CTRL_PRMBLEN_SHIFT 10
#define ALX_MAC_CTRL_PCRCE BIT(7)
#define ALX_MAC_CTRL_CRCE BIT(6)
#define ALX_MAC_CTRL_FULLD BIT(5)
#define ALX_MAC_CTRL_RXFC_EN BIT(3)
#define ALX_MAC_CTRL_TXFC_EN BIT(2)
#define ALX_MAC_CTRL_RX_EN BIT(1)
#define ALX_MAC_CTRL_TX_EN BIT(0)
#define ALX_STAD0 0x1488
#define ALX_STAD1 0x148C
#define ALX_HASH_TBL0 0x1490
#define ALX_HASH_TBL1 0x1494
#define ALX_MTU 0x149C
#define ALX_MTU_JUMBO_TH 1514
#define ALX_MTU_STD_ALGN 1536
#define ALX_SRAM5 0x1524
#define ALX_SRAM_RXF_LEN_MASK 0xFFF
#define ALX_SRAM_RXF_LEN_SHIFT 0
#define ALX_SRAM_RXF_LEN_8K (8*1024)
#define ALX_SRAM9 0x1534
#define ALX_SRAM_LOAD_PTR BIT(0)
#define ALX_RX_BASE_ADDR_HI 0x1540
#define ALX_TX_BASE_ADDR_HI 0x1544
#define ALX_RFD_ADDR_LO 0x1550
#define ALX_RFD_RING_SZ 0x1560
#define ALX_RFD_BUF_SZ 0x1564
#define ALX_RRD_ADDR_LO 0x1568
#define ALX_RRD_RING_SZ 0x1578
/* pri3: highest, pri0: lowest */
#define ALX_TPD_PRI3_ADDR_LO 0x14E4
#define ALX_TPD_PRI2_ADDR_LO 0x14E0
#define ALX_TPD_PRI1_ADDR_LO 0x157C
#define ALX_TPD_PRI0_ADDR_LO 0x1580
/* producer index is 16bit */
#define ALX_TPD_PRI3_PIDX 0x1618
#define ALX_TPD_PRI2_PIDX 0x161A
#define ALX_TPD_PRI1_PIDX 0x15F0
#define ALX_TPD_PRI0_PIDX 0x15F2
/* consumer index is 16bit */
#define ALX_TPD_PRI3_CIDX 0x161C
#define ALX_TPD_PRI2_CIDX 0x161E
#define ALX_TPD_PRI1_CIDX 0x15F4
#define ALX_TPD_PRI0_CIDX 0x15F6
#define ALX_TPD_RING_SZ 0x1584
#define ALX_TXQ0 0x1590
#define ALX_TXQ0_TXF_BURST_PREF_MASK 0xFFFF
#define ALX_TXQ0_TXF_BURST_PREF_SHIFT 16
#define ALX_TXQ_TXF_BURST_PREF_DEF 0x200
#define ALX_TXQ0_LSO_8023_EN BIT(7)
#define ALX_TXQ0_MODE_ENHANCE BIT(6)
#define ALX_TXQ0_EN BIT(5)
#define ALX_TXQ0_SUPT_IPOPT BIT(4)
#define ALX_TXQ0_TPD_BURSTPREF_MASK 0xF
#define ALX_TXQ0_TPD_BURSTPREF_SHIFT 0
#define ALX_TXQ_TPD_BURSTPREF_DEF 5
#define ALX_TXQ1 0x1594
/* bit11: drop large packet, len > (rfd buf) */
#define ALX_TXQ1_ERRLGPKT_DROP_EN BIT(11)
#define ALX_TXQ1_JUMBO_TSO_TH (7*1024)
#define ALX_RXQ0 0x15A0
#define ALX_RXQ0_EN BIT(31)
#define ALX_RXQ0_RSS_HASH_EN BIT(29)
#define ALX_RXQ0_RSS_MODE_MASK 0x3
#define ALX_RXQ0_RSS_MODE_SHIFT 26
#define ALX_RXQ0_RSS_MODE_DIS 0
#define ALX_RXQ0_RSS_MODE_MQMI 3
#define ALX_RXQ0_NUM_RFD_PREF_MASK 0x3F
#define ALX_RXQ0_NUM_RFD_PREF_SHIFT 20
#define ALX_RXQ0_NUM_RFD_PREF_DEF 8
#define ALX_RXQ0_IDT_TBL_SIZE_MASK 0x1FF
#define ALX_RXQ0_IDT_TBL_SIZE_SHIFT 8
#define ALX_RXQ0_IDT_TBL_SIZE_DEF 0x100
#define ALX_RXQ0_IDT_TBL_SIZE_NORMAL 128
#define ALX_RXQ0_IPV6_PARSE_EN BIT(7)
#define ALX_RXQ0_RSS_HSTYP_MASK 0xF
#define ALX_RXQ0_RSS_HSTYP_SHIFT 2
#define ALX_RXQ0_RSS_HSTYP_IPV6_TCP_EN BIT(5)
#define ALX_RXQ0_RSS_HSTYP_IPV6_EN BIT(4)
#define ALX_RXQ0_RSS_HSTYP_IPV4_TCP_EN BIT(3)
#define ALX_RXQ0_RSS_HSTYP_IPV4_EN BIT(2)
#define ALX_RXQ0_RSS_HSTYP_ALL (ALX_RXQ0_RSS_HSTYP_IPV6_TCP_EN | \
ALX_RXQ0_RSS_HSTYP_IPV4_TCP_EN | \
ALX_RXQ0_RSS_HSTYP_IPV6_EN | \
ALX_RXQ0_RSS_HSTYP_IPV4_EN)
#define ALX_RXQ0_ASPM_THRESH_MASK 0x3
#define ALX_RXQ0_ASPM_THRESH_SHIFT 0
#define ALX_RXQ0_ASPM_THRESH_100M 3
#define ALX_RXQ2 0x15A8
#define ALX_RXQ2_RXF_XOFF_THRESH_MASK 0xFFF
#define ALX_RXQ2_RXF_XOFF_THRESH_SHIFT 16
#define ALX_RXQ2_RXF_XON_THRESH_MASK 0xFFF
#define ALX_RXQ2_RXF_XON_THRESH_SHIFT 0
/* Size = tx-packet(1522) + IPG(12) + SOF(8) + 64(Pause) + IPG(12) + SOF(8) +
* rx-packet(1522) + delay-of-link(64)
* = 3212.
*/
#define ALX_RXQ2_RXF_FLOW_CTRL_RSVD 3212
#define ALX_DMA 0x15C0
#define ALX_DMA_RCHNL_SEL_MASK 0x3
#define ALX_DMA_RCHNL_SEL_SHIFT 26
#define ALX_DMA_WDLY_CNT_MASK 0xF
#define ALX_DMA_WDLY_CNT_SHIFT 16
#define ALX_DMA_WDLY_CNT_DEF 4
#define ALX_DMA_RDLY_CNT_MASK 0x1F
#define ALX_DMA_RDLY_CNT_SHIFT 11
#define ALX_DMA_RDLY_CNT_DEF 15
/* bit10: 0:tpd with pri, 1: data */
#define ALX_DMA_RREQ_PRI_DATA BIT(10)
#define ALX_DMA_RREQ_BLEN_MASK 0x7
#define ALX_DMA_RREQ_BLEN_SHIFT 4
#define ALX_DMA_RORDER_MODE_MASK 0x7
#define ALX_DMA_RORDER_MODE_SHIFT 0
#define ALX_DMA_RORDER_MODE_OUT 4
#define ALX_WOL0 0x14A0
#define ALX_WOL0_PME_LINK BIT(5)
#define ALX_WOL0_LINK_EN BIT(4)
#define ALX_WOL0_PME_MAGIC_EN BIT(3)
#define ALX_WOL0_MAGIC_EN BIT(2)
#define ALX_RFD_PIDX 0x15E0
#define ALX_RFD_CIDX 0x15F8
/* MIB */
#define ALX_MIB_BASE 0x1700
#define ALX_MIB_RX_OK (ALX_MIB_BASE + 0)
#define ALX_MIB_RX_ERRADDR (ALX_MIB_BASE + 92)
#define ALX_MIB_TX_OK (ALX_MIB_BASE + 96)
#define ALX_MIB_TX_MCCNT (ALX_MIB_BASE + 192)
#define ALX_RX_STATS_BIN ALX_MIB_RX_OK
#define ALX_RX_STATS_END ALX_MIB_RX_ERRADDR
#define ALX_TX_STATS_BIN ALX_MIB_TX_OK
#define ALX_TX_STATS_END ALX_MIB_TX_MCCNT
#define ALX_ISR 0x1600
#define ALX_ISR_DIS BIT(31)
#define ALX_ISR_RX_Q7 BIT(30)
#define ALX_ISR_RX_Q6 BIT(29)
#define ALX_ISR_RX_Q5 BIT(28)
#define ALX_ISR_RX_Q4 BIT(27)
#define ALX_ISR_PCIE_LNKDOWN BIT(26)
#define ALX_ISR_RX_Q3 BIT(19)
#define ALX_ISR_RX_Q2 BIT(18)
#define ALX_ISR_RX_Q1 BIT(17)
#define ALX_ISR_RX_Q0 BIT(16)
#define ALX_ISR_TX_Q0 BIT(15)
#define ALX_ISR_PHY BIT(12)
#define ALX_ISR_DMAW BIT(10)
#define ALX_ISR_DMAR BIT(9)
#define ALX_ISR_TXF_UR BIT(8)
#define ALX_ISR_TX_Q3 BIT(7)
#define ALX_ISR_TX_Q2 BIT(6)
#define ALX_ISR_TX_Q1 BIT(5)
#define ALX_ISR_RFD_UR BIT(4)
#define ALX_ISR_RXF_OV BIT(3)
#define ALX_ISR_MANU BIT(2)
#define ALX_ISR_TIMER BIT(1)
#define ALX_ISR_SMB BIT(0)
#define ALX_IMR 0x1604
/* re-send assert msg if SW no response */
#define ALX_INT_RETRIG 0x1608
/* 40ms */
#define ALX_INT_RETRIG_TO 20000
#define ALX_SMB_TIMER 0x15C4
#define ALX_TINT_TPD_THRSHLD 0x15C8
#define ALX_TINT_TIMER 0x15CC
#define ALX_CLK_GATE 0x1814
#define ALX_CLK_GATE_RXMAC BIT(5)
#define ALX_CLK_GATE_TXMAC BIT(4)
#define ALX_CLK_GATE_RXQ BIT(3)
#define ALX_CLK_GATE_TXQ BIT(2)
#define ALX_CLK_GATE_DMAR BIT(1)
#define ALX_CLK_GATE_DMAW BIT(0)
#define ALX_CLK_GATE_ALL (ALX_CLK_GATE_RXMAC | \
ALX_CLK_GATE_TXMAC | \
ALX_CLK_GATE_RXQ | \
ALX_CLK_GATE_TXQ | \
ALX_CLK_GATE_DMAR | \
ALX_CLK_GATE_DMAW)
/* interop between drivers */
#define ALX_DRV 0x1804
#define ALX_DRV_PHY_AUTO BIT(28)
#define ALX_DRV_PHY_1000 BIT(27)
#define ALX_DRV_PHY_100 BIT(26)
#define ALX_DRV_PHY_10 BIT(25)
#define ALX_DRV_PHY_DUPLEX BIT(24)
/* bit23: adv Pause */
#define ALX_DRV_PHY_PAUSE BIT(23)
/* bit22: adv Asym Pause */
#define ALX_DRV_PHY_MASK 0xFF
#define ALX_DRV_PHY_SHIFT 21
#define ALX_DRV_PHY_UNKNOWN 0
/* flag of phy inited */
#define ALX_PHY_INITED 0x003F
/* reg 1830 ~ 186C for C0+, 16 bit map patterns and wake packet detection */
#define ALX_WOL_CTRL2 0x1830
#define ALX_WOL_CTRL2_DATA_STORE BIT(3)
#define ALX_WOL_CTRL2_PTRN_EVT BIT(2)
#define ALX_WOL_CTRL2_PME_PTRN_EN BIT(1)
#define ALX_WOL_CTRL2_PTRN_EN BIT(0)
#define ALX_WOL_CTRL3 0x1834
#define ALX_WOL_CTRL3_PTRN_ADDR_MASK 0xFFFFF
#define ALX_WOL_CTRL3_PTRN_ADDR_SHIFT 0
#define ALX_WOL_CTRL4 0x1838
#define ALX_WOL_CTRL4_PT15_MATCH BIT(31)
#define ALX_WOL_CTRL4_PT14_MATCH BIT(30)
#define ALX_WOL_CTRL4_PT13_MATCH BIT(29)
#define ALX_WOL_CTRL4_PT12_MATCH BIT(28)
#define ALX_WOL_CTRL4_PT11_MATCH BIT(27)
#define ALX_WOL_CTRL4_PT10_MATCH BIT(26)
#define ALX_WOL_CTRL4_PT9_MATCH BIT(25)
#define ALX_WOL_CTRL4_PT8_MATCH BIT(24)
#define ALX_WOL_CTRL4_PT7_MATCH BIT(23)
#define ALX_WOL_CTRL4_PT6_MATCH BIT(22)
#define ALX_WOL_CTRL4_PT5_MATCH BIT(21)
#define ALX_WOL_CTRL4_PT4_MATCH BIT(20)
#define ALX_WOL_CTRL4_PT3_MATCH BIT(19)
#define ALX_WOL_CTRL4_PT2_MATCH BIT(18)
#define ALX_WOL_CTRL4_PT1_MATCH BIT(17)
#define ALX_WOL_CTRL4_PT0_MATCH BIT(16)
#define ALX_WOL_CTRL4_PT15_EN BIT(15)
#define ALX_WOL_CTRL4_PT14_EN BIT(14)
#define ALX_WOL_CTRL4_PT13_EN BIT(13)
#define ALX_WOL_CTRL4_PT12_EN BIT(12)
#define ALX_WOL_CTRL4_PT11_EN BIT(11)
#define ALX_WOL_CTRL4_PT10_EN BIT(10)
#define ALX_WOL_CTRL4_PT9_EN BIT(9)
#define ALX_WOL_CTRL4_PT8_EN BIT(8)
#define ALX_WOL_CTRL4_PT7_EN BIT(7)
#define ALX_WOL_CTRL4_PT6_EN BIT(6)
#define ALX_WOL_CTRL4_PT5_EN BIT(5)
#define ALX_WOL_CTRL4_PT4_EN BIT(4)
#define ALX_WOL_CTRL4_PT3_EN BIT(3)
#define ALX_WOL_CTRL4_PT2_EN BIT(2)
#define ALX_WOL_CTRL4_PT1_EN BIT(1)
#define ALX_WOL_CTRL4_PT0_EN BIT(0)
#define ALX_WOL_CTRL5 0x183C
#define ALX_WOL_CTRL5_PT3_LEN_MASK 0xFF
#define ALX_WOL_CTRL5_PT3_LEN_SHIFT 24
#define ALX_WOL_CTRL5_PT2_LEN_MASK 0xFF
#define ALX_WOL_CTRL5_PT2_LEN_SHIFT 16
#define ALX_WOL_CTRL5_PT1_LEN_MASK 0xFF
#define ALX_WOL_CTRL5_PT1_LEN_SHIFT 8
#define ALX_WOL_CTRL5_PT0_LEN_MASK 0xFF
#define ALX_WOL_CTRL5_PT0_LEN_SHIFT 0
#define ALX_WOL_CTRL6 0x1840
#define ALX_WOL_CTRL5_PT7_LEN_MASK 0xFF
#define ALX_WOL_CTRL5_PT7_LEN_SHIFT 24
#define ALX_WOL_CTRL5_PT6_LEN_MASK 0xFF
#define ALX_WOL_CTRL5_PT6_LEN_SHIFT 16
#define ALX_WOL_CTRL5_PT5_LEN_MASK 0xFF
#define ALX_WOL_CTRL5_PT5_LEN_SHIFT 8
#define ALX_WOL_CTRL5_PT4_LEN_MASK 0xFF
#define ALX_WOL_CTRL5_PT4_LEN_SHIFT 0
#define ALX_WOL_CTRL7 0x1844
#define ALX_WOL_CTRL5_PT11_LEN_MASK 0xFF
#define ALX_WOL_CTRL5_PT11_LEN_SHIFT 24
#define ALX_WOL_CTRL5_PT10_LEN_MASK 0xFF
#define ALX_WOL_CTRL5_PT10_LEN_SHIFT 16
#define ALX_WOL_CTRL5_PT9_LEN_MASK 0xFF
#define ALX_WOL_CTRL5_PT9_LEN_SHIFT 8
#define ALX_WOL_CTRL5_PT8_LEN_MASK 0xFF
#define ALX_WOL_CTRL5_PT8_LEN_SHIFT 0
#define ALX_WOL_CTRL8 0x1848
#define ALX_WOL_CTRL5_PT15_LEN_MASK 0xFF
#define ALX_WOL_CTRL5_PT15_LEN_SHIFT 24
#define ALX_WOL_CTRL5_PT14_LEN_MASK 0xFF
#define ALX_WOL_CTRL5_PT14_LEN_SHIFT 16
#define ALX_WOL_CTRL5_PT13_LEN_MASK 0xFF
#define ALX_WOL_CTRL5_PT13_LEN_SHIFT 8
#define ALX_WOL_CTRL5_PT12_LEN_MASK 0xFF
#define ALX_WOL_CTRL5_PT12_LEN_SHIFT 0
#define ALX_ACER_FIXED_PTN0 0x1850
#define ALX_ACER_FIXED_PTN0_MASK 0xFFFFFFFF
#define ALX_ACER_FIXED_PTN0_SHIFT 0
#define ALX_ACER_FIXED_PTN1 0x1854
#define ALX_ACER_FIXED_PTN1_MASK 0xFFFF
#define ALX_ACER_FIXED_PTN1_SHIFT 0
#define ALX_ACER_RANDOM_NUM0 0x1858
#define ALX_ACER_RANDOM_NUM0_MASK 0xFFFFFFFF
#define ALX_ACER_RANDOM_NUM0_SHIFT 0
#define ALX_ACER_RANDOM_NUM1 0x185C
#define ALX_ACER_RANDOM_NUM1_MASK 0xFFFFFFFF
#define ALX_ACER_RANDOM_NUM1_SHIFT 0
#define ALX_ACER_RANDOM_NUM2 0x1860
#define ALX_ACER_RANDOM_NUM2_MASK 0xFFFFFFFF
#define ALX_ACER_RANDOM_NUM2_SHIFT 0
#define ALX_ACER_RANDOM_NUM3 0x1864
#define ALX_ACER_RANDOM_NUM3_MASK 0xFFFFFFFF
#define ALX_ACER_RANDOM_NUM3_SHIFT 0
#define ALX_ACER_MAGIC 0x1868
#define ALX_ACER_MAGIC_EN BIT(31)
#define ALX_ACER_MAGIC_PME_EN BIT(30)
#define ALX_ACER_MAGIC_MATCH BIT(29)
#define ALX_ACER_MAGIC_FF_CHECK BIT(10)
#define ALX_ACER_MAGIC_RAN_LEN_MASK 0x1F
#define ALX_ACER_MAGIC_RAN_LEN_SHIFT 5
#define ALX_ACER_MAGIC_FIX_LEN_MASK 0x1F
#define ALX_ACER_MAGIC_FIX_LEN_SHIFT 0
#define ALX_ACER_TIMER 0x186C
#define ALX_ACER_TIMER_EN BIT(31)
#define ALX_ACER_TIMER_PME_EN BIT(30)
#define ALX_ACER_TIMER_MATCH BIT(29)
#define ALX_ACER_TIMER_THRES_MASK 0x1FFFF
#define ALX_ACER_TIMER_THRES_SHIFT 0
#define ALX_ACER_TIMER_THRES_DEF 1
/* RSS definitions */
#define ALX_RSS_KEY0 0x14B0
#define ALX_RSS_KEY1 0x14B4
#define ALX_RSS_KEY2 0x14B8
#define ALX_RSS_KEY3 0x14BC
#define ALX_RSS_KEY4 0x14C0
#define ALX_RSS_KEY5 0x14C4
#define ALX_RSS_KEY6 0x14C8
#define ALX_RSS_KEY7 0x14CC
#define ALX_RSS_KEY8 0x14D0
#define ALX_RSS_KEY9 0x14D4
#define ALX_RSS_IDT_TBL0 0x1B00
#define ALX_MSI_MAP_TBL1 0x15D0
#define ALX_MSI_MAP_TBL1_TXQ1_SHIFT 20
#define ALX_MSI_MAP_TBL1_TXQ0_SHIFT 16
#define ALX_MSI_MAP_TBL1_RXQ3_SHIFT 12
#define ALX_MSI_MAP_TBL1_RXQ2_SHIFT 8
#define ALX_MSI_MAP_TBL1_RXQ1_SHIFT 4
#define ALX_MSI_MAP_TBL1_RXQ0_SHIFT 0
#define ALX_MSI_MAP_TBL2 0x15D8
#define ALX_MSI_MAP_TBL2_TXQ3_SHIFT 20
#define ALX_MSI_MAP_TBL2_TXQ2_SHIFT 16
#define ALX_MSI_MAP_TBL2_RXQ7_SHIFT 12
#define ALX_MSI_MAP_TBL2_RXQ6_SHIFT 8
#define ALX_MSI_MAP_TBL2_RXQ5_SHIFT 4
#define ALX_MSI_MAP_TBL2_RXQ4_SHIFT 0
#define ALX_MSI_ID_MAP 0x15D4
#define ALX_MSI_RETRANS_TIMER 0x1920
/* bit16: 1:line,0:standard */
#define ALX_MSI_MASK_SEL_LINE BIT(16)
#define ALX_MSI_RETRANS_TM_MASK 0xFFFF
#define ALX_MSI_RETRANS_TM_SHIFT 0
/* CR DMA ctrl */
/* TX QoS */
#define ALX_WRR 0x1938
#define ALX_WRR_PRI_MASK 0x3
#define ALX_WRR_PRI_SHIFT 29
#define ALX_WRR_PRI_RESTRICT_NONE 3
#define ALX_WRR_PRI3_MASK 0x1F
#define ALX_WRR_PRI3_SHIFT 24
#define ALX_WRR_PRI2_MASK 0x1F
#define ALX_WRR_PRI2_SHIFT 16
#define ALX_WRR_PRI1_MASK 0x1F
#define ALX_WRR_PRI1_SHIFT 8
#define ALX_WRR_PRI0_MASK 0x1F
#define ALX_WRR_PRI0_SHIFT 0
#define ALX_HQTPD 0x193C
#define ALX_HQTPD_BURST_EN BIT(31)
#define ALX_HQTPD_Q3_NUMPREF_MASK 0xF
#define ALX_HQTPD_Q3_NUMPREF_SHIFT 8
#define ALX_HQTPD_Q2_NUMPREF_MASK 0xF
#define ALX_HQTPD_Q2_NUMPREF_SHIFT 4
#define ALX_HQTPD_Q1_NUMPREF_MASK 0xF
#define ALX_HQTPD_Q1_NUMPREF_SHIFT 0
#define ALX_MISC 0x19C0
#define ALX_MISC_PSW_OCP_MASK 0x7
#define ALX_MISC_PSW_OCP_SHIFT 21
#define ALX_MISC_PSW_OCP_DEF 0x7
#define ALX_MISC_ISO_EN BIT(12)
#define ALX_MISC_INTNLOSC_OPEN BIT(3)
#define ALX_MSIC2 0x19C8
#define ALX_MSIC2_CALB_START BIT(0)
#define ALX_MISC3 0x19CC
/* bit1: 1:Software control 25M */
#define ALX_MISC3_25M_BY_SW BIT(1)
/* bit0: 25M switch to intnl OSC */
#define ALX_MISC3_25M_NOTO_INTNL BIT(0)
/* MSIX tbl in memory space */
#define ALX_MSIX_ENTRY_BASE 0x2000
/********************* PHY regs definition ***************************/
/* PHY Specific Status Register */
#define ALX_MII_GIGA_PSSR 0x11
#define ALX_GIGA_PSSR_SPD_DPLX_RESOLVED 0x0800
#define ALX_GIGA_PSSR_DPLX 0x2000
#define ALX_GIGA_PSSR_SPEED 0xC000
#define ALX_GIGA_PSSR_10MBS 0x0000
#define ALX_GIGA_PSSR_100MBS 0x4000
#define ALX_GIGA_PSSR_1000MBS 0x8000
/* PHY Interrupt Enable Register */
#define ALX_MII_IER 0x12
#define ALX_IER_LINK_UP 0x0400
#define ALX_IER_LINK_DOWN 0x0800
/* PHY Interrupt Status Register */
#define ALX_MII_ISR 0x13
#define ALX_MII_DBG_ADDR 0x1D
#define ALX_MII_DBG_DATA 0x1E
/***************************** debug port *************************************/
#define ALX_MIIDBG_ANACTRL 0x00
#define ALX_ANACTRL_DEF 0x02EF
#define ALX_MIIDBG_SYSMODCTRL 0x04
/* en half bias */
#define ALX_SYSMODCTRL_IECHOADJ_DEF 0xBB8B
#define ALX_MIIDBG_SRDSYSMOD 0x05
#define ALX_SRDSYSMOD_DEEMP_EN 0x0040
#define ALX_SRDSYSMOD_DEF 0x2C46
#define ALX_MIIDBG_HIBNEG 0x0B
#define ALX_HIBNEG_PSHIB_EN 0x8000
#define ALX_HIBNEG_HIB_PSE 0x1000
#define ALX_HIBNEG_DEF 0xBC40
#define ALX_HIBNEG_NOHIB (ALX_HIBNEG_DEF & \
~(ALX_HIBNEG_PSHIB_EN | ALX_HIBNEG_HIB_PSE))
#define ALX_MIIDBG_TST10BTCFG 0x12
#define ALX_TST10BTCFG_DEF 0x4C04
#define ALX_MIIDBG_AZ_ANADECT 0x15
#define ALX_AZ_ANADECT_DEF 0x3220
#define ALX_AZ_ANADECT_LONG 0x3210
#define ALX_MIIDBG_MSE16DB 0x18
#define ALX_MSE16DB_UP 0x05EA
#define ALX_MSE16DB_DOWN 0x02EA
#define ALX_MIIDBG_MSE20DB 0x1C
#define ALX_MSE20DB_TH_MASK 0x7F
#define ALX_MSE20DB_TH_SHIFT 2
#define ALX_MSE20DB_TH_DEF 0x2E
#define ALX_MSE20DB_TH_HI 0x54
#define ALX_MIIDBG_AGC 0x23
#define ALX_AGC_2_VGA_MASK 0x3FU
#define ALX_AGC_2_VGA_SHIFT 8
#define ALX_AGC_LONG1G_LIMT 40
#define ALX_AGC_LONG100M_LIMT 44
#define ALX_MIIDBG_LEGCYPS 0x29
#define ALX_LEGCYPS_EN 0x8000
#define ALX_LEGCYPS_DEF 0x129D
#define ALX_MIIDBG_TST100BTCFG 0x36
#define ALX_TST100BTCFG_DEF 0xE12C
#define ALX_MIIDBG_GREENCFG 0x3B
#define ALX_GREENCFG_DEF 0x7078
#define ALX_MIIDBG_GREENCFG2 0x3D
#define ALX_GREENCFG2_BP_GREEN 0x8000
#define ALX_GREENCFG2_GATE_DFSE_EN 0x0080
/******* dev 3 *********/
#define ALX_MIIEXT_PCS 3
#define ALX_MIIEXT_CLDCTRL3 0x8003
#define ALX_CLDCTRL3_BP_CABLE1TH_DET_GT 0x8000
#define ALX_MIIEXT_CLDCTRL5 0x8005
#define ALX_CLDCTRL5_BP_VD_HLFBIAS 0x4000
#define ALX_MIIEXT_CLDCTRL6 0x8006
#define ALX_CLDCTRL6_CAB_LEN_MASK 0xFF
#define ALX_CLDCTRL6_CAB_LEN_SHIFT 0
#define ALX_CLDCTRL6_CAB_LEN_SHORT1G 116
#define ALX_CLDCTRL6_CAB_LEN_SHORT100M 152
#define ALX_MIIEXT_VDRVBIAS 0x8062
#define ALX_VDRVBIAS_DEF 0x3
/********* dev 7 **********/
#define ALX_MIIEXT_ANEG 7
#define ALX_MIIEXT_LOCAL_EEEADV 0x3C
#define ALX_LOCAL_EEEADV_1000BT 0x0004
#define ALX_LOCAL_EEEADV_100BT 0x0002
#define ALX_MIIEXT_AFE 0x801A
#define ALX_AFE_10BT_100M_TH 0x0040
#define ALX_MIIEXT_S3DIG10 0x8023
/* bit0: 1:bypass 10BT rx fifo, 0:original 10BT rx */
#define ALX_MIIEXT_S3DIG10_SL 0x0001
#define ALX_MIIEXT_S3DIG10_DEF 0
#define ALX_MIIEXT_NLP78 0x8027
#define ALX_MIIEXT_NLP78_120M_DEF 0x8A05
#endif