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Merge branch 'drm-nouveau-next' of git://anongit.freedesktop.org/git/nouveau/linux-2.6 into drm-core-next

Browse Source 
* 'drm-nouveau-next' of git://anongit.freedesktop.org/git/nouveau/linux-2.6: (57 commits)
  drm/nouveau: map first page of mmio early and determine chipset earlier
  drm/nvd0/disp: disconnect encoders before reprogramming them
  drm/nvd0/disp: move syncs/magic setup to or mode_set
  drm/nouveau/dp: account for channel coding overhead in link training
  drm/nvd0/disp: fix dcb sor link matching in supervisor handler
  drm/nvd0/disp: initial implementation of displayport
  drm/nouveau/dp: make dp dpms function common, call from sor code instead
  drm/nv50/hwsq: some nv92 fixes
  drm/nouveau/dp: move all nv50/sor-specific code out of nouveau_dp.c
  drm/nouveau/dp: make functions for executing various bios tables
  drm/nouveau/pm: fix oops if chipset has no pm support at all
  drm/nouveau/bios: rework vbios shadowing
  drm/nouveau/bios: attempt acpi rom fetch before pcirom
  drm/nvd0/disp: attempt to handle more than 2 crtcs if possible
  drm/nvc0/vram: get part count from PUNITS
  drm/nv40/pm: fix fanspeed regression
  drm/nouveau/pm: several fixes for nvc0 memory timings
  drm/nvc0/pm: restrict pll mode to clocks that can actually use it
  drm/nouveau/dp: fix bad comparison in dp_link_train_commit()
  drm/nouveau/mxm: call mxmi to determine revision before calling mxms
  ...
This commit is contained in:
Dave Airlie 2012-03-13 10:16:06 +00:00
commit abd32008ff
32 changed files with 2698 additions and 1353 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
drivers/gpu/drm/nouveau/Makefile
View File

@ -14,7 +14,8 @@ nouveau-y := nouveau_drv.o nouveau_state.o nouveau_channel.o nouveau_mem.o \
nouveau_mm.o nouveau_vm.o nouveau_mxm.o nouveau_gpio.o \
nv04_timer.o \
nv04_mc.o nv40_mc.o nv50_mc.o \
nv04_fb.o nv10_fb.o nv30_fb.o nv40_fb.o nv50_fb.o nvc0_fb.o \
nv04_fb.o nv10_fb.o nv20_fb.o nv30_fb.o nv40_fb.o \
nv50_fb.o nvc0_fb.o \
nv04_fifo.o nv10_fifo.o nv40_fifo.o nv50_fifo.o nvc0_fifo.o \
nv04_graph.o nv10_graph.o nv20_graph.o \
nv40_graph.o nv50_graph.o nvc0_graph.o \

281
drivers/gpu/drm/nouveau/nouveau_bios.c
View File

@ -65,195 +65,232 @@ static bool nv_cksum(const uint8_t *data, unsigned int length)
}
static int
score_vbios(struct drm_device *dev, const uint8_t *data, const bool writeable)
score_vbios(struct nvbios *bios, const bool writeable)
{
if (!(data[0] == 0x55 && data[1] == 0xAA)) {
NV_TRACEWARN(dev, "... BIOS signature not found\n");
if (!bios->data || bios->data[0] != 0x55 || bios->data[1] != 0xAA) {
NV_TRACEWARN(bios->dev, "... BIOS signature not found\n");
return 0;
}
if (nv_cksum(data, data[2] * 512)) {
NV_TRACEWARN(dev, "... BIOS checksum invalid\n");
if (nv_cksum(bios->data, bios->data[2] * 512)) {
NV_TRACEWARN(bios->dev, "... BIOS checksum invalid\n");
/* if a ro image is somewhat bad, it's probably all rubbish */
return writeable ? 2 : 1;
} else
NV_TRACE(dev, "... appears to be valid\n");
}
NV_TRACE(bios->dev, "... appears to be valid\n");
return 3;
}
static void load_vbios_prom(struct drm_device *dev, uint8_t *data)
static void
bios_shadow_prom(struct nvbios *bios)
{
struct drm_device *dev = bios->dev;
struct drm_nouveau_private *dev_priv = dev->dev_private;
uint32_t pci_nv_20, save_pci_nv_20;
int pcir_ptr;
u32 pcireg, access;
u16 pcir;
int i;
/* enable access to rom */
if (dev_priv->card_type >= NV_50)
pci_nv_20 = 0x88050;
pcireg = 0x088050;
else
pci_nv_20 = NV_PBUS_PCI_NV_20;
pcireg = NV_PBUS_PCI_NV_20;
access = nv_mask(dev, pcireg, 0x00000001, 0x00000000);
/* enable ROM access */
save_pci_nv_20 = nvReadMC(dev, pci_nv_20);
nvWriteMC(dev, pci_nv_20,
save_pci_nv_20 & ~NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED);
/* bail if no rom signature, with a workaround for a PROM reading
* issue on some chipsets. the first read after a period of
* inactivity returns the wrong result, so retry the first header
* byte a few times before giving up as a workaround
*/
i = 16;
do {
if (nv_rd08(dev, NV_PROM_OFFSET + 0) == 0x55)
break;
} while (i--);
/* bail if no rom signature */
if (nv_rd08(dev, NV_PROM_OFFSET) != 0x55 ||
nv_rd08(dev, NV_PROM_OFFSET + 1) != 0xaa)
if (!i || nv_rd08(dev, NV_PROM_OFFSET + 1) != 0xaa)
goto out;
/* additional check (see note below) - read PCI record header */
pcir_ptr = nv_rd08(dev, NV_PROM_OFFSET + 0x18) |
nv_rd08(dev, NV_PROM_OFFSET + 0x19) << 8;
if (nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr) != 'P' ||
nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr + 1) != 'C' ||
nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr + 2) != 'I' ||
nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr + 3) != 'R')
pcir = nv_rd08(dev, NV_PROM_OFFSET + 0x18) |
nv_rd08(dev, NV_PROM_OFFSET + 0x19) << 8;
if (nv_rd08(dev, NV_PROM_OFFSET + pcir + 0) != 'P' ||
nv_rd08(dev, NV_PROM_OFFSET + pcir + 1) != 'C' ||
nv_rd08(dev, NV_PROM_OFFSET + pcir + 2) != 'I' ||
nv_rd08(dev, NV_PROM_OFFSET + pcir + 3) != 'R')
goto out;
/* on some 6600GT/6800LE prom reads are messed up. nvclock alleges a
* a good read may be obtained by waiting or re-reading (cargocult: 5x)
* each byte. we'll hope pramin has something usable instead
*/
for (i = 0; i < NV_PROM_SIZE; i++)
data[i] = nv_rd08(dev, NV_PROM_OFFSET + i);
/* read entire bios image to system memory */
bios->length = nv_rd08(dev, NV_PROM_OFFSET + 2) * 512;
bios->data = kmalloc(bios->length, GFP_KERNEL);
if (bios->data) {
for (i = 0; i < bios->length; i++)
bios->data[i] = nv_rd08(dev, NV_PROM_OFFSET + i);
}
out:
/* disable ROM access */
nvWriteMC(dev, pci_nv_20,
save_pci_nv_20 | NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED);
/* disable access to rom */
nv_wr32(dev, pcireg, access);
}
static void load_vbios_pramin(struct drm_device *dev, uint8_t *data)
static void
bios_shadow_pramin(struct nvbios *bios)
{
struct drm_device *dev = bios->dev;
struct drm_nouveau_private *dev_priv = dev->dev_private;
uint32_t old_bar0_pramin = 0;
u32 bar0 = 0;
int i;
if (dev_priv->card_type >= NV_50) {
u64 addr = (u64)(nv_rd32(dev, 0x619f04) & 0xffffff00) << 8;
if (!addr) {
addr = (u64)nv_rd32(dev, 0x1700) << 16;
addr = (u64)nv_rd32(dev, 0x001700) << 16;
addr += 0xf0000;
}
old_bar0_pramin = nv_rd32(dev, 0x1700);
nv_wr32(dev, 0x1700, addr >> 16);
bar0 = nv_mask(dev, 0x001700, 0xffffffff, addr >> 16);
}
/* bail if no rom signature */
if (nv_rd08(dev, NV_PRAMIN_OFFSET) != 0x55 ||
if (nv_rd08(dev, NV_PRAMIN_OFFSET + 0) != 0x55 ||
nv_rd08(dev, NV_PRAMIN_OFFSET + 1) != 0xaa)
goto out;
for (i = 0; i < NV_PROM_SIZE; i++)
data[i] = nv_rd08(dev, NV_PRAMIN_OFFSET + i);
bios->length = nv_rd08(dev, NV_PRAMIN_OFFSET + 2) * 512;
bios->data = kmalloc(bios->length, GFP_KERNEL);
if (bios->data) {
for (i = 0; i < bios->length; i++)
bios->data[i] = nv_rd08(dev, NV_PRAMIN_OFFSET + i);
}
out:
if (dev_priv->card_type >= NV_50)
nv_wr32(dev, 0x1700, old_bar0_pramin);
nv_wr32(dev, 0x001700, bar0);
}
static void load_vbios_pci(struct drm_device *dev, uint8_t *data)
static void
bios_shadow_pci(struct nvbios *bios)
{
void __iomem *rom = NULL;
size_t rom_len;
int ret;
struct pci_dev *pdev = bios->dev->pdev;
size_t length;
ret = pci_enable_rom(dev->pdev);
if (ret)
return;
if (!pci_enable_rom(pdev)) {
void __iomem *rom = pci_map_rom(pdev, &length);
if (rom) {
bios->data = kmalloc(length, GFP_KERNEL);
if (bios->data) {
memcpy_fromio(bios->data, rom, length);
bios->length = length;
}
pci_unmap_rom(pdev, rom);
}
rom = pci_map_rom(dev->pdev, &rom_len);
if (!rom)
goto out;
memcpy_fromio(data, rom, rom_len);
pci_unmap_rom(dev->pdev, rom);
out:
pci_disable_rom(dev->pdev);
}
static void load_vbios_acpi(struct drm_device *dev, uint8_t *data)
{
int i;
int ret;
int size = 64 * 1024;
if (!nouveau_acpi_rom_supported(dev->pdev))
return;
for (i = 0; i < (size / ROM_BIOS_PAGE); i++) {
ret = nouveau_acpi_get_bios_chunk(data,
(i * ROM_BIOS_PAGE),
ROM_BIOS_PAGE);
if (ret <= 0)
break;
pci_disable_rom(pdev);
}
}
static void
bios_shadow_acpi(struct nvbios *bios)
{
struct pci_dev *pdev = bios->dev->pdev;
int ptr, len, ret;
u8 data[3];
if (!nouveau_acpi_rom_supported(pdev))
return;
ret = nouveau_acpi_get_bios_chunk(data, 0, sizeof(data));
if (ret != sizeof(data))
return;
bios->length = min(data[2] * 512, 65536);
bios->data = kmalloc(bios->length, GFP_KERNEL);
if (!bios->data)
return;
len = bios->length;
ptr = 0;
while (len) {
int size = (len > ROM_BIOS_PAGE) ? ROM_BIOS_PAGE : len;
ret = nouveau_acpi_get_bios_chunk(bios->data, ptr, size);
if (ret != size) {
kfree(bios->data);
bios->data = NULL;
return;
}
len -= size;
ptr += size;
}
return;
}
struct methods {
const char desc[8];
void (*loadbios)(struct drm_device *, uint8_t *);
void (*shadow)(struct nvbios *);
const bool rw;
int score;
u32 size;
u8 *data;
};
static struct methods shadow_methods[] = {
{ "PRAMIN", load_vbios_pramin, true },
{ "PROM", load_vbios_prom, false },
{ "PCIROM", load_vbios_pci, true },
{ "ACPI", load_vbios_acpi, true },
};
#define NUM_SHADOW_METHODS ARRAY_SIZE(shadow_methods)
static bool NVShadowVBIOS(struct drm_device *dev, uint8_t *data)
static bool
bios_shadow(struct drm_device *dev)
{
struct methods *methods = shadow_methods;
int testscore = 3;
int scores[NUM_SHADOW_METHODS], i;
struct methods shadow_methods[] = {
{ "PRAMIN", bios_shadow_pramin, true, 0, 0, NULL },
{ "PROM", bios_shadow_prom, false, 0, 0, NULL },
{ "ACPI", bios_shadow_acpi, true, 0, 0, NULL },
{ "PCIROM", bios_shadow_pci, true, 0, 0, NULL },
{}
};
struct drm_nouveau_private *dev_priv = dev->dev_private;
struct nvbios *bios = &dev_priv->vbios;
struct methods *mthd, *best;
if (nouveau_vbios) {
for (i = 0; i < NUM_SHADOW_METHODS; i++)
if (!strcasecmp(nouveau_vbios, methods[i].desc))
break;
mthd = shadow_methods;
do {
if (strcasecmp(nouveau_vbios, mthd->desc))
continue;
NV_INFO(dev, "VBIOS source: %s\n", mthd->desc);
if (i < NUM_SHADOW_METHODS) {
NV_INFO(dev, "Attempting to use BIOS image from %s\n",
methods[i].desc);
methods[i].loadbios(dev, data);
if (score_vbios(dev, data, methods[i].rw))
mthd->shadow(bios);
mthd->score = score_vbios(bios, mthd->rw);
if (mthd->score)
return true;
}
} while ((++mthd)->shadow);
NV_ERROR(dev, "VBIOS source \'%s\' invalid\n", nouveau_vbios);
}
for (i = 0; i < NUM_SHADOW_METHODS; i++) {
NV_TRACE(dev, "Attempting to load BIOS image from %s\n",
methods[i].desc);
data[0] = data[1] = 0; /* avoid reuse of previous image */
methods[i].loadbios(dev, data);
scores[i] = score_vbios(dev, data, methods[i].rw);
if (scores[i] == testscore)
return true;
}
mthd = shadow_methods;
do {
NV_TRACE(dev, "Checking %s for VBIOS\n", mthd->desc);
mthd->shadow(bios);
mthd->score = score_vbios(bios, mthd->rw);
mthd->size = bios->length;
mthd->data = bios->data;
} while (mthd->score != 3 && (++mthd)->shadow);
while (--testscore > 0) {
for (i = 0; i < NUM_SHADOW_METHODS; i++) {
if (scores[i] == testscore) {
NV_TRACE(dev, "Using BIOS image from %s\n",
methods[i].desc);
methods[i].loadbios(dev, data);
return true;
}
mthd = shadow_methods;
best = mthd;
do {
if (mthd->score > best->score) {
kfree(best->data);
best = mthd;
}
} while ((++mthd)->shadow);
if (best->score) {
NV_TRACE(dev, "Using VBIOS from %s\n", best->desc);
bios->length = best->size;
bios->data = best->data;
return true;
}
NV_ERROR(dev, "No valid BIOS image found\n");
NV_ERROR(dev, "No valid VBIOS image found\n");
return false;
}
@ -6334,11 +6371,7 @@ static bool NVInitVBIOS(struct drm_device *dev)
spin_lock_init(&bios->lock);
bios->dev = dev;
if (!NVShadowVBIOS(dev, bios->data))
return false;
bios->length = NV_PROM_SIZE;
return true;
return bios_shadow(dev);
}
static int nouveau_parse_vbios_struct(struct drm_device *dev)
@ -6498,6 +6531,10 @@ nouveau_bios_init(struct drm_device *dev)
void
nouveau_bios_takedown(struct drm_device *dev)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
nouveau_mxm_fini(dev);
nouveau_i2c_fini(dev);
kfree(dev_priv->vbios.data);
}

6
drivers/gpu/drm/nouveau/nouveau_bios.h
View File

@ -75,6 +75,8 @@ enum dcb_connector_type {
DCB_CONNECTOR_eDP = 0x47,
DCB_CONNECTOR_HDMI_0 = 0x60,
DCB_CONNECTOR_HDMI_1 = 0x61,
DCB_CONNECTOR_DMS59_DP0 = 0x64,
DCB_CONNECTOR_DMS59_DP1 = 0x65,
DCB_CONNECTOR_NONE = 0xff
};
@ -209,6 +211,8 @@ struct nvbios {
NVBIOS_BIT
} type;
uint16_t offset;
uint32_t length;
uint8_t *data;
uint8_t chip_version;
@ -219,8 +223,6 @@ struct nvbios {
spinlock_t lock;
uint8_t data[NV_PROM_SIZE];
unsigned int length;
bool execute;
uint8_t major_version;

29
drivers/gpu/drm/nouveau/nouveau_connector.c
View File

@ -519,6 +519,19 @@ nouveau_connector_set_property(struct drm_connector *connector,
return nv_crtc->set_dither(nv_crtc, true);
}
if (nv_crtc && nv_crtc->set_color_vibrance) {
/* Hue */
if (property == disp->vibrant_hue_property) {
nv_crtc->vibrant_hue = value - 90;
return nv_crtc->set_color_vibrance(nv_crtc, true);
}
/* Saturation */
if (property == disp->color_vibrance_property) {
nv_crtc->color_vibrance = value - 100;
return nv_crtc->set_color_vibrance(nv_crtc, true);
}
}
if (nv_encoder && nv_encoder->dcb->type == OUTPUT_TV)
return get_slave_funcs(encoder)->set_property(
encoder, connector, property, value);
@ -858,6 +871,8 @@ drm_conntype_from_dcb(enum dcb_connector_type dcb)
case DCB_CONNECTOR_DVI_D : return DRM_MODE_CONNECTOR_DVID;
case DCB_CONNECTOR_LVDS :
case DCB_CONNECTOR_LVDS_SPWG: return DRM_MODE_CONNECTOR_LVDS;
case DCB_CONNECTOR_DMS59_DP0:
case DCB_CONNECTOR_DMS59_DP1:
case DCB_CONNECTOR_DP : return DRM_MODE_CONNECTOR_DisplayPort;
case DCB_CONNECTOR_eDP : return DRM_MODE_CONNECTOR_eDP;
case DCB_CONNECTOR_HDMI_0 :
@ -1002,7 +1017,9 @@ nouveau_connector_create(struct drm_device *dev, int index)
nv_connector->type == DCB_CONNECTOR_DVI_I ||
nv_connector->type == DCB_CONNECTOR_HDMI_0 ||
nv_connector->type == DCB_CONNECTOR_HDMI_1 ||
nv_connector->type == DCB_CONNECTOR_DP)) {
nv_connector->type == DCB_CONNECTOR_DP ||
nv_connector->type == DCB_CONNECTOR_DMS59_DP0 ||
nv_connector->type == DCB_CONNECTOR_DMS59_DP1)) {
drm_connector_attach_property(connector,
disp->underscan_property,
UNDERSCAN_OFF);
@ -1014,6 +1031,16 @@ nouveau_connector_create(struct drm_device *dev, int index)
0);
}
/* Add hue and saturation options */
if (disp->vibrant_hue_property)
drm_connector_attach_property(connector,
disp->vibrant_hue_property,
90);
if (disp->color_vibrance_property)
drm_connector_attach_property(connector,
disp->color_vibrance_property,
150);
switch (nv_connector->type) {
case DCB_CONNECTOR_VGA:
if (dev_priv->card_type >= NV_50) {

3
drivers/gpu/drm/nouveau/nouveau_crtc.h
View File

@ -35,6 +35,8 @@ struct nouveau_crtc {
uint32_t dpms_saved_fp_control;
uint32_t fp_users;
int saturation;
int color_vibrance;
int vibrant_hue;
int sharpness;
int last_dpms;
@ -67,6 +69,7 @@ struct nouveau_crtc {
int (*set_dither)(struct nouveau_crtc *crtc, bool update);
int (*set_scale)(struct nouveau_crtc *crtc, bool update);
int (*set_color_vibrance)(struct nouveau_crtc *crtc, bool update);
};
static inline struct nouveau_crtc *nouveau_crtc(struct drm_crtc *crtc)

14
drivers/gpu/drm/nouveau/nouveau_display.c
View File

@ -286,6 +286,20 @@ nouveau_display_create(struct drm_device *dev)
disp->underscan_vborder_property =
drm_property_create_range(dev, 0, "underscan vborder", 0, 128);
if (gen == 1) {
disp->vibrant_hue_property =
drm_property_create(dev, DRM_MODE_PROP_RANGE,
"vibrant hue", 2);
disp->vibrant_hue_property->values[0] = 0;
disp->vibrant_hue_property->values[1] = 180; /* -90..+90 */
disp->color_vibrance_property =
drm_property_create(dev, DRM_MODE_PROP_RANGE,
"color vibrance", 2);
disp->color_vibrance_property->values[0] = 0;
disp->color_vibrance_property->values[1] = 200; /* -100..+100 */
}
dev->mode_config.funcs = (void *)&nouveau_mode_config_funcs;
dev->mode_config.fb_base = pci_resource_start(dev->pdev, 1);

318
drivers/gpu/drm/nouveau/nouveau_dp.c
View File

@ -161,116 +161,6 @@ out:
return ret;
}
static u32
dp_link_bw_get(struct drm_device *dev, int or, int link)
{
u32 ctrl = nv_rd32(dev, 0x614300 + (or * 0x800));
if (!(ctrl & 0x000c0000))
return 162000;
return 270000;
}
static int
dp_lane_count_get(struct drm_device *dev, int or, int link)
{
u32 ctrl = nv_rd32(dev, NV50_SOR_DP_CTRL(or, link));
switch (ctrl & 0x000f0000) {
case 0x00010000: return 1;
case 0x00030000: return 2;
default:
return 4;
}
}
void
nouveau_dp_tu_update(struct drm_device *dev, int or, int link, u32 clk, u32 bpp)
{
const u32 symbol = 100000;
int bestTU = 0, bestVTUi = 0, bestVTUf = 0, bestVTUa = 0;
int TU, VTUi, VTUf, VTUa;
u64 link_data_rate, link_ratio, unk;
u32 best_diff = 64 * symbol;
u32 link_nr, link_bw, r;
/* calculate packed data rate for each lane */
link_nr = dp_lane_count_get(dev, or, link);
link_data_rate = (clk * bpp / 8) / link_nr;
/* calculate ratio of packed data rate to link symbol rate */
link_bw = dp_link_bw_get(dev, or, link);
link_ratio = link_data_rate * symbol;
r = do_div(link_ratio, link_bw);
for (TU = 64; TU >= 32; TU--) {
/* calculate average number of valid symbols in each TU */
u32 tu_valid = link_ratio * TU;
u32 calc, diff;
/* find a hw representation for the fraction.. */
VTUi = tu_valid / symbol;
calc = VTUi * symbol;
diff = tu_valid - calc;
if (diff) {
if (diff >= (symbol / 2)) {
VTUf = symbol / (symbol - diff);
if (symbol - (VTUf * diff))
VTUf++;
if (VTUf <= 15) {
VTUa = 1;
calc += symbol - (symbol / VTUf);
} else {
VTUa = 0;
VTUf = 1;
calc += symbol;
}
} else {
VTUa = 0;
VTUf = min((int)(symbol / diff), 15);
calc += symbol / VTUf;
}
diff = calc - tu_valid;
} else {
/* no remainder, but the hw doesn't like the fractional
* part to be zero. decrement the integer part and
* have the fraction add a whole symbol back
*/
VTUa = 0;
VTUf = 1;
VTUi--;
}
if (diff < best_diff) {
best_diff = diff;
bestTU = TU;
bestVTUa = VTUa;
bestVTUf = VTUf;
bestVTUi = VTUi;
if (diff == 0)
break;
}
}
if (!bestTU) {
NV_ERROR(dev, "DP: unable to find suitable config\n");
return;
}
/* XXX close to vbios numbers, but not right */
unk = (symbol - link_ratio) * bestTU;
unk *= link_ratio;
r = do_div(unk, symbol);
r = do_div(unk, symbol);
unk += 6;
nv_mask(dev, NV50_SOR_DP_CTRL(or, link), 0x000001fc, bestTU << 2);
nv_mask(dev, NV50_SOR_DP_SCFG(or, link), 0x010f7f3f, bestVTUa << 24 |
bestVTUf << 16 |
bestVTUi << 8 |
unk);
}
u8 *
nouveau_dp_bios_data(struct drm_device *dev, struct dcb_entry *dcb, u8 **entry)
{
@ -318,13 +208,10 @@ nouveau_dp_bios_data(struct drm_device *dev, struct dcb_entry *dcb, u8 **entry)
* link training
*****************************************************************************/
struct dp_state {
struct dp_train_func *func;
struct dcb_entry *dcb;
u8 *table;
u8 *entry;
int auxch;
int crtc;
int or;
int link;
u8 *dpcd;
int link_nr;
u32 link_bw;
@ -335,142 +222,58 @@ struct dp_state {
static void
dp_set_link_config(struct drm_device *dev, struct dp_state *dp)
{
int or = dp->or, link = dp->link;
u8 *entry, sink[2];
u32 dp_ctrl;
u16 script;
u8 sink[2];
NV_DEBUG_KMS(dev, "%d lanes at %d KB/s\n", dp->link_nr, dp->link_bw);
/* set selected link rate on source */
switch (dp->link_bw) {
case 270000:
nv_mask(dev, 0x614300 + (or * 0x800), 0x000c0000, 0x00040000);
sink[0] = DP_LINK_BW_2_7;
break;
default:
nv_mask(dev, 0x614300 + (or * 0x800), 0x000c0000, 0x00000000);
sink[0] = DP_LINK_BW_1_62;
break;
}
/* offset +0x0a of each dp encoder table entry is a pointer to another
* table, that has (among other things) pointers to more scripts that
* need to be executed, this time depending on link speed.
*/
entry = ROMPTR(dev, dp->entry[10]);
if (entry) {
if (dp->table[0] < 0x30) {
while (dp->link_bw < (ROM16(entry[0]) * 10))
entry += 4;
script = ROM16(entry[2]);
} else {
while (dp->link_bw < (entry[0] * 27000))
entry += 3;
script = ROM16(entry[1]);
}
nouveau_bios_run_init_table(dev, script, dp->dcb, dp->crtc);
}
/* configure lane count on the source */
dp_ctrl = ((1 << dp->link_nr) - 1) << 16;
sink[1] = dp->link_nr;
if (dp->dpcd[2] & DP_ENHANCED_FRAME_CAP) {
dp_ctrl |= 0x00004000;
sink[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
}
nv_mask(dev, NV50_SOR_DP_CTRL(or, link), 0x001f4000, dp_ctrl);
/* set desired link configuration on the source */
dp->func->link_set(dev, dp->dcb, dp->crtc, dp->link_nr, dp->link_bw,
dp->dpcd[2] & DP_ENHANCED_FRAME_CAP);
/* inform the sink of the new configuration */
sink[0] = dp->link_bw / 27000;
sink[1] = dp->link_nr;
if (dp->dpcd[2] & DP_ENHANCED_FRAME_CAP)
sink[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
auxch_tx(dev, dp->auxch, 8, DP_LINK_BW_SET, sink, 2);
}
static void
dp_set_training_pattern(struct drm_device *dev, struct dp_state *dp, u8 tp)
dp_set_training_pattern(struct drm_device *dev, struct dp_state *dp, u8 pattern)
{
u8 sink_tp;
NV_DEBUG_KMS(dev, "training pattern %d\n", tp);
NV_DEBUG_KMS(dev, "training pattern %d\n", pattern);
nv_mask(dev, NV50_SOR_DP_CTRL(dp->or, dp->link), 0x0f000000, tp << 24);
dp->func->train_set(dev, dp->dcb, pattern);
auxch_tx(dev, dp->auxch, 9, DP_TRAINING_PATTERN_SET, &sink_tp, 1);
sink_tp &= ~DP_TRAINING_PATTERN_MASK;
sink_tp |= tp;
sink_tp |= pattern;
auxch_tx(dev, dp->auxch, 8, DP_TRAINING_PATTERN_SET, &sink_tp, 1);
}
static const u8 nv50_lane_map[] = { 16, 8, 0, 24 };
static const u8 nvaf_lane_map[] = { 24, 16, 8, 0 };
static int
dp_link_train_commit(struct drm_device *dev, struct dp_state *dp)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
u32 mask = 0, drv = 0, pre = 0, unk = 0;
const u8 *shifts;
int link = dp->link;
int or = dp->or;
int i;
if (dev_priv->chipset != 0xaf)
shifts = nv50_lane_map;
else
shifts = nvaf_lane_map;
for (i = 0; i < dp->link_nr; i++) {
u8 *conf = dp->entry + dp->table[4];
u8 lane = (dp->stat[4 + (i >> 1)] >> ((i & 1) * 4)) & 0xf;
u8 lpre = (lane & 0x0c) >> 2;
u8 lvsw = (lane & 0x03) >> 0;
mask |= 0xff << shifts[i];
unk |= 1 << (shifts[i] >> 3);
dp->conf[i] = (lpre << 3) | lvsw;
if (lvsw == DP_TRAIN_VOLTAGE_SWING_1200)
dp->conf[i] |= DP_TRAIN_MAX_SWING_REACHED;
if (lpre == DP_TRAIN_PRE_EMPHASIS_9_5)
if ((lpre << 3) == DP_TRAIN_PRE_EMPHASIS_9_5)
dp->conf[i] |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
NV_DEBUG_KMS(dev, "config lane %d %02x\n", i, dp->conf[i]);
if (dp->table[0] < 0x30) {
u8 *last = conf + (dp->entry[4] * dp->table[5]);
while (lvsw != conf[0] || lpre != conf[1]) {
conf += dp->table[5];
if (conf >= last)
return -EINVAL;
}
conf += 2;
} else {
/* no lookup table anymore, set entries for each
* combination of voltage swing and pre-emphasis
* level allowed by the DP spec.
*/
switch (lvsw) {
case 0: lpre += 0; break;
case 1: lpre += 4; break;
case 2: lpre += 7; break;
case 3: lpre += 9; break;
}
conf = conf + (lpre * dp->table[5]);
conf++;
}
drv |= conf[0] << shifts[i];
pre |= conf[1] << shifts[i];
unk = (unk & ~0x0000ff00) | (conf[2] << 8);
dp->func->train_adj(dev, dp->dcb, i, lvsw, lpre);
}
nv_mask(dev, NV50_SOR_DP_UNK118(or, link), mask, drv);
nv_mask(dev, NV50_SOR_DP_UNK120(or, link), mask, pre);
nv_mask(dev, NV50_SOR_DP_UNK130(or, link), 0x0000ff0f, unk);
return auxch_tx(dev, dp->auxch, 8, DP_TRAINING_LANE0_SET, dp->conf, 4);
}
@ -554,8 +357,50 @@ dp_link_train_eq(struct drm_device *dev, struct dp_state *dp)
return eq_done ? 0 : -1;
}
static void
dp_set_downspread(struct drm_device *dev, struct dp_state *dp, bool enable)
{
u16 script = 0x0000;
u8 *entry, *table = nouveau_dp_bios_data(dev, dp->dcb, &entry);
if (table) {
if (table[0] >= 0x20 && table[0] <= 0x30) {
if (enable) script = ROM16(entry[12]);
else script = ROM16(entry[14]);
}
}
nouveau_bios_run_init_table(dev, script, dp->dcb, dp->crtc);
}
static void
dp_link_train_init(struct drm_device *dev, struct dp_state *dp)
{
u16 script = 0x0000;
u8 *entry, *table = nouveau_dp_bios_data(dev, dp->dcb, &entry);
if (table) {
if (table[0] >= 0x20 && table[0] <= 0x30)
script = ROM16(entry[6]);
}
nouveau_bios_run_init_table(dev, script, dp->dcb, dp->crtc);
}
static void
dp_link_train_fini(struct drm_device *dev, struct dp_state *dp)
{
u16 script = 0x0000;
u8 *entry, *table = nouveau_dp_bios_data(dev, dp->dcb, &entry);
if (table) {
if (table[0] >= 0x20 && table[0] <= 0x30)
script = ROM16(entry[8]);
}
nouveau_bios_run_init_table(dev, script, dp->dcb, dp->crtc);
}
bool
nouveau_dp_link_train(struct drm_encoder *encoder, u32 datarate)
nouveau_dp_link_train(struct drm_encoder *encoder, u32 datarate,
struct dp_train_func *func)
{
struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
@ -571,17 +416,15 @@ nouveau_dp_link_train(struct drm_encoder *encoder, u32 datarate)
if (!auxch)
return false;
dp.table = nouveau_dp_bios_data(dev, nv_encoder->dcb, &dp.entry);
if (!dp.table)
return -EINVAL;
dp.func = func;
dp.dcb = nv_encoder->dcb;
dp.crtc = nv_crtc->index;
dp.auxch = auxch->drive;
dp.or = nv_encoder->or;
dp.link = !(nv_encoder->dcb->sorconf.link & 1);
dp.dpcd = nv_encoder->dp.dpcd;
/* adjust required bandwidth for 8B/10B coding overhead */
datarate = (datarate / 8) * 10;
/* some sinks toggle hotplug in response to some of the actions
* we take during link training (DP_SET_POWER is one), we need
* to ignore them for the moment to avoid races.
@ -589,16 +432,10 @@ nouveau_dp_link_train(struct drm_encoder *encoder, u32 datarate)
nouveau_gpio_irq(dev, 0, nv_connector->hpd, 0xff, false);
/* enable down-spreading, if possible */
if (dp.table[1] >= 16) {
u16 script = ROM16(dp.entry[14]);
if (nv_encoder->dp.dpcd[3] & 1)
script = ROM16(dp.entry[12]);
nouveau_bios_run_init_table(dev, script, dp.dcb, dp.crtc);
}
dp_set_downspread(dev, &dp, nv_encoder->dp.dpcd[3] & 1);
/* execute pre-train script from vbios */
nouveau_bios_run_init_table(dev, ROM16(dp.entry[6]), dp.dcb, dp.crtc);
dp_link_train_init(dev, &dp);
/* start off at highest link rate supported by encoder and display */
while (*link_bw > nv_encoder->dp.link_bw)
@ -632,13 +469,36 @@ nouveau_dp_link_train(struct drm_encoder *encoder, u32 datarate)
dp_set_training_pattern(dev, &dp, DP_TRAINING_PATTERN_DISABLE);
/* execute post-train script from vbios */
nouveau_bios_run_init_table(dev, ROM16(dp.entry[8]), dp.dcb, dp.crtc);
dp_link_train_fini(dev, &dp);
/* re-enable hotplug detect */
nouveau_gpio_irq(dev, 0, nv_connector->hpd, 0xff, true);
return true;
}
void
nouveau_dp_dpms(struct drm_encoder *encoder, int mode, u32 datarate,
struct dp_train_func *func)
{
struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
struct nouveau_i2c_chan *auxch;
u8 status;
auxch = nouveau_i2c_find(encoder->dev, nv_encoder->dcb->i2c_index);
if (!auxch)
return;
if (mode == DRM_MODE_DPMS_ON)
status = DP_SET_POWER_D0;
else
status = DP_SET_POWER_D3;
nouveau_dp_auxch(auxch, 8, DP_SET_POWER, &status, 1);
if (mode == DRM_MODE_DPMS_ON)
nouveau_dp_link_train(encoder, datarate, func);
}
bool
nouveau_dp_detect(struct drm_encoder *encoder)
{

18
drivers/gpu/drm/nouveau/nouveau_drv.c
View File

@ -57,6 +57,10 @@ MODULE_PARM_DESC(vram_notify, "Force DMA notifiers to be in VRAM");
int nouveau_vram_notify = 0;
module_param_named(vram_notify, nouveau_vram_notify, int, 0400);
MODULE_PARM_DESC(vram_type, "Override detected VRAM type");
char *nouveau_vram_type;
module_param_named(vram_type, nouveau_vram_type, charp, 0400);
MODULE_PARM_DESC(duallink, "Allow dual-link TMDS (>=GeForce 8)");
int nouveau_duallink = 1;
module_param_named(duallink, nouveau_duallink, int, 0400);
@ -89,7 +93,7 @@ MODULE_PARM_DESC(override_conntype, "Ignore DCB connector type");
int nouveau_override_conntype = 0;
module_param_named(override_conntype, nouveau_override_conntype, int, 0400);
MODULE_PARM_DESC(tv_disable, "Disable TV-out detection\n");
MODULE_PARM_DESC(tv_disable, "Disable TV-out detection");
int nouveau_tv_disable = 0;
module_param_named(tv_disable, nouveau_tv_disable, int, 0400);
@ -104,27 +108,27 @@ module_param_named(tv_norm, nouveau_tv_norm, charp, 0400);
MODULE_PARM_DESC(reg_debug, "Register access debug bitmask:\n"
"\t\t0x1 mc, 0x2 video, 0x4 fb, 0x8 extdev,\n"
"\t\t0x10 crtc, 0x20 ramdac, 0x40 vgacrtc, 0x80 rmvio,\n"
"\t\t0x100 vgaattr, 0x200 EVO (G80+). ");
"\t\t0x100 vgaattr, 0x200 EVO (G80+)");
int nouveau_reg_debug;
module_param_named(reg_debug, nouveau_reg_debug, int, 0600);
MODULE_PARM_DESC(perflvl, "Performance level (default: boot)\n");
MODULE_PARM_DESC(perflvl, "Performance level (default: boot)");
char *nouveau_perflvl;
module_param_named(perflvl, nouveau_perflvl, charp, 0400);
MODULE_PARM_DESC(perflvl_wr, "Allow perflvl changes (warning: dangerous!)\n");
MODULE_PARM_DESC(perflvl_wr, "Allow perflvl changes (warning: dangerous!)");
int nouveau_perflvl_wr;
module_param_named(perflvl_wr, nouveau_perflvl_wr, int, 0400);
MODULE_PARM_DESC(msi, "Enable MSI (default: off)\n");
MODULE_PARM_DESC(msi, "Enable MSI (default: off)");
int nouveau_msi;
module_param_named(msi, nouveau_msi, int, 0400);
MODULE_PARM_DESC(ctxfw, "Use external HUB/GPC ucode (fermi)\n");
MODULE_PARM_DESC(ctxfw, "Use external HUB/GPC ucode (fermi)");
int nouveau_ctxfw;
module_param_named(ctxfw, nouveau_ctxfw, int, 0400);
MODULE_PARM_DESC(mxmdcb, "Santise DCB table according to MXM-SIS\n");
MODULE_PARM_DESC(mxmdcb, "Santise DCB table according to MXM-SIS");
int nouveau_mxmdcb = 1;
module_param_named(mxmdcb, nouveau_mxmdcb, int, 0400);

150
drivers/gpu/drm/nouveau/nouveau_drv.h
View File

@ -406,6 +406,9 @@ struct nouveau_display_engine {
struct drm_property *underscan_property;
struct drm_property *underscan_hborder_property;
struct drm_property *underscan_vborder_property;
/* not really hue and saturation: */
struct drm_property *vibrant_hue_property;
struct drm_property *color_vibrance_property;
};
struct nouveau_gpio_engine {
@ -432,58 +435,85 @@ struct nouveau_pm_voltage {
int nr_level;
};
/* Exclusive upper limits */
#define NV_MEM_CL_DDR2_MAX 8
#define NV_MEM_WR_DDR2_MAX 9
#define NV_MEM_CL_DDR3_MAX 17
#define NV_MEM_WR_DDR3_MAX 17
#define NV_MEM_CL_GDDR3_MAX 16
#define NV_MEM_WR_GDDR3_MAX 18
#define NV_MEM_CL_GDDR5_MAX 21
#define NV_MEM_WR_GDDR5_MAX 20
struct nouveau_pm_memtiming {
int id;
u32 reg_0; /* 0x10f290 on Fermi, 0x100220 for older */
u32 reg_1;
u32 reg_2;
u32 reg_3;
u32 reg_4;
u32 reg_5;
u32 reg_6;
u32 reg_7;
u32 reg_8;
/* To be written to 0x1002c0 */
u8 CL;
u8 WR;
u32 reg[9];
u32 mr[4];
u8 tCWL;
u8 odt;
u8 drive_strength;
};
struct nouveau_pm_tbl_header{
struct nouveau_pm_tbl_header {
u8 version;
u8 header_len;
u8 entry_cnt;
u8 entry_len;
};
struct nouveau_pm_tbl_entry{
struct nouveau_pm_tbl_entry {
u8 tWR;
u8 tUNK_1;
u8 tWTR;
u8 tCL;
u8 tRP; /* Byte 3 */
u8 tRC;
u8 empty_4;
u8 tRAS; /* Byte 5 */
u8 tRFC; /* Byte 5 */
u8 empty_6;
u8 tRFC; /* Byte 7 */
u8 tRAS; /* Byte 7 */
u8 empty_8;
u8 tRC; /* Byte 9 */
u8 tUNK_10, tUNK_11, tUNK_12, tUNK_13, tUNK_14;
u8 empty_15,empty_16,empty_17;
u8 tUNK_18, tUNK_19, tUNK_20, tUNK_21;
u8 tRP; /* Byte 9 */
u8 tRCDRD;
u8 tRCDWR;
u8 tRRD;
u8 tUNK_13;
u8 RAM_FT1; /* 14, a bitmask of random RAM features */
u8 empty_15;
u8 tUNK_16;
u8 empty_17;
u8 tUNK_18;
u8 tCWL;
u8 tUNK_20, tUNK_21;
};
/* nouveau_mem.c */
void nv30_mem_timing_entry(struct drm_device *dev, struct nouveau_pm_tbl_header *hdr,
struct nouveau_pm_tbl_entry *e, uint8_t magic_number,
struct nouveau_pm_memtiming *timing);
struct nouveau_pm_profile;
struct nouveau_pm_profile_func {
void (*destroy)(struct nouveau_pm_profile *);
void (*init)(struct nouveau_pm_profile *);
void (*fini)(struct nouveau_pm_profile *);
struct nouveau_pm_level *(*select)(struct nouveau_pm_profile *);
};
struct nouveau_pm_profile {
const struct nouveau_pm_profile_func *func;
struct list_head head;
char name[8];
};
#define NOUVEAU_PM_MAX_LEVEL 8
struct nouveau_pm_level {
struct nouveau_pm_profile profile;
struct device_attribute dev_attr;
char name[32];
int id;
u32 core;
struct nouveau_pm_memtiming timing;
u32 memory;
u16 memscript;
u32 core;
u32 shader;
u32 rop;
u32 copy;
@ -498,9 +528,6 @@ struct nouveau_pm_level {
u32 volt_min; /* microvolts */
u32 volt_max;
u8 fanspeed;
u16 memscript;
struct nouveau_pm_memtiming *timing;
};
struct nouveau_pm_temp_sensor_constants {
@ -517,27 +544,26 @@ struct nouveau_pm_threshold_temp {
s16 fan_boost;
};
struct nouveau_pm_memtimings {
bool supported;
struct nouveau_pm_memtiming *timing;
int nr_timing;
};
struct nouveau_pm_fan {
u32 percent;
u32 min_duty;
u32 max_duty;
u32 pwm_freq;
u32 pwm_divisor;
};
struct nouveau_pm_engine {
struct nouveau_pm_voltage voltage;
struct nouveau_pm_level perflvl[NOUVEAU_PM_MAX_LEVEL];
int nr_perflvl;
struct nouveau_pm_memtimings memtimings;
struct nouveau_pm_temp_sensor_constants sensor_constants;
struct nouveau_pm_threshold_temp threshold_temp;
struct nouveau_pm_fan fan;
u32 pwm_divisor;
struct nouveau_pm_profile *profile_ac;
struct nouveau_pm_profile *profile_dc;
struct nouveau_pm_profile *profile;
struct list_head profiles;
struct nouveau_pm_level boot;
struct nouveau_pm_level *cur;
@ -669,14 +695,14 @@ struct nv04_mode_state {
};
enum nouveau_card_type {
NV_04 = 0x00,
NV_04 = 0x04,
NV_10 = 0x10,
NV_20 = 0x20,
NV_30 = 0x30,
NV_40 = 0x40,
NV_50 = 0x50,
NV_C0 = 0xc0,
NV_D0 = 0xd0
NV_D0 = 0xd0,
};
struct drm_nouveau_private {
@ -772,8 +798,22 @@ struct drm_nouveau_private {
} tile;
/* VRAM/fb configuration */
enum {
NV_MEM_TYPE_UNKNOWN = 0,
NV_MEM_TYPE_STOLEN,
NV_MEM_TYPE_SGRAM,
NV_MEM_TYPE_SDRAM,
NV_MEM_TYPE_DDR1,
NV_MEM_TYPE_DDR2,
NV_MEM_TYPE_DDR3,
NV_MEM_TYPE_GDDR2,
NV_MEM_TYPE_GDDR3,
NV_MEM_TYPE_GDDR4,
NV_MEM_TYPE_GDDR5
} vram_type;
uint64_t vram_size;
uint64_t vram_sys_base;
bool vram_rank_B;
uint64_t fb_available_size;
uint64_t fb_mappable_pages;
@ -846,6 +886,7 @@ extern int nouveau_uscript_lvds;
extern int nouveau_uscript_tmds;
extern int nouveau_vram_pushbuf;
extern int nouveau_vram_notify;
extern char *nouveau_vram_type;
extern int nouveau_fbpercrtc;
extern int nouveau_tv_disable;
extern char *nouveau_tv_norm;
@ -894,8 +935,12 @@ extern void nouveau_mem_gart_fini(struct drm_device *);
extern int nouveau_mem_init_agp(struct drm_device *);
extern int nouveau_mem_reset_agp(struct drm_device *);
extern void nouveau_mem_close(struct drm_device *);
extern int nouveau_mem_detect(struct drm_device *);
extern bool nouveau_mem_flags_valid(struct drm_device *, u32 tile_flags);
extern int nouveau_mem_timing_calc(struct drm_device *, u32 freq,
struct nouveau_pm_memtiming *);
extern void nouveau_mem_timing_read(struct drm_device *,
struct nouveau_pm_memtiming *);
extern int nouveau_mem_vbios_type(struct drm_device *);
extern struct nouveau_tile_reg *nv10_mem_set_tiling(
struct drm_device *dev, uint32_t addr, uint32_t size,
uint32_t pitch, uint32_t flags);
@ -1117,19 +1162,14 @@ int nouveau_ttm_mmap(struct file *, struct vm_area_struct *);
/* nouveau_hdmi.c */
void nouveau_hdmi_mode_set(struct drm_encoder *, struct drm_display_mode *);
/* nouveau_dp.c */
int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr,
uint8_t *data, int data_nr);
bool nouveau_dp_detect(struct drm_encoder *);
bool nouveau_dp_link_train(struct drm_encoder *, u32 datarate);
void nouveau_dp_tu_update(struct drm_device *, int, int, u32, u32);
u8 *nouveau_dp_bios_data(struct drm_device *, struct dcb_entry *, u8 **);
/* nv04_fb.c */
extern int nv04_fb_vram_init(struct drm_device *);
extern int nv04_fb_init(struct drm_device *);
extern void nv04_fb_takedown(struct drm_device *);
/* nv10_fb.c */
extern int nv10_fb_vram_init(struct drm_device *dev);
extern int nv1a_fb_vram_init(struct drm_device *dev);
extern int nv10_fb_init(struct drm_device *);
extern void nv10_fb_takedown(struct drm_device *);
extern void nv10_fb_init_tile_region(struct drm_device *dev, int i,
@ -1138,6 +1178,16 @@ extern void nv10_fb_init_tile_region(struct drm_device *dev, int i,
extern void nv10_fb_set_tile_region(struct drm_device *dev, int i);
extern void nv10_fb_free_tile_region(struct drm_device *dev, int i);
/* nv20_fb.c */
extern int nv20_fb_vram_init(struct drm_device *dev);
extern int nv20_fb_init(struct drm_device *);
extern void nv20_fb_takedown(struct drm_device *);
extern void nv20_fb_init_tile_region(struct drm_device *dev, int i,
uint32_t addr, uint32_t size,
uint32_t pitch, uint32_t flags);
extern void nv20_fb_set_tile_region(struct drm_device *dev, int i);
extern void nv20_fb_free_tile_region(struct drm_device *dev, int i);
/* nv30_fb.c */
extern int nv30_fb_init(struct drm_device *);
extern void nv30_fb_takedown(struct drm_device *);
@ -1147,6 +1197,7 @@ extern void nv30_fb_init_tile_region(struct drm_device *dev, int i,
extern void nv30_fb_free_tile_region(struct drm_device *dev, int i);
/* nv40_fb.c */
extern int nv40_fb_vram_init(struct drm_device *dev);
extern int nv40_fb_init(struct drm_device *);
extern void nv40_fb_takedown(struct drm_device *);
extern void nv40_fb_set_tile_region(struct drm_device *dev, int i);
@ -1703,6 +1754,7 @@ nv44_graph_class(struct drm_device *dev)
#define NV_MEM_ACCESS_RW (NV_MEM_ACCESS_RO | NV_MEM_ACCESS_WO)
#define NV_MEM_ACCESS_SYS 4
#define NV_MEM_ACCESS_VM 8
#define NV_MEM_ACCESS_NOSNOOP 16
#define NV_MEM_TARGET_VRAM 0
#define NV_MEM_TARGET_PCI 1

18
drivers/gpu/drm/nouveau/nouveau_encoder.h
View File

@ -32,6 +32,14 @@
#define NV_DPMS_CLEARED 0x80
struct dp_train_func {
void (*link_set)(struct drm_device *, struct dcb_entry *, int crtc,
int nr, u32 bw, bool enhframe);
void (*train_set)(struct drm_device *, struct dcb_entry *, u8 pattern);
void (*train_adj)(struct drm_device *, struct dcb_entry *,
u8 lane, u8 swing, u8 preem);
};
struct nouveau_encoder {
struct drm_encoder_slave base;
@ -78,9 +86,19 @@ get_slave_funcs(struct drm_encoder *enc)
return to_encoder_slave(enc)->slave_funcs;
}
/* nouveau_dp.c */
int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr,
uint8_t *data, int data_nr);
bool nouveau_dp_detect(struct drm_encoder *);
void nouveau_dp_dpms(struct drm_encoder *, int mode, u32 datarate,
struct dp_train_func *);
u8 *nouveau_dp_bios_data(struct drm_device *, struct dcb_entry *, u8 **);
struct nouveau_connector *
nouveau_encoder_connector_get(struct nouveau_encoder *encoder);
int nv50_sor_create(struct drm_connector *, struct dcb_entry *);
void nv50_sor_dp_calc_tu(struct drm_device *, int, int, u32, u32);
int nv50_dac_create(struct drm_connector *, struct dcb_entry *);
#endif /* __NOUVEAU_ENCODER_H__ */

825
drivers/gpu/drm/nouveau/nouveau_mem.c
View File

@ -26,7 +26,8 @@
* DEALINGS IN THE SOFTWARE.
*
* Authors:
* Keith Whitwell <keith@tungstengraphics.com>
* Ben Skeggs <bskeggs@redhat.com>
* Roy Spliet <r.spliet@student.tudelft.nl>
*/
@ -192,75 +193,6 @@ nouveau_mem_gart_fini(struct drm_device *dev)
}
}
static uint32_t
nouveau_mem_detect_nv04(struct drm_device *dev)
{
uint32_t boot0 = nv_rd32(dev, NV04_PFB_BOOT_0);
if (boot0 & 0x00000100)
return (((boot0 >> 12) & 0xf) * 2 + 2) * 1024 * 1024;
switch (boot0 & NV04_PFB_BOOT_0_RAM_AMOUNT) {
case NV04_PFB_BOOT_0_RAM_AMOUNT_32MB:
return 32 * 1024 * 1024;
case NV04_PFB_BOOT_0_RAM_AMOUNT_16MB:
return 16 * 1024 * 1024;
case NV04_PFB_BOOT_0_RAM_AMOUNT_8MB:
return 8 * 1024 * 1024;
case NV04_PFB_BOOT_0_RAM_AMOUNT_4MB:
return 4 * 1024 * 1024;
}
return 0;
}
static uint32_t
nouveau_mem_detect_nforce(struct drm_device *dev)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
struct pci_dev *bridge;
uint32_t mem;
bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 1));
if (!bridge) {
NV_ERROR(dev, "no bridge device\n");
return 0;
}
if (dev_priv->flags & NV_NFORCE) {
pci_read_config_dword(bridge, 0x7C, &mem);
return (uint64_t)(((mem >> 6) & 31) + 1)*1024*1024;
} else
if (dev_priv->flags & NV_NFORCE2) {
pci_read_config_dword(bridge, 0x84, &mem);
return (uint64_t)(((mem >> 4) & 127) + 1)*1024*1024;
}
NV_ERROR(dev, "impossible!\n");
return 0;
}
int
nouveau_mem_detect(struct drm_device *dev)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
if (dev_priv->card_type == NV_04) {
dev_priv->vram_size = nouveau_mem_detect_nv04(dev);
} else
if (dev_priv->flags & (NV_NFORCE | NV_NFORCE2)) {
dev_priv->vram_size = nouveau_mem_detect_nforce(dev);
} else
if (dev_priv->card_type < NV_50) {
dev_priv->vram_size = nv_rd32(dev, NV04_PFB_FIFO_DATA);
dev_priv->vram_size &= NV10_PFB_FIFO_DATA_RAM_AMOUNT_MB_MASK;
}
if (dev_priv->vram_size)
return 0;
return -ENOMEM;
}
bool
nouveau_mem_flags_valid(struct drm_device *dev, u32 tile_flags)
{
@ -385,11 +317,29 @@ nouveau_mem_init_agp(struct drm_device *dev)
return 0;
}
static const struct vram_types {
int value;
const char *name;
} vram_type_map[] = {
{ NV_MEM_TYPE_STOLEN , "stolen system memory" },
{ NV_MEM_TYPE_SGRAM , "SGRAM" },
{ NV_MEM_TYPE_SDRAM , "SDRAM" },
{ NV_MEM_TYPE_DDR1 , "DDR1" },
{ NV_MEM_TYPE_DDR2 , "DDR2" },
{ NV_MEM_TYPE_DDR3 , "DDR3" },
{ NV_MEM_TYPE_GDDR2 , "GDDR2" },
{ NV_MEM_TYPE_GDDR3 , "GDDR3" },
{ NV_MEM_TYPE_GDDR4 , "GDDR4" },
{ NV_MEM_TYPE_GDDR5 , "GDDR5" },
{ NV_MEM_TYPE_UNKNOWN, "unknown type" }
};
int
nouveau_mem_vram_init(struct drm_device *dev)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
struct ttm_bo_device *bdev = &dev_priv->ttm.bdev;
const struct vram_types *vram_type;
int ret, dma_bits;
dma_bits = 32;
@ -427,7 +377,21 @@ nouveau_mem_vram_init(struct drm_device *dev)
return ret;
}
NV_INFO(dev, "Detected %dMiB VRAM\n", (int)(dev_priv->vram_size >> 20));
vram_type = vram_type_map;
while (vram_type->value != NV_MEM_TYPE_UNKNOWN) {
if (nouveau_vram_type) {
if (!strcasecmp(nouveau_vram_type, vram_type->name))
break;
dev_priv->vram_type = vram_type->value;
} else {
if (vram_type->value == dev_priv->vram_type)
break;
}
vram_type++;
}
NV_INFO(dev, "Detected %dMiB VRAM (%s)\n",
(int)(dev_priv->vram_size >> 20), vram_type->name);
if (dev_priv->vram_sys_base) {
NV_INFO(dev, "Stolen system memory at: 0x%010llx\n",
dev_priv->vram_sys_base);
@ -508,216 +472,617 @@ nouveau_mem_gart_init(struct drm_device *dev)
return 0;
}
/* XXX: For now a dummy. More samples required, possibly even a card
* Called from nouveau_perf.c */
void nv30_mem_timing_entry(struct drm_device *dev, struct nouveau_pm_tbl_header *hdr,
struct nouveau_pm_tbl_entry *e, uint8_t magic_number,
struct nouveau_pm_memtiming *timing) {
NV_DEBUG(dev,"Timing entry format unknown, please contact nouveau developers");
}
void nv40_mem_timing_entry(struct drm_device *dev, struct nouveau_pm_tbl_header *hdr,
struct nouveau_pm_tbl_entry *e, uint8_t magic_number,
struct nouveau_pm_memtiming *timing) {
timing->reg_0 = (e->tRC << 24 | e->tRFC << 16 | e->tRAS << 8 | e->tRP);
static int
nv40_mem_timing_calc(struct drm_device *dev, u32 freq,
struct nouveau_pm_tbl_entry *e, u8 len,
struct nouveau_pm_memtiming *boot,
struct nouveau_pm_memtiming *t)
{
t->reg[0] = (e->tRP << 24 | e->tRAS << 16 | e->tRFC << 8 | e->tRC);
/* XXX: I don't trust the -1's and +1's... they must come
* from somewhere! */
timing->reg_1 = (e->tWR + 2 + magic_number) << 24 |
1 << 16 |
(e->tUNK_1 + 2 + magic_number) << 8 |
(e->tCL + 2 - magic_number);
timing->reg_2 = (magic_number << 24 | e->tUNK_12 << 16 | e->tUNK_11 << 8 | e->tUNK_10);
timing->reg_2 |= 0x20200000;
t->reg[1] = (e->tWR + 2 + (t->tCWL - 1)) << 24 |
1 << 16 |
(e->tWTR + 2 + (t->tCWL - 1)) << 8 |
(e->tCL + 2 - (t->tCWL - 1));
NV_DEBUG(dev, "Entry %d: 220: %08x %08x %08x\n", timing->id,
timing->reg_0, timing->reg_1,timing->reg_2);
t->reg[2] = 0x20200000 |
((t->tCWL - 1) << 24 |
e->tRRD << 16 |
e->tRCDWR << 8 |
e->tRCDRD);
NV_DEBUG(dev, "Entry %d: 220: %08x %08x %08x\n", t->id,
t->reg[0], t->reg[1], t->reg[2]);
return 0;
}
void nv50_mem_timing_entry(struct drm_device *dev, struct bit_entry *P, struct nouveau_pm_tbl_header *hdr,
struct nouveau_pm_tbl_entry *e, uint8_t magic_number,struct nouveau_pm_memtiming *timing) {
static int
nv50_mem_timing_calc(struct drm_device *dev, u32 freq,
struct nouveau_pm_tbl_entry *e, u8 len,
struct nouveau_pm_memtiming *boot,
struct nouveau_pm_memtiming *t)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
struct bit_entry P;
uint8_t unk18 = 1, unk20 = 0, unk21 = 0, tmp7_3;
uint8_t unk18 = 1,
unk19 = 1,
unk20 = 0,
unk21 = 0;
if (bit_table(dev, 'P', &P))
return -EINVAL;
switch (min(hdr->entry_len, (u8) 22)) {
switch (min(len, (u8) 22)) {
case 22:
unk21 = e->tUNK_21;
case 21:
unk20 = e->tUNK_20;
case 20:
unk19 = e->tUNK_19;
if (e->tCWL > 0)
t->tCWL = e->tCWL;
case 19:
unk18 = e->tUNK_18;
break;
}
timing->reg_0 = (e->tRC << 24 | e->tRFC << 16 | e->tRAS << 8 | e->tRP);
t->reg[0] = (e->tRP << 24 | e->tRAS << 16 | e->tRFC << 8 | e->tRC);
/* XXX: I don't trust the -1's and +1's... they must come
* from somewhere! */
timing->reg_1 = (e->tWR + unk19 + 1 + magic_number) << 24 |
max(unk18, (u8) 1) << 16 |
(e->tUNK_1 + unk19 + 1 + magic_number) << 8;
if (dev_priv->chipset == 0xa8) {
timing->reg_1 |= (e->tCL - 1);
t->reg[1] = (e->tWR + 2 + (t->tCWL - 1)) << 24 |
max(unk18, (u8) 1) << 16 |
(e->tWTR + 2 + (t->tCWL - 1)) << 8;
t->reg[2] = ((t->tCWL - 1) << 24 |
e->tRRD << 16 |
e->tRCDWR << 8 |
e->tRCDRD);
t->reg[4] = e->tUNK_13 << 8 | e->tUNK_13;
t->reg[5] = (e->tRFC << 24 | max(e->tRCDRD, e->tRCDWR) << 16 | e->tRP);
t->reg[8] = boot->reg[8] & 0xffffff00;
if (P.version == 1) {
t->reg[1] |= (e->tCL + 2 - (t->tCWL - 1));
t->reg[3] = (0x14 + e->tCL) << 24 |
0x16 << 16 |
(e->tCL - 1) << 8 |
(e->tCL - 1);
t->reg[4] |= boot->reg[4] & 0xffff0000;
t->reg[6] = (0x33 - t->tCWL) << 16 |
t->tCWL << 8 |
(0x2e + e->tCL - t->tCWL);
t->reg[7] = 0x4000202 | (e->tCL - 1) << 16;
/* XXX: P.version == 1 only has DDR2 and GDDR3? */
if (dev_priv->vram_type == NV_MEM_TYPE_DDR2) {
t->reg[5] |= (e->tCL + 3) << 8;
t->reg[6] |= (t->tCWL - 2) << 8;
t->reg[8] |= (e->tCL - 4);
} else {
t->reg[5] |= (e->tCL + 2) << 8;
t->reg[6] |= t->tCWL << 8;
t->reg[8] |= (e->tCL - 2);
}
} else {
timing->reg_1 |= (e->tCL + 2 - magic_number);
}
timing->reg_2 = (e->tUNK_12 << 16 | e->tUNK_11 << 8 | e->tUNK_10);
t->reg[1] |= (5 + e->tCL - (t->tCWL));
timing->reg_5 = (e->tRAS << 24 | e->tRC);
timing->reg_5 += max(e->tUNK_10, e->tUNK_11) << 16;
/* XXX: 0xb? 0x30? */
t->reg[3] = (0x30 + e->tCL) << 24 |
(boot->reg[3] & 0x00ff0000)|
(0xb + e->tCL) << 8 |
(e->tCL - 1);
t->reg[4] |= (unk20 << 24 | unk21 << 16);
if (P->version == 1) {
timing->reg_2 |= magic_number << 24;
timing->reg_3 = (0x14 + e->tCL) << 24 |
0x16 << 16 |
(e->tCL - 1) << 8 |
(e->tCL - 1);
timing->reg_4 = (nv_rd32(dev,0x10022c) & 0xffff0000) | e->tUNK_13 << 8 | e->tUNK_13;
timing->reg_5 |= (e->tCL + 2) << 8;
timing->reg_7 = 0x4000202 | (e->tCL - 1) << 16;
} else {
timing->reg_2 |= (unk19 - 1) << 24;
/* XXX: reg_10022c for recentish cards pretty much unknown*/
timing->reg_3 = e->tCL - 1;
timing->reg_4 = (unk20 << 24 | unk21 << 16 |
e->tUNK_13 << 8 | e->tUNK_13);
/* XXX: +6? */
timing->reg_5 |= (unk19 + 6) << 8;
t->reg[5] |= (t->tCWL + 6) << 8;
/* XXX: reg_10023c currently unknown
* 10023c seen as 06xxxxxx, 0bxxxxxx or 0fxxxxxx */
timing->reg_7 = 0x202;
t->reg[6] = (0x5a + e->tCL) << 16 |
(6 - e->tCL + t->tCWL) << 8 |
(0x50 + e->tCL - t->tCWL);
tmp7_3 = (boot->reg[7] & 0xff000000) >> 24;
t->reg[7] = (tmp7_3 << 24) |
((tmp7_3 - 6 + e->tCL) << 16) |
0x202;
}
NV_DEBUG(dev, "Entry %d: 220: %08x %08x %08x %08x\n", timing->id,
timing->reg_0, timing->reg_1,
timing->reg_2, timing->reg_3);
NV_DEBUG(dev, "Entry %d: 220: %08x %08x %08x %08x\n", t->id,
t->reg[0], t->reg[1], t->reg[2], t->reg[3]);
NV_DEBUG(dev, " 230: %08x %08x %08x %08x\n",
timing->reg_4, timing->reg_5,
timing->reg_6, timing->reg_7);
NV_DEBUG(dev, " 240: %08x\n", timing->reg_8);
t->reg[4], t->reg[5], t->reg[6], t->reg[7]);
NV_DEBUG(dev, " 240: %08x\n", t->reg[8]);
return 0;
}
void nvc0_mem_timing_entry(struct drm_device *dev, struct nouveau_pm_tbl_header *hdr,
struct nouveau_pm_tbl_entry *e, struct nouveau_pm_memtiming *timing) {
timing->reg_0 = (e->tRC << 24 | (e->tRFC & 0x7f) << 17 | e->tRAS << 8 | e->tRP);
timing->reg_1 = (nv_rd32(dev,0x10f294) & 0xff000000) | (e->tUNK_11&0x0f) << 20 | (e->tUNK_19 << 7) | (e->tCL & 0x0f);
timing->reg_2 = (nv_rd32(dev,0x10f298) & 0xff0000ff) | e->tWR << 16 | e->tUNK_1 << 8;
timing->reg_3 = e->tUNK_20 << 9 | e->tUNK_13;
timing->reg_4 = (nv_rd32(dev,0x10f2a0) & 0xfff000ff) | e->tUNK_12 << 15;
NV_DEBUG(dev, "Entry %d: 290: %08x %08x %08x %08x\n", timing->id,
timing->reg_0, timing->reg_1,
timing->reg_2, timing->reg_3);
NV_DEBUG(dev, " 2a0: %08x %08x %08x %08x\n",
timing->reg_4, timing->reg_5,
timing->reg_6, timing->reg_7);
static int
nvc0_mem_timing_calc(struct drm_device *dev, u32 freq,
struct nouveau_pm_tbl_entry *e, u8 len,
struct nouveau_pm_memtiming *boot,
struct nouveau_pm_memtiming *t)
{
if (e->tCWL > 0)
t->tCWL = e->tCWL;
t->reg[0] = (e->tRP << 24 | (e->tRAS & 0x7f) << 17 |
e->tRFC << 8 | e->tRC);
t->reg[1] = (boot->reg[1] & 0xff000000) |
(e->tRCDWR & 0x0f) << 20 |
(e->tRCDRD & 0x0f) << 14 |
(t->tCWL << 7) |
(e->tCL & 0x0f);
t->reg[2] = (boot->reg[2] & 0xff0000ff) |
e->tWR << 16 | e->tWTR << 8;
t->reg[3] = (e->tUNK_20 & 0x1f) << 9 |
(e->tUNK_21 & 0xf) << 5 |
(e->tUNK_13 & 0x1f);
t->reg[4] = (boot->reg[4] & 0xfff00fff) |
(e->tRRD&0x1f) << 15;
NV_DEBUG(dev, "Entry %d: 290: %08x %08x %08x %08x\n", t->id,
t->reg[0], t->reg[1], t->reg[2], t->reg[3]);
NV_DEBUG(dev, " 2a0: %08x\n", t->reg[4]);
return 0;
}
/**
* Processes the Memory Timing BIOS table, stores generated
* register values
* @pre init scripts were run, memtiming regs are initialized
* MR generation methods
*/
void
nouveau_mem_timing_init(struct drm_device *dev)
static int
nouveau_mem_ddr2_mr(struct drm_device *dev, u32 freq,
struct nouveau_pm_tbl_entry *e, u8 len,
struct nouveau_pm_memtiming *boot,
struct nouveau_pm_memtiming *t)
{
t->drive_strength = 0;
if (len < 15) {
t->odt = boot->odt;
} else {
t->odt = e->RAM_FT1 & 0x07;
}
if (e->tCL >= NV_MEM_CL_DDR2_MAX) {
NV_WARN(dev, "(%u) Invalid tCL: %u", t->id, e->tCL);
return -ERANGE;
}
if (e->tWR >= NV_MEM_WR_DDR2_MAX) {
NV_WARN(dev, "(%u) Invalid tWR: %u", t->id, e->tWR);
return -ERANGE;
}
if (t->odt > 3) {
NV_WARN(dev, "(%u) Invalid odt value, assuming disabled: %x",
t->id, t->odt);
t->odt = 0;
}
t->mr[0] = (boot->mr[0] & 0x100f) |
(e->tCL) << 4 |
(e->tWR - 1) << 9;
t->mr[1] = (boot->mr[1] & 0x101fbb) |
(t->odt & 0x1) << 2 |
(t->odt & 0x2) << 5;
NV_DEBUG(dev, "(%u) MR: %08x", t->id, t->mr[0]);
return 0;
}
uint8_t nv_mem_wr_lut_ddr3[NV_MEM_WR_DDR3_MAX] = {
0, 0, 0, 0, 0, 1, 2, 3, 4, 5, 5, 6, 6, 7, 7, 0, 0};
static int
nouveau_mem_ddr3_mr(struct drm_device *dev, u32 freq,
struct nouveau_pm_tbl_entry *e, u8 len,
struct nouveau_pm_memtiming *boot,
struct nouveau_pm_memtiming *t)
{
u8 cl = e->tCL - 4;
t->drive_strength = 0;
if (len < 15) {
t->odt = boot->odt;
} else {
t->odt = e->RAM_FT1 & 0x07;
}
if (e->tCL >= NV_MEM_CL_DDR3_MAX || e->tCL < 4) {
NV_WARN(dev, "(%u) Invalid tCL: %u", t->id, e->tCL);
return -ERANGE;
}
if (e->tWR >= NV_MEM_WR_DDR3_MAX || e->tWR < 4) {
NV_WARN(dev, "(%u) Invalid tWR: %u", t->id, e->tWR);
return -ERANGE;
}
if (e->tCWL < 5) {
NV_WARN(dev, "(%u) Invalid tCWL: %u", t->id, e->tCWL);
return -ERANGE;
}
t->mr[0] = (boot->mr[0] & 0x180b) |
/* CAS */
(cl & 0x7) << 4 |
(cl & 0x8) >> 1 |
(nv_mem_wr_lut_ddr3[e->tWR]) << 9;
t->mr[1] = (boot->mr[1] & 0x101dbb) |
(t->odt & 0x1) << 2 |
(t->odt & 0x2) << 5 |
(t->odt & 0x4) << 7;
t->mr[2] = (boot->mr[2] & 0x20ffb7) | (e->tCWL - 5) << 3;
NV_DEBUG(dev, "(%u) MR: %08x %08x", t->id, t->mr[0], t->mr[2]);
return 0;
}
uint8_t nv_mem_cl_lut_gddr3[NV_MEM_CL_GDDR3_MAX] = {
0, 0, 0, 0, 4, 5, 6, 7, 0, 1, 2, 3, 8, 9, 10, 11};
uint8_t nv_mem_wr_lut_gddr3[NV_MEM_WR_GDDR3_MAX] = {
0, 0, 0, 0, 0, 2, 3, 8, 9, 10, 11, 0, 0, 1, 1, 0, 3};
static int
nouveau_mem_gddr3_mr(struct drm_device *dev, u32 freq,
struct nouveau_pm_tbl_entry *e, u8 len,
struct nouveau_pm_memtiming *boot,
struct nouveau_pm_memtiming *t)
{
if (len < 15) {
t->drive_strength = boot->drive_strength;
t->odt = boot->odt;
} else {
t->drive_strength = (e->RAM_FT1 & 0x30) >> 4;
t->odt = e->RAM_FT1 & 0x07;
}
if (e->tCL >= NV_MEM_CL_GDDR3_MAX) {
NV_WARN(dev, "(%u) Invalid tCL: %u", t->id, e->tCL);
return -ERANGE;
}
if (e->tWR >= NV_MEM_WR_GDDR3_MAX) {
NV_WARN(dev, "(%u) Invalid tWR: %u", t->id, e->tWR);
return -ERANGE;
}
if (t->odt > 3) {
NV_WARN(dev, "(%u) Invalid odt value, assuming autocal: %x",
t->id, t->odt);
t->odt = 0;
}
t->mr[0] = (boot->mr[0] & 0xe0b) |
/* CAS */
((nv_mem_cl_lut_gddr3[e->tCL] & 0x7) << 4) |
((nv_mem_cl_lut_gddr3[e->tCL] & 0x8) >> 2);
t->mr[1] = (boot->mr[1] & 0x100f40) | t->drive_strength |
(t->odt << 2) |
(nv_mem_wr_lut_gddr3[e->tWR] & 0xf) << 4;
t->mr[2] = boot->mr[2];
NV_DEBUG(dev, "(%u) MR: %08x %08x %08x", t->id,
t->mr[0], t->mr[1], t->mr[2]);
return 0;
}
static int
nouveau_mem_gddr5_mr(struct drm_device *dev, u32 freq,
struct nouveau_pm_tbl_entry *e, u8 len,
struct nouveau_pm_memtiming *boot,
struct nouveau_pm_memtiming *t)
{
if (len < 15) {
t->drive_strength = boot->drive_strength;
t->odt = boot->odt;
} else {
t->drive_strength = (e->RAM_FT1 & 0x30) >> 4;
t->odt = e->RAM_FT1 & 0x03;
}
if (e->tCL >= NV_MEM_CL_GDDR5_MAX) {
NV_WARN(dev, "(%u) Invalid tCL: %u", t->id, e->tCL);
return -ERANGE;
}
if (e->tWR >= NV_MEM_WR_GDDR5_MAX) {
NV_WARN(dev, "(%u) Invalid tWR: %u", t->id, e->tWR);
return -ERANGE;
}
if (t->odt > 3) {
NV_WARN(dev, "(%u) Invalid odt value, assuming autocal: %x",
t->id, t->odt);
t->odt = 0;
}
t->mr[0] = (boot->mr[0] & 0x007) |
((e->tCL - 5) << 3) |
((e->tWR - 4) << 8);
t->mr[1] = (boot->mr[1] & 0x1007f0) |
t->drive_strength |
(t->odt << 2);
NV_DEBUG(dev, "(%u) MR: %08x %08x", t->id, t->mr[0], t->mr[1]);
return 0;
}
int
nouveau_mem_timing_calc(struct drm_device *dev, u32 freq,
struct nouveau_pm_memtiming *t)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
struct nouveau_pm_engine *pm = &dev_priv->engine.pm;
struct nouveau_pm_memtimings *memtimings = &pm->memtimings;
struct nvbios *bios = &dev_priv->vbios;
struct bit_entry P;
struct nouveau_pm_tbl_header *hdr = NULL;
uint8_t magic_number;
u8 *entry;
int i;
struct nouveau_pm_memtiming *boot = &pm->boot.timing;
struct nouveau_pm_tbl_entry *e;
u8 ver, len, *ptr, *ramcfg;
int ret;
if (bios->type == NVBIOS_BIT) {
if (bit_table(dev, 'P', &P))
return;
ptr = nouveau_perf_timing(dev, freq, &ver, &len);
if (!ptr || ptr[0] == 0x00) {
*t = *boot;
return 0;
}
e = (struct nouveau_pm_tbl_entry *)ptr;
if (P.version == 1)
hdr = (struct nouveau_pm_tbl_header *) ROMPTR(dev, P.data[4]);
t->tCWL = boot->tCWL;
switch (dev_priv->card_type) {
case NV_40:
ret = nv40_mem_timing_calc(dev, freq, e, len, boot, t);
break;
case NV_50:
ret = nv50_mem_timing_calc(dev, freq, e, len, boot, t);
break;
case NV_C0:
ret = nvc0_mem_timing_calc(dev, freq, e, len, boot, t);
break;
default:
ret = -ENODEV;
break;
}
switch (dev_priv->vram_type * !ret) {
case NV_MEM_TYPE_GDDR3:
ret = nouveau_mem_gddr3_mr(dev, freq, e, len, boot, t);
break;
case NV_MEM_TYPE_GDDR5:
ret = nouveau_mem_gddr5_mr(dev, freq, e, len, boot, t);
break;
case NV_MEM_TYPE_DDR2:
ret = nouveau_mem_ddr2_mr(dev, freq, e, len, boot, t);
break;
case NV_MEM_TYPE_DDR3:
ret = nouveau_mem_ddr3_mr(dev, freq, e, len, boot, t);
break;
default:
ret = -EINVAL;
break;
}
ramcfg = nouveau_perf_ramcfg(dev, freq, &ver, &len);
if (ramcfg) {
int dll_off;
if (ver == 0x00)
dll_off = !!(ramcfg[3] & 0x04);
else
if (P.version == 2)
hdr = (struct nouveau_pm_tbl_header *) ROMPTR(dev, P.data[8]);
else {
NV_WARN(dev, "unknown mem for BIT P %d\n", P.version);
}
} else {
NV_DEBUG(dev, "BMP version too old for memory\n");
return;
}
dll_off = !!(ramcfg[2] & 0x40);
if (!hdr) {
NV_DEBUG(dev, "memory timing table pointer invalid\n");
return;
}
if (hdr->version != 0x10) {
NV_WARN(dev, "memory timing table 0x%02x unknown\n", hdr->version);
return;
}
/* validate record length */
if (hdr->entry_len < 15) {
NV_ERROR(dev, "mem timing table length unknown: %d\n", hdr->entry_len);
return;
}
/* parse vbios entries into common format */
memtimings->timing =
kcalloc(hdr->entry_cnt, sizeof(*memtimings->timing), GFP_KERNEL);
if (!memtimings->timing)
return;
/* Get "some number" from the timing reg for NV_40 and NV_50
* Used in calculations later... source unknown */
magic_number = 0;
if (P.version == 1) {
magic_number = (nv_rd32(dev, 0x100228) & 0x0f000000) >> 24;
}
entry = (u8*) hdr + hdr->header_len;
for (i = 0; i < hdr->entry_cnt; i++, entry += hdr->entry_len) {
struct nouveau_pm_memtiming *timing = &pm->memtimings.timing[i];
if (entry[0] == 0)
continue;
timing->id = i;
timing->WR = entry[0];
timing->CL = entry[2];
if(dev_priv->card_type <= NV_40) {
nv40_mem_timing_entry(dev,hdr,(struct nouveau_pm_tbl_entry*) entry,magic_number,&pm->memtimings.timing[i]);
} else if(dev_priv->card_type == NV_50){
nv50_mem_timing_entry(dev,&P,hdr,(struct nouveau_pm_tbl_entry*) entry,magic_number,&pm->memtimings.timing[i]);
} else if(dev_priv->card_type == NV_C0) {
nvc0_mem_timing_entry(dev,hdr,(struct nouveau_pm_tbl_entry*) entry,&pm->memtimings.timing[i]);
switch (dev_priv->vram_type) {
case NV_MEM_TYPE_GDDR3:
t->mr[1] &= ~0x00000040;
t->mr[1] |= 0x00000040 * dll_off;
break;
default:
t->mr[1] &= ~0x00000001;
t->mr[1] |= 0x00000001 * dll_off;
break;
}
}
memtimings->nr_timing = hdr->entry_cnt;
memtimings->supported = P.version == 1;
return ret;
}
void
nouveau_mem_timing_fini(struct drm_device *dev)
nouveau_mem_timing_read(struct drm_device *dev, struct nouveau_pm_memtiming *t)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
struct nouveau_pm_memtimings *mem = &dev_priv->engine.pm.memtimings;
u32 timing_base, timing_regs, mr_base;
int i;
if(mem->timing) {
kfree(mem->timing);
mem->timing = NULL;
if (dev_priv->card_type >= 0xC0) {
timing_base = 0x10f290;
mr_base = 0x10f300;
} else {
timing_base = 0x100220;
mr_base = 0x1002c0;
}
t->id = -1;
switch (dev_priv->card_type) {
case NV_50:
timing_regs = 9;
break;
case NV_C0:
case NV_D0:
timing_regs = 5;
break;
case NV_30:
case NV_40:
timing_regs = 3;
break;
default:
timing_regs = 0;
return;
}
for(i = 0; i < timing_regs; i++)
t->reg[i] = nv_rd32(dev, timing_base + (0x04 * i));
t->tCWL = 0;
if (dev_priv->card_type < NV_C0) {
t->tCWL = ((nv_rd32(dev, 0x100228) & 0x0f000000) >> 24) + 1;
} else if (dev_priv->card_type <= NV_D0) {
t->tCWL = ((nv_rd32(dev, 0x10f294) & 0x00000f80) >> 7);
}
t->mr[0] = nv_rd32(dev, mr_base);
t->mr[1] = nv_rd32(dev, mr_base + 0x04);
t->mr[2] = nv_rd32(dev, mr_base + 0x20);
t->mr[3] = nv_rd32(dev, mr_base + 0x24);
t->odt = 0;
t->drive_strength = 0;
switch (dev_priv->vram_type) {
case NV_MEM_TYPE_DDR3:
t->odt |= (t->mr[1] & 0x200) >> 7;
case NV_MEM_TYPE_DDR2:
t->odt |= (t->mr[1] & 0x04) >> 2 |
(t->mr[1] & 0x40) >> 5;
break;
case NV_MEM_TYPE_GDDR3:
case NV_MEM_TYPE_GDDR5:
t->drive_strength = t->mr[1] & 0x03;
t->odt = (t->mr[1] & 0x0c) >> 2;
break;
default:
break;
}
}
int
nouveau_mem_exec(struct nouveau_mem_exec_func *exec,
struct nouveau_pm_level *perflvl)
{
struct drm_nouveau_private *dev_priv = exec->dev->dev_private;
struct nouveau_pm_memtiming *info = &perflvl->timing;
u32 tMRD = 1000, tCKSRE = 0, tCKSRX = 0, tXS = 0, tDLLK = 0;
u32 mr[3] = { info->mr[0], info->mr[1], info->mr[2] };
u32 mr1_dlloff;
switch (dev_priv->vram_type) {
case NV_MEM_TYPE_DDR2:
tDLLK = 2000;
mr1_dlloff = 0x00000001;
break;
case NV_MEM_TYPE_DDR3:
tDLLK = 12000;
mr1_dlloff = 0x00000001;
break;
case NV_MEM_TYPE_GDDR3:
tDLLK = 40000;
mr1_dlloff = 0x00000040;
break;
default:
NV_ERROR(exec->dev, "cannot reclock unsupported memtype\n");
return -ENODEV;
}
/* fetch current MRs */
switch (dev_priv->vram_type) {
case NV_MEM_TYPE_GDDR3:
case NV_MEM_TYPE_DDR3:
mr[2] = exec->mrg(exec, 2);
default:
mr[1] = exec->mrg(exec, 1);
mr[0] = exec->mrg(exec, 0);
break;
}
/* DLL 'on' -> DLL 'off' mode, disable before entering self-refresh */
if (!(mr[1] & mr1_dlloff) && (info->mr[1] & mr1_dlloff)) {
exec->precharge(exec);
exec->mrs (exec, 1, mr[1] | mr1_dlloff);
exec->wait(exec, tMRD);
}
/* enter self-refresh mode */
exec->precharge(exec);
exec->refresh(exec);
exec->refresh(exec);
exec->refresh_auto(exec, false);
exec->refresh_self(exec, true);
exec->wait(exec, tCKSRE);
/* modify input clock frequency */
exec->clock_set(exec);
/* exit self-refresh mode */
exec->wait(exec, tCKSRX);
exec->precharge(exec);
exec->refresh_self(exec, false);
exec->refresh_auto(exec, true);
exec->wait(exec, tXS);
/* update MRs */
if (mr[2] != info->mr[2]) {
exec->mrs (exec, 2, info->mr[2]);
exec->wait(exec, tMRD);
}
if (mr[1] != info->mr[1]) {
/* need to keep DLL off until later, at least on GDDR3 */
exec->mrs (exec, 1, info->mr[1] | (mr[1] & mr1_dlloff));
exec->wait(exec, tMRD);
}
if (mr[0] != info->mr[0]) {
exec->mrs (exec, 0, info->mr[0]);
exec->wait(exec, tMRD);
}
/* update PFB timing registers */
exec->timing_set(exec);
/* DLL (enable + ) reset */
if (!(info->mr[1] & mr1_dlloff)) {
if (mr[1] & mr1_dlloff) {
exec->mrs (exec, 1, info->mr[1]);
exec->wait(exec, tMRD);
}
exec->mrs (exec, 0, info->mr[0] | 0x00000100);
exec->wait(exec, tMRD);
exec->mrs (exec, 0, info->mr[0] | 0x00000000);
exec->wait(exec, tMRD);
exec->wait(exec, tDLLK);
if (dev_priv->vram_type == NV_MEM_TYPE_GDDR3)
exec->precharge(exec);
}
return 0;
}
int
nouveau_mem_vbios_type(struct drm_device *dev)
{
struct bit_entry M;
u8 ramcfg = (nv_rd32(dev, 0x101000) & 0x0000003c) >> 2;
if (!bit_table(dev, 'M', &M) || M.version != 2 || M.length < 5) {
u8 *table = ROMPTR(dev, M.data[3]);
if (table && table[0] == 0x10 && ramcfg < table[3]) {
u8 *entry = table + table[1] + (ramcfg * table[2]);
switch (entry[0] & 0x0f) {
case 0: return NV_MEM_TYPE_DDR2;
case 1: return NV_MEM_TYPE_DDR3;
case 2: return NV_MEM_TYPE_GDDR3;
case 3: return NV_MEM_TYPE_GDDR5;
default:
break;
}
}
}
return NV_MEM_TYPE_UNKNOWN;
}
static int

39
drivers/gpu/drm/nouveau/nouveau_mxm.c
View File

@ -582,6 +582,35 @@ mxm_shadow_dsm(struct drm_device *dev, u8 version)
#define WMI_WMMX_GUID "F6CB5C3C-9CAE-4EBD-B577-931EA32A2CC0"
static u8
wmi_wmmx_mxmi(struct drm_device *dev, u8 version)
{
u32 mxmi_args[] = { 0x494D584D /* MXMI */, version, 0 };
struct acpi_buffer args = { sizeof(mxmi_args), mxmi_args };
struct acpi_buffer retn = { ACPI_ALLOCATE_BUFFER, NULL };
union acpi_object *obj;
acpi_status status;
status = wmi_evaluate_method(WMI_WMMX_GUID, 0, 0, &args, &retn);
if (ACPI_FAILURE(status)) {
MXM_DBG(dev, "WMMX MXMI returned %d\n", status);
return 0x00;
}
obj = retn.pointer;
if (obj->type == ACPI_TYPE_INTEGER) {
version = obj->integer.value;
MXM_DBG(dev, "WMMX MXMI version %d.%d\n",
(version >> 4), version & 0x0f);
} else {
version = 0;
MXM_DBG(dev, "WMMX MXMI returned non-integer\n");
}
kfree(obj);
return version;
}
static bool
mxm_shadow_wmi(struct drm_device *dev, u8 version)
{
@ -592,7 +621,15 @@ mxm_shadow_wmi(struct drm_device *dev, u8 version)
union acpi_object *obj;
acpi_status status;
if (!wmi_has_guid(WMI_WMMX_GUID))
if (!wmi_has_guid(WMI_WMMX_GUID)) {
MXM_DBG(dev, "WMMX GUID not found\n");
return false;
}
mxms_args[1] = wmi_wmmx_mxmi(dev, 0x00);
if (!mxms_args[1])
mxms_args[1] = wmi_wmmx_mxmi(dev, version);
if (!mxms_args[1])
return false;
status = wmi_evaluate_method(WMI_WMMX_GUID, 0, 0, &args, &retn);

409
drivers/gpu/drm/nouveau/nouveau_perf.c
View File

@ -27,6 +27,178 @@
#include "nouveau_drv.h"
#include "nouveau_pm.h"
static u8 *
nouveau_perf_table(struct drm_device *dev, u8 *ver)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
struct nvbios *bios = &dev_priv->vbios;
struct bit_entry P;
if (!bit_table(dev, 'P', &P) && P.version && P.version <= 2) {
u8 *perf = ROMPTR(dev, P.data[0]);
if (perf) {
*ver = perf[0];
return perf;
}
}
if (bios->type == NVBIOS_BMP) {
if (bios->data[bios->offset + 6] >= 0x25) {
u8 *perf = ROMPTR(dev, bios->data[bios->offset + 0x94]);
if (perf) {
*ver = perf[1];
return perf;
}
}
}
return NULL;
}
static u8 *
nouveau_perf_entry(struct drm_device *dev, int idx,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
{
u8 *perf = nouveau_perf_table(dev, ver);
if (perf) {
if (*ver >= 0x12 && *ver < 0x20 && idx < perf[2]) {
*hdr = perf[3];
*cnt = 0;
*len = 0;
return perf + perf[0] + idx * perf[3];
} else
if (*ver >= 0x20 && *ver < 0x40 && idx < perf[2]) {
*hdr = perf[3];
*cnt = perf[4];
*len = perf[5];
return perf + perf[1] + idx * (*hdr + (*cnt * *len));
} else
if (*ver >= 0x40 && *ver < 0x41 && idx < perf[5]) {
*hdr = perf[2];
*cnt = perf[4];
*len = perf[3];
return perf + perf[1] + idx * (*hdr + (*cnt * *len));
}
}
return NULL;
}
static u8 *
nouveau_perf_rammap(struct drm_device *dev, u32 freq,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
struct bit_entry P;
u8 *perf, i = 0;
if (!bit_table(dev, 'P', &P) && P.version == 2) {
u8 *rammap = ROMPTR(dev, P.data[4]);
if (rammap) {
u8 *ramcfg = rammap + rammap[1];
*ver = rammap[0];
*hdr = rammap[2];
*cnt = rammap[4];
*len = rammap[3];
freq /= 1000;
for (i = 0; i < rammap[5]; i++) {
if (freq >= ROM16(ramcfg[0]) &&
freq <= ROM16(ramcfg[2]))
return ramcfg;
ramcfg += *hdr + (*cnt * *len);
}
}
return NULL;
}
if (dev_priv->chipset == 0x49 ||
dev_priv->chipset == 0x4b)
freq /= 2;
while ((perf = nouveau_perf_entry(dev, i++, ver, hdr, cnt, len))) {
if (*ver >= 0x20 && *ver < 0x25) {
if (perf[0] != 0xff && freq <= ROM16(perf[11]) * 1000)
break;
} else
if (*ver >= 0x25 && *ver < 0x40) {
if (perf[0] != 0xff && freq <= ROM16(perf[12]) * 1000)
break;
}
}
if (perf) {
u8 *ramcfg = perf + *hdr;
*ver = 0x00;
*hdr = 0;
return ramcfg;
}
return NULL;
}
u8 *
nouveau_perf_ramcfg(struct drm_device *dev, u32 freq, u8 *ver, u8 *len)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
struct nvbios *bios = &dev_priv->vbios;
u8 strap, hdr, cnt;
u8 *rammap;
strap = (nv_rd32(dev, 0x101000) & 0x0000003c) >> 2;
if (bios->ram_restrict_tbl_ptr)
strap = bios->data[bios->ram_restrict_tbl_ptr + strap];
rammap = nouveau_perf_rammap(dev, freq, ver, &hdr, &cnt, len);
if (rammap && strap < cnt)
return rammap + hdr + (strap * *len);
return NULL;
}
u8 *
nouveau_perf_timing(struct drm_device *dev, u32 freq, u8 *ver, u8 *len)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
struct nvbios *bios = &dev_priv->vbios;
struct bit_entry P;
u8 *perf, *timing = NULL;
u8 i = 0, hdr, cnt;
if (bios->type == NVBIOS_BMP) {
while ((perf = nouveau_perf_entry(dev, i++, ver, &hdr, &cnt,
len)) && *ver == 0x15) {
if (freq <= ROM32(perf[5]) * 20) {
*ver = 0x00;
*len = 14;
return perf + 41;
}
}
return NULL;
}
if (!bit_table(dev, 'P', &P)) {
if (P.version == 1)
timing = ROMPTR(dev, P.data[4]);
else
if (P.version == 2)
timing = ROMPTR(dev, P.data[8]);
}
if (timing && timing[0] == 0x10) {
u8 *ramcfg = nouveau_perf_ramcfg(dev, freq, ver, len);
if (ramcfg && ramcfg[1] < timing[2]) {
*ver = timing[0];
*len = timing[3];
return timing + timing[1] + (ramcfg[1] * timing[3]);
}
}
return NULL;
}
static void
legacy_perf_init(struct drm_device *dev)
{
@ -72,74 +244,11 @@ legacy_perf_init(struct drm_device *dev)
pm->nr_perflvl = 1;
}
static struct nouveau_pm_memtiming *
nouveau_perf_timing(struct drm_device *dev, struct bit_entry *P,
u16 memclk, u8 *entry, u8 recordlen, u8 entries)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
struct nouveau_pm_engine *pm = &dev_priv->engine.pm;
struct nvbios *bios = &dev_priv->vbios;
u8 ramcfg;
int i;
/* perf v2 has a separate "timing map" table, we have to match
* the target memory clock to a specific entry, *then* use
* ramcfg to select the correct subentry
*/
if (P->version == 2) {
u8 *tmap = ROMPTR(dev, P->data[4]);
if (!tmap) {
NV_DEBUG(dev, "no timing map pointer\n");
return NULL;
}
if (tmap[0] != 0x10) {
NV_WARN(dev, "timing map 0x%02x unknown\n", tmap[0]);
return NULL;
}
entry = tmap + tmap[1];
recordlen = tmap[2] + (tmap[4] * tmap[3]);
for (i = 0; i < tmap[5]; i++, entry += recordlen) {
if (memclk >= ROM16(entry[0]) &&
memclk <= ROM16(entry[2]))
break;
}
if (i == tmap[5]) {
NV_WARN(dev, "no match in timing map table\n");
return NULL;
}
entry += tmap[2];
recordlen = tmap[3];
entries = tmap[4];
}
ramcfg = (nv_rd32(dev, NV_PEXTDEV_BOOT_0) & 0x0000003c) >> 2;
if (bios->ram_restrict_tbl_ptr)
ramcfg = bios->data[bios->ram_restrict_tbl_ptr + ramcfg];
if (ramcfg >= entries) {
NV_WARN(dev, "ramcfg strap out of bounds!\n");
return NULL;
}
entry += ramcfg * recordlen;
if (entry[1] >= pm->memtimings.nr_timing) {
if (entry[1] != 0xff)
NV_WARN(dev, "timingset %d does not exist\n", entry[1]);
return NULL;
}
return &pm->memtimings.timing[entry[1]];
}
static void
nouveau_perf_voltage(struct drm_device *dev, struct bit_entry *P,
struct nouveau_pm_level *perflvl)
nouveau_perf_voltage(struct drm_device *dev, struct nouveau_pm_level *perflvl)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
struct bit_entry P;
u8 *vmap;
int id;
@ -158,13 +267,13 @@ nouveau_perf_voltage(struct drm_device *dev, struct bit_entry *P,
/* on newer ones, the perflvl stores an index into yet another
* vbios table containing a min/max voltage value for the perflvl
*/
if (P->version != 2 || P->length < 34) {
if (bit_table(dev, 'P', &P) || P.version != 2 || P.length < 34) {
NV_DEBUG(dev, "where's our volt map table ptr? %d %d\n",
P->version, P->length);
P.version, P.length);
return;
}
vmap = ROMPTR(dev, P->data[32]);
vmap = ROMPTR(dev, P.data[32]);
if (!vmap) {
NV_DEBUG(dev, "volt map table pointer invalid\n");
return;
@ -183,130 +292,70 @@ nouveau_perf_init(struct drm_device *dev)
struct drm_nouveau_private *dev_priv = dev->dev_private;
struct nouveau_pm_engine *pm = &dev_priv->engine.pm;
struct nvbios *bios = &dev_priv->vbios;
struct bit_entry P;
struct nouveau_pm_memtimings *memtimings = &pm->memtimings;
struct nouveau_pm_tbl_header mt_hdr;
u8 version, headerlen, recordlen, entries;
u8 *perf, *entry;
int vid, i;
u8 *perf, ver, hdr, cnt, len;
int ret, vid, i = -1;
if (bios->type == NVBIOS_BIT) {
if (bit_table(dev, 'P', &P))
return;
if (P.version != 1 && P.version != 2) {
NV_WARN(dev, "unknown perf for BIT P %d\n", P.version);
return;
}
perf = ROMPTR(dev, P.data[0]);
version = perf[0];
headerlen = perf[1];
if (version < 0x40) {
recordlen = perf[3] + (perf[4] * perf[5]);
entries = perf[2];
pm->pwm_divisor = ROM16(perf[6]);
} else {
recordlen = perf[2] + (perf[3] * perf[4]);
entries = perf[5];
}
} else {
if (bios->data[bios->offset + 6] < 0x25) {
legacy_perf_init(dev);
return;
}
perf = ROMPTR(dev, bios->data[bios->offset + 0x94]);
if (!perf) {
NV_DEBUG(dev, "perf table pointer invalid\n");
return;
}
version = perf[1];
headerlen = perf[0];
recordlen = perf[3];
entries = perf[2];
if (bios->type == NVBIOS_BMP && bios->data[bios->offset + 6] < 0x25) {
legacy_perf_init(dev);
return;
}
if (entries > NOUVEAU_PM_MAX_LEVEL) {
NV_DEBUG(dev, "perf table has too many entries - buggy vbios?\n");
entries = NOUVEAU_PM_MAX_LEVEL;
}
perf = nouveau_perf_table(dev, &ver);
if (ver >= 0x20 && ver < 0x40)
pm->fan.pwm_divisor = ROM16(perf[6]);
entry = perf + headerlen;
/* For version 0x15, initialize memtiming table */
if(version == 0x15) {
memtimings->timing =
kcalloc(entries, sizeof(*memtimings->timing), GFP_KERNEL);
if (!memtimings->timing) {
NV_WARN(dev,"Could not allocate memtiming table\n");
return;
}
mt_hdr.entry_cnt = entries;
mt_hdr.entry_len = 14;
mt_hdr.version = version;
mt_hdr.header_len = 4;
}
for (i = 0; i < entries; i++) {
while ((perf = nouveau_perf_entry(dev, ++i, &ver, &hdr, &cnt, &len))) {
struct nouveau_pm_level *perflvl = &pm->perflvl[pm->nr_perflvl];
perflvl->timing = NULL;
if (entry[0] == 0xff) {
entry += recordlen;
if (perf[0] == 0xff)
continue;
}
switch (version) {
switch (ver) {
case 0x12:
case 0x13:
case 0x15:
perflvl->fanspeed = entry[55];
if (recordlen > 56)
perflvl->volt_min = entry[56];
perflvl->core = ROM32(entry[1]) * 10;
perflvl->memory = ROM32(entry[5]) * 20;
perflvl->fanspeed = perf[55];
if (hdr > 56)
perflvl->volt_min = perf[56];
perflvl->core = ROM32(perf[1]) * 10;
perflvl->memory = ROM32(perf[5]) * 20;
break;
case 0x21:
case 0x23:
case 0x24:
perflvl->fanspeed = entry[4];
perflvl->volt_min = entry[5];
perflvl->shader = ROM16(entry[6]) * 1000;
perflvl->fanspeed = perf[4];
perflvl->volt_min = perf[5];
perflvl->shader = ROM16(perf[6]) * 1000;
perflvl->core = perflvl->shader;
perflvl->core += (signed char)entry[8] * 1000;
perflvl->core += (signed char)perf[8] * 1000;
if (dev_priv->chipset == 0x49 ||
dev_priv->chipset == 0x4b)
perflvl->memory = ROM16(entry[11]) * 1000;
perflvl->memory = ROM16(perf[11]) * 1000;
else
perflvl->memory = ROM16(entry[11]) * 2000;
perflvl->memory = ROM16(perf[11]) * 2000;
break;
case 0x25:
perflvl->fanspeed = entry[4];
perflvl->volt_min = entry[5];
perflvl->core = ROM16(entry[6]) * 1000;
perflvl->shader = ROM16(entry[10]) * 1000;
perflvl->memory = ROM16(entry[12]) * 1000;
perflvl->fanspeed = perf[4];
perflvl->volt_min = perf[5];
perflvl->core = ROM16(perf[6]) * 1000;
perflvl->shader = ROM16(perf[10]) * 1000;
perflvl->memory = ROM16(perf[12]) * 1000;
break;
case 0x30:
perflvl->memscript = ROM16(entry[2]);
perflvl->memscript = ROM16(perf[2]);
case 0x35:
perflvl->fanspeed = entry[6];
perflvl->volt_min = entry[7];
perflvl->core = ROM16(entry[8]) * 1000;
perflvl->shader = ROM16(entry[10]) * 1000;
perflvl->memory = ROM16(entry[12]) * 1000;
perflvl->vdec = ROM16(entry[16]) * 1000;
perflvl->dom6 = ROM16(entry[20]) * 1000;
perflvl->fanspeed = perf[6];
perflvl->volt_min = perf[7];
perflvl->core = ROM16(perf[8]) * 1000;
perflvl->shader = ROM16(perf[10]) * 1000;
perflvl->memory = ROM16(perf[12]) * 1000;
perflvl->vdec = ROM16(perf[16]) * 1000;
perflvl->dom6 = ROM16(perf[20]) * 1000;
break;
case 0x40:
#define subent(n) (ROM16(entry[perf[2] + ((n) * perf[3])]) & 0xfff) * 1000
#define subent(n) ((ROM16(perf[hdr + (n) * len]) & 0xfff) * 1000)
perflvl->fanspeed = 0; /*XXX*/
perflvl->volt_min = entry[2];
perflvl->volt_min = perf[2];
if (dev_priv->card_type == NV_50) {
perflvl->core = subent(0);
perflvl->shader = subent(1);
@ -329,36 +378,34 @@ nouveau_perf_init(struct drm_device *dev)
}
/* make sure vid is valid */
nouveau_perf_voltage(dev, &P, perflvl);
nouveau_perf_voltage(dev, perflvl);
if (pm->voltage.supported && perflvl->volt_min) {
vid = nouveau_volt_vid_lookup(dev, perflvl->volt_min);
if (vid < 0) {
NV_DEBUG(dev, "drop perflvl %d, bad vid\n", i);
entry += recordlen;
NV_DEBUG(dev, "perflvl %d, bad vid\n", i);
continue;
}
}
/* get the corresponding memory timings */
if (version == 0x15) {
memtimings->timing[i].id = i;
nv30_mem_timing_entry(dev,&mt_hdr,(struct nouveau_pm_tbl_entry*) &entry[41],0,&memtimings->timing[i]);
perflvl->timing = &memtimings->timing[i];
} else if (version > 0x15) {
/* last 3 args are for < 0x40, ignored for >= 0x40 */
perflvl->timing =
nouveau_perf_timing(dev, &P,
perflvl->memory / 1000,
entry + perf[3],
perf[5], perf[4]);
ret = nouveau_mem_timing_calc(dev, perflvl->memory,
&perflvl->timing);
if (ret) {
NV_DEBUG(dev, "perflvl %d, bad timing: %d\n", i, ret);
continue;
}
snprintf(perflvl->name, sizeof(perflvl->name),
"performance_level_%d", i);
perflvl->id = i;
pm->nr_perflvl++;
entry += recordlen;
snprintf(perflvl->profile.name, sizeof(perflvl->profile.name),
"%d", perflvl->id);
perflvl->profile.func = &nouveau_pm_static_profile_func;
list_add_tail(&perflvl->profile.head, &pm->profiles);
pm->nr_perflvl++;
}
}

235
drivers/gpu/drm/nouveau/nouveau_pm.c
View File

@ -50,7 +50,7 @@ nouveau_pwmfan_get(struct drm_device *dev)
ret = nouveau_gpio_find(dev, 0, DCB_GPIO_PWM_FAN, 0xff, &gpio);
if (ret == 0) {
ret = pm->pwm_get(dev, gpio.line, &divs, &duty);
if (ret == 0) {
if (ret == 0 && divs) {
divs = max(divs, duty);
if (dev_priv->card_type <= NV_40 || (gpio.log[0] & 1))
duty = divs - duty;
@ -77,7 +77,7 @@ nouveau_pwmfan_set(struct drm_device *dev, int percent)
ret = nouveau_gpio_find(dev, 0, DCB_GPIO_PWM_FAN, 0xff, &gpio);
if (ret == 0) {
divs = pm->pwm_divisor;
divs = pm->fan.pwm_divisor;
if (pm->fan.pwm_freq) {
/*XXX: PNVIO clock more than likely... */
divs = 135000 / pm->fan.pwm_freq;
@ -89,7 +89,10 @@ nouveau_pwmfan_set(struct drm_device *dev, int percent)
if (dev_priv->card_type <= NV_40 || (gpio.log[0] & 1))
duty = divs - duty;
return pm->pwm_set(dev, gpio.line, divs, duty);
ret = pm->pwm_set(dev, gpio.line, divs, duty);
if (!ret)
pm->fan.percent = percent;
return ret;
}
return -ENODEV;
@ -144,9 +147,13 @@ nouveau_pm_perflvl_set(struct drm_device *dev, struct nouveau_pm_level *perflvl)
return ret;
state = pm->clocks_pre(dev, perflvl);
if (IS_ERR(state))
return PTR_ERR(state);
pm->clocks_set(dev, state);
if (IS_ERR(state)) {
ret = PTR_ERR(state);
goto error;
}
ret = pm->clocks_set(dev, state);
if (ret)
goto error;
ret = nouveau_pm_perflvl_aux(dev, perflvl, perflvl, pm->cur);
if (ret)
@ -154,6 +161,65 @@ nouveau_pm_perflvl_set(struct drm_device *dev, struct nouveau_pm_level *perflvl)
pm->cur = perflvl;
return 0;
error:
/* restore the fan speed and voltage before leaving */
nouveau_pm_perflvl_aux(dev, perflvl, perflvl, pm->cur);
return ret;
}
void
nouveau_pm_trigger(struct drm_device *dev)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
struct nouveau_pm_engine *pm = &dev_priv->engine.pm;
struct nouveau_pm_profile *profile = NULL;
struct nouveau_pm_level *perflvl = NULL;
int ret;
/* select power profile based on current power source */
if (power_supply_is_system_supplied())
profile = pm->profile_ac;
else
profile = pm->profile_dc;
if (profile != pm->profile) {
pm->profile->func->fini(pm->profile);
pm->profile = profile;
pm->profile->func->init(pm->profile);
}
/* select performance level based on profile */
perflvl = profile->func->select(profile);
/* change perflvl, if necessary */
if (perflvl != pm->cur) {
struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
u64 time0 = ptimer->read(dev);
NV_INFO(dev, "setting performance level: %d", perflvl->id);
ret = nouveau_pm_perflvl_set(dev, perflvl);
if (ret)
NV_INFO(dev, "> reclocking failed: %d\n\n", ret);
NV_INFO(dev, "> reclocking took %lluns\n\n",
ptimer->read(dev) - time0);
}
}
static struct nouveau_pm_profile *
profile_find(struct drm_device *dev, const char *string)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
struct nouveau_pm_engine *pm = &dev_priv->engine.pm;
struct nouveau_pm_profile *profile;
list_for_each_entry(profile, &pm->profiles, head) {
if (!strncmp(profile->name, string, sizeof(profile->name)))
return profile;
}
return NULL;
}
static int
@ -161,33 +227,54 @@ nouveau_pm_profile_set(struct drm_device *dev, const char *profile)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
struct nouveau_pm_engine *pm = &dev_priv->engine.pm;
struct nouveau_pm_level *perflvl = NULL;
struct nouveau_pm_profile *ac = NULL, *dc = NULL;
char string[16], *cur = string, *ptr;
/* safety precaution, for now */
if (nouveau_perflvl_wr != 7777)
return -EPERM;
if (!strncmp(profile, "boot", 4))
perflvl = &pm->boot;
else {
int pl = simple_strtol(profile, NULL, 10);
int i;
strncpy(string, profile, sizeof(string));
if ((ptr = strchr(string, '\n')))
*ptr = '\0';
for (i = 0; i < pm->nr_perflvl; i++) {
if (pm->perflvl[i].id == pl) {
perflvl = &pm->perflvl[i];
break;
}
}
ptr = strsep(&cur, ",");
if (ptr)
ac = profile_find(dev, ptr);
if (!perflvl)
return -EINVAL;
}
ptr = strsep(&cur, ",");
if (ptr)
dc = profile_find(dev, ptr);
else
dc = ac;
NV_INFO(dev, "setting performance level: %s\n", profile);
return nouveau_pm_perflvl_set(dev, perflvl);
if (ac == NULL || dc == NULL)
return -EINVAL;
pm->profile_ac = ac;
pm->profile_dc = dc;
nouveau_pm_trigger(dev);
return 0;
}
static void
nouveau_pm_static_dummy(struct nouveau_pm_profile *profile)
{
}
static struct nouveau_pm_level *
nouveau_pm_static_select(struct nouveau_pm_profile *profile)
{
return container_of(profile, struct nouveau_pm_level, profile);
}
const struct nouveau_pm_profile_func nouveau_pm_static_profile_func = {
.destroy = nouveau_pm_static_dummy,
.init = nouveau_pm_static_dummy,
.fini = nouveau_pm_static_dummy,
.select = nouveau_pm_static_select,
};
static int
nouveau_pm_perflvl_get(struct drm_device *dev, struct nouveau_pm_level *perflvl)
{
@ -197,9 +284,11 @@ nouveau_pm_perflvl_get(struct drm_device *dev, struct nouveau_pm_level *perflvl)
memset(perflvl, 0, sizeof(*perflvl));
ret = pm->clocks_get(dev, perflvl);
if (ret)
return ret;
if (pm->clocks_get) {
ret = pm->clocks_get(dev, perflvl);
if (ret)
return ret;
}
if (pm->voltage.supported && pm->voltage_get) {
ret = pm->voltage_get(dev);
@ -213,13 +302,14 @@ nouveau_pm_perflvl_get(struct drm_device *dev, struct nouveau_pm_level *perflvl)
if (ret > 0)
perflvl->fanspeed = ret;
nouveau_mem_timing_read(dev, &perflvl->timing);
return 0;
}
static void
nouveau_pm_perflvl_info(struct nouveau_pm_level *perflvl, char *ptr, int len)
{
char c[16], s[16], v[32], f[16], t[16], m[16];
char c[16], s[16], v[32], f[16], m[16];
c[0] = '\0';
if (perflvl->core)
@ -247,18 +337,15 @@ nouveau_pm_perflvl_info(struct nouveau_pm_level *perflvl, char *ptr, int len)
if (perflvl->fanspeed)
snprintf(f, sizeof(f), " fanspeed %d%%", perflvl->fanspeed);
t[0] = '\0';
if (perflvl->timing)
snprintf(t, sizeof(t), " timing %d", perflvl->timing->id);
snprintf(ptr, len, "%s%s%s%s%s%s\n", c, s, m, t, v, f);
snprintf(ptr, len, "%s%s%s%s%s\n", c, s, m, v, f);
}
static ssize_t
nouveau_pm_get_perflvl_info(struct device *d,
struct device_attribute *a, char *buf)
{
struct nouveau_pm_level *perflvl = (struct nouveau_pm_level *)a;
struct nouveau_pm_level *perflvl =
container_of(a, struct nouveau_pm_level, dev_attr);
char *ptr = buf;
int len = PAGE_SIZE;
@ -280,12 +367,8 @@ nouveau_pm_get_perflvl(struct device *d, struct device_attribute *a, char *buf)
int len = PAGE_SIZE, ret;
char *ptr = buf;
if (!pm->cur)
snprintf(ptr, len, "setting: boot\n");
else if (pm->cur == &pm->boot)
snprintf(ptr, len, "setting: boot\nc:");
else
snprintf(ptr, len, "setting: static %d\nc:", pm->cur->id);
snprintf(ptr, len, "profile: %s, %s\nc:",
pm->profile_ac->name, pm->profile_dc->name);
ptr += strlen(buf);
len -= strlen(buf);
@ -397,7 +480,7 @@ nouveau_hwmon_set_max_temp(struct device *d, struct device_attribute *a,
struct nouveau_pm_threshold_temp *temp = &pm->threshold_temp;
long value;
if (strict_strtol(buf, 10, &value) == -EINVAL)
if (kstrtol(buf, 10, &value) == -EINVAL)
return count;
temp->down_clock = value/1000;
@ -432,7 +515,7 @@ nouveau_hwmon_set_critical_temp(struct device *d, struct device_attribute *a,
struct nouveau_pm_threshold_temp *temp = &pm->threshold_temp;
long value;
if (strict_strtol(buf, 10, &value) == -EINVAL)
if (kstrtol(buf, 10, &value) == -EINVAL)
return count;
temp->critical = value/1000;
@ -529,7 +612,7 @@ nouveau_hwmon_set_pwm0(struct device *d, struct device_attribute *a,
if (nouveau_perflvl_wr != 7777)
return -EPERM;
if (strict_strtol(buf, 10, &value) == -EINVAL)
if (kstrtol(buf, 10, &value) == -EINVAL)
return -EINVAL;
if (value < pm->fan.min_duty)
@ -568,7 +651,7 @@ nouveau_hwmon_set_pwm0_min(struct device *d, struct device_attribute *a,
struct nouveau_pm_engine *pm = &dev_priv->engine.pm;
long value;
if (strict_strtol(buf, 10, &value) == -EINVAL)
if (kstrtol(buf, 10, &value) == -EINVAL)
return -EINVAL;
if (value < 0)
@ -609,7 +692,7 @@ nouveau_hwmon_set_pwm0_max(struct device *d, struct device_attribute *a,
struct nouveau_pm_engine *pm = &dev_priv->engine.pm;
long value;
if (strict_strtol(buf, 10, &value) == -EINVAL)
if (kstrtol(buf, 10, &value) == -EINVAL)
return -EINVAL;
if (value < 0)
@ -731,8 +814,10 @@ nouveau_hwmon_fini(struct drm_device *dev)
if (pm->hwmon) {
sysfs_remove_group(&dev->pdev->dev.kobj, &hwmon_attrgroup);
sysfs_remove_group(&dev->pdev->dev.kobj, &hwmon_pwm_fan_attrgroup);
sysfs_remove_group(&dev->pdev->dev.kobj, &hwmon_fan_rpm_attrgroup);
sysfs_remove_group(&dev->pdev->dev.kobj,
&hwmon_pwm_fan_attrgroup);
sysfs_remove_group(&dev->pdev->dev.kobj,
&hwmon_fan_rpm_attrgroup);
hwmon_device_unregister(pm->hwmon);
}
@ -752,6 +837,7 @@ nouveau_pm_acpi_event(struct notifier_block *nb, unsigned long val, void *data)
bool ac = power_supply_is_system_supplied();
NV_DEBUG(dev, "power supply changed: %s\n", ac ? "AC" : "DC");
nouveau_pm_trigger(dev);
}
return NOTIFY_OK;
@ -766,35 +852,48 @@ nouveau_pm_init(struct drm_device *dev)
char info[256];
int ret, i;
nouveau_mem_timing_init(dev);
/* parse aux tables from vbios */
nouveau_volt_init(dev);
nouveau_perf_init(dev);
nouveau_temp_init(dev);
/* determine current ("boot") performance level */
ret = nouveau_pm_perflvl_get(dev, &pm->boot);
if (ret) {
NV_ERROR(dev, "failed to determine boot perflvl\n");
return ret;
}
strncpy(pm->boot.name, "boot", 4);
strncpy(pm->boot.profile.name, "boot", 4);
pm->boot.profile.func = &nouveau_pm_static_profile_func;
INIT_LIST_HEAD(&pm->profiles);
list_add(&pm->boot.profile.head, &pm->profiles);
pm->profile_ac = &pm->boot.profile;
pm->profile_dc = &pm->boot.profile;
pm->profile = &pm->boot.profile;
pm->cur = &pm->boot;
/* add performance levels from vbios */
nouveau_perf_init(dev);
/* display available performance levels */
NV_INFO(dev, "%d available performance level(s)\n", pm->nr_perflvl);
for (i = 0; i < pm->nr_perflvl; i++) {
nouveau_pm_perflvl_info(&pm->perflvl[i], info, sizeof(info));
NV_INFO(dev, "%d:%s", pm->perflvl[i].id, info);
}
/* determine current ("boot") performance level */
ret = nouveau_pm_perflvl_get(dev, &pm->boot);
if (ret == 0) {
strncpy(pm->boot.name, "boot", 4);
pm->cur = &pm->boot;
nouveau_pm_perflvl_info(&pm->boot, info, sizeof(info));
NV_INFO(dev, "c:%s", info);
}
nouveau_pm_perflvl_info(&pm->boot, info, sizeof(info));
NV_INFO(dev, "c:%s", info);
/* switch performance levels now if requested */
if (nouveau_perflvl != NULL) {
ret = nouveau_pm_profile_set(dev, nouveau_perflvl);
if (ret) {
NV_ERROR(dev, "error setting perflvl \"%s\": %d\n",
nouveau_perflvl, ret);
}
}
if (nouveau_perflvl != NULL)
nouveau_pm_profile_set(dev, nouveau_perflvl);
/* determine the current fan speed */
pm->fan.percent = nouveau_pwmfan_get(dev);
nouveau_sysfs_init(dev);
nouveau_hwmon_init(dev);
@ -811,6 +910,12 @@ nouveau_pm_fini(struct drm_device *dev)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
struct nouveau_pm_engine *pm = &dev_priv->engine.pm;
struct nouveau_pm_profile *profile, *tmp;
list_for_each_entry_safe(profile, tmp, &pm->profiles, head) {
list_del(&profile->head);
profile->func->destroy(profile);
}
if (pm->cur != &pm->boot)
nouveau_pm_perflvl_set(dev, &pm->boot);
@ -818,7 +923,6 @@ nouveau_pm_fini(struct drm_device *dev)
nouveau_temp_fini(dev);
nouveau_perf_fini(dev);
nouveau_volt_fini(dev);
nouveau_mem_timing_fini(dev);
#if defined(CONFIG_ACPI) && defined(CONFIG_POWER_SUPPLY)
unregister_acpi_notifier(&pm->acpi_nb);
@ -840,4 +944,5 @@ nouveau_pm_resume(struct drm_device *dev)
perflvl = pm->cur;
pm->cur = &pm->boot;
nouveau_pm_perflvl_set(dev, perflvl);
nouveau_pwmfan_set(dev, pm->fan.percent);
}

22
drivers/gpu/drm/nouveau/nouveau_pm.h
View File

@ -25,10 +25,30 @@
#ifndef __NOUVEAU_PM_H__
#define __NOUVEAU_PM_H__
struct nouveau_mem_exec_func {
struct drm_device *dev;
void (*precharge)(struct nouveau_mem_exec_func *);
void (*refresh)(struct nouveau_mem_exec_func *);
void (*refresh_auto)(struct nouveau_mem_exec_func *, bool);
void (*refresh_self)(struct nouveau_mem_exec_func *, bool);
void (*wait)(struct nouveau_mem_exec_func *, u32 nsec);
u32 (*mrg)(struct nouveau_mem_exec_func *, int mr);
void (*mrs)(struct nouveau_mem_exec_func *, int mr, u32 data);
void (*clock_set)(struct nouveau_mem_exec_func *);
void (*timing_set)(struct nouveau_mem_exec_func *);
void *priv;
};
/* nouveau_mem.c */
int nouveau_mem_exec(struct nouveau_mem_exec_func *,
struct nouveau_pm_level *);
/* nouveau_pm.c */
int nouveau_pm_init(struct drm_device *dev);
void nouveau_pm_fini(struct drm_device *dev);
void nouveau_pm_resume(struct drm_device *dev);
extern const struct nouveau_pm_profile_func nouveau_pm_static_profile_func;
void nouveau_pm_trigger(struct drm_device *dev);
/* nouveau_volt.c */
void nouveau_volt_init(struct drm_device *);
@ -41,6 +61,8 @@ int nouveau_voltage_gpio_set(struct drm_device *, int voltage);
/* nouveau_perf.c */
void nouveau_perf_init(struct drm_device *);
void nouveau_perf_fini(struct drm_device *);
u8 *nouveau_perf_timing(struct drm_device *, u32 freq, u8 *ver, u8 *len);
u8 *nouveau_perf_ramcfg(struct drm_device *, u32 freq, u8 *ver, u8 *len);
/* nouveau_mem.c */
void nouveau_mem_timing_init(struct drm_device *);

232
drivers/gpu/drm/nouveau/nouveau_state.c
View File

@ -87,7 +87,7 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
engine->pm.clocks_get = nv04_pm_clocks_get;
engine->pm.clocks_pre = nv04_pm_clocks_pre;
engine->pm.clocks_set = nv04_pm_clocks_set;
engine->vram.init = nouveau_mem_detect;
engine->vram.init = nv04_fb_vram_init;
engine->vram.takedown = nouveau_stub_takedown;
engine->vram.flags_valid = nouveau_mem_flags_valid;
break;
@ -134,7 +134,11 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
engine->pm.clocks_get = nv04_pm_clocks_get;
engine->pm.clocks_pre = nv04_pm_clocks_pre;
engine->pm.clocks_set = nv04_pm_clocks_set;
engine->vram.init = nouveau_mem_detect;
if (dev_priv->chipset == 0x1a ||
dev_priv->chipset == 0x1f)
engine->vram.init = nv1a_fb_vram_init;
else
engine->vram.init = nv10_fb_vram_init;
engine->vram.takedown = nouveau_stub_takedown;
engine->vram.flags_valid = nouveau_mem_flags_valid;
break;
@ -153,11 +157,11 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
engine->timer.init = nv04_timer_init;
engine->timer.read = nv04_timer_read;
engine->timer.takedown = nv04_timer_takedown;
engine->fb.init = nv10_fb_init;
engine->fb.takedown = nv10_fb_takedown;
engine->fb.init_tile_region = nv10_fb_init_tile_region;
engine->fb.set_tile_region = nv10_fb_set_tile_region;
engine->fb.free_tile_region = nv10_fb_free_tile_region;
engine->fb.init = nv20_fb_init;
engine->fb.takedown = nv20_fb_takedown;
engine->fb.init_tile_region = nv20_fb_init_tile_region;
engine->fb.set_tile_region = nv20_fb_set_tile_region;
engine->fb.free_tile_region = nv20_fb_free_tile_region;
engine->fifo.channels = 32;
engine->fifo.init = nv10_fifo_init;
engine->fifo.takedown = nv04_fifo_fini;
@ -181,7 +185,7 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
engine->pm.clocks_get = nv04_pm_clocks_get;
engine->pm.clocks_pre = nv04_pm_clocks_pre;
engine->pm.clocks_set = nv04_pm_clocks_set;
engine->vram.init = nouveau_mem_detect;
engine->vram.init = nv20_fb_vram_init;
engine->vram.takedown = nouveau_stub_takedown;
engine->vram.flags_valid = nouveau_mem_flags_valid;
break;
@ -230,7 +234,7 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
engine->pm.clocks_set = nv04_pm_clocks_set;
engine->pm.voltage_get = nouveau_voltage_gpio_get;
engine->pm.voltage_set = nouveau_voltage_gpio_set;
engine->vram.init = nouveau_mem_detect;
engine->vram.init = nv20_fb_vram_init;
engine->vram.takedown = nouveau_stub_takedown;
engine->vram.flags_valid = nouveau_mem_flags_valid;
break;
@ -286,7 +290,7 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
engine->pm.temp_get = nv40_temp_get;
engine->pm.pwm_get = nv40_pm_pwm_get;
engine->pm.pwm_set = nv40_pm_pwm_set;
engine->vram.init = nouveau_mem_detect;
engine->vram.init = nv40_fb_vram_init;
engine->vram.takedown = nouveau_stub_takedown;
engine->vram.flags_valid = nouveau_mem_flags_valid;
break;
@ -588,16 +592,34 @@ nouveau_card_init(struct drm_device *dev)
nv_mask(dev, 0x00088080, 0x00000800, 0x00000000);
}
nouveau_pm_init(dev);
ret = engine->vram.init(dev);
/* PMC */
ret = engine->mc.init(dev);
if (ret)
goto out_bios;
ret = nouveau_gpuobj_init(dev);
/* PTIMER */
ret = engine->timer.init(dev);
if (ret)
goto out_mc;
/* PFB */
ret = engine->fb.init(dev);
if (ret)
goto out_timer;
ret = engine->vram.init(dev);
if (ret)
goto out_fb;
/* PGPIO */
ret = nouveau_gpio_create(dev);
if (ret)
goto out_vram;
ret = nouveau_gpuobj_init(dev);
if (ret)
goto out_gpio;
ret = engine->instmem.init(dev);
if (ret)
goto out_gpuobj;
@ -610,26 +632,6 @@ nouveau_card_init(struct drm_device *dev)
if (ret)
goto out_ttmvram;
/* PMC */
ret = engine->mc.init(dev);
if (ret)
goto out_gart;
/* PGPIO */
ret = nouveau_gpio_create(dev);
if (ret)
goto out_mc;
/* PTIMER */
ret = engine->timer.init(dev);
if (ret)
goto out_gpio;
/* PFB */
ret = engine->fb.init(dev);
if (ret)
goto out_timer;
if (!dev_priv->noaccel) {
switch (dev_priv->card_type) {
case NV_04:
@ -734,11 +736,12 @@ nouveau_card_init(struct drm_device *dev)
goto out_irq;
nouveau_backlight_init(dev);
nouveau_pm_init(dev);
if (dev_priv->eng[NVOBJ_ENGINE_GR]) {
ret = nouveau_fence_init(dev);
if (ret)
goto out_disp;
goto out_pm;
ret = nouveau_channel_alloc(dev, &dev_priv->channel, NULL,
NvDmaFB, NvDmaTT);
@ -762,7 +765,8 @@ out_chan:
nouveau_channel_put_unlocked(&dev_priv->channel);
out_fence:
nouveau_fence_fini(dev);
out_disp:
out_pm:
nouveau_pm_fini(dev);
nouveau_backlight_exit(dev);
nouveau_display_destroy(dev);
out_irq:
@ -779,15 +783,6 @@ out_engine:
dev_priv->eng[e]->destroy(dev,e );
}
}
engine->fb.takedown(dev);
out_timer:
engine->timer.takedown(dev);
out_gpio:
nouveau_gpio_destroy(dev);
out_mc:
engine->mc.takedown(dev);
out_gart:
nouveau_mem_gart_fini(dev);
out_ttmvram:
nouveau_mem_vram_fini(dev);
@ -795,10 +790,17 @@ out_instmem:
engine->instmem.takedown(dev);
out_gpuobj:
nouveau_gpuobj_takedown(dev);
out_gpio:
nouveau_gpio_destroy(dev);
out_vram:
engine->vram.takedown(dev);
out_fb:
engine->fb.takedown(dev);
out_timer:
engine->timer.takedown(dev);
out_mc:
engine->mc.takedown(dev);
out_bios:
nouveau_pm_fini(dev);
nouveau_bios_takedown(dev);
out_display_early:
engine->display.late_takedown(dev);
@ -823,6 +825,7 @@ static void nouveau_card_takedown(struct drm_device *dev)
nouveau_fence_fini(dev);
}
nouveau_pm_fini(dev);
nouveau_backlight_exit(dev);
nouveau_display_destroy(dev);
@ -835,11 +838,6 @@ static void nouveau_card_takedown(struct drm_device *dev)
}
}
}
engine->fb.takedown(dev);
engine->timer.takedown(dev);
nouveau_gpio_destroy(dev);
engine->mc.takedown(dev);
engine->display.late_takedown(dev);
if (dev_priv->vga_ram) {
nouveau_bo_unpin(dev_priv->vga_ram);
@ -855,13 +853,18 @@ static void nouveau_card_takedown(struct drm_device *dev)
engine->instmem.takedown(dev);
nouveau_gpuobj_takedown(dev);
nouveau_gpio_destroy(dev);
engine->vram.takedown(dev);
engine->fb.takedown(dev);
engine->timer.takedown(dev);
engine->mc.takedown(dev);
nouveau_bios_takedown(dev);
engine->display.late_takedown(dev);
nouveau_irq_fini(dev);
nouveau_pm_fini(dev);
nouveau_bios_takedown(dev);
vga_client_register(dev->pdev, NULL, NULL, NULL);
}
@ -990,7 +993,7 @@ static int nouveau_remove_conflicting_drivers(struct drm_device *dev)
int nouveau_load(struct drm_device *dev, unsigned long flags)
{
struct drm_nouveau_private *dev_priv;
uint32_t reg0, strap;
uint32_t reg0 = ~0, strap;
resource_size_t mmio_start_offs;
int ret;
@ -1009,10 +1012,65 @@ int nouveau_load(struct drm_device *dev, unsigned long flags)
NV_DEBUG(dev, "vendor: 0x%X device: 0x%X class: 0x%X\n",
dev->pci_vendor, dev->pci_device, dev->pdev->class);
/* resource 0 is mmio regs */
/* resource 1 is linear FB */
/* resource 2 is RAMIN (mmio regs + 0x1000000) */
/* resource 6 is bios */
/* first up, map the start of mmio and determine the chipset */
dev_priv->mmio = ioremap(pci_resource_start(dev->pdev, 0), PAGE_SIZE);
if (dev_priv->mmio) {
#ifdef __BIG_ENDIAN
/* put the card into big-endian mode if it's not */
if (nv_rd32(dev, NV03_PMC_BOOT_1) != 0x01000001)
nv_wr32(dev, NV03_PMC_BOOT_1, 0x01000001);
DRM_MEMORYBARRIER();
#endif
/* determine chipset and derive architecture from it */
reg0 = nv_rd32(dev, NV03_PMC_BOOT_0);
if ((reg0 & 0x0f000000) > 0) {
dev_priv->chipset = (reg0 & 0xff00000) >> 20;
switch (dev_priv->chipset & 0xf0) {
case 0x10:
case 0x20:
case 0x30:
dev_priv->card_type = dev_priv->chipset & 0xf0;
break;
case 0x40:
case 0x60:
dev_priv->card_type = NV_40;
break;
case 0x50:
case 0x80:
case 0x90:
case 0xa0:
dev_priv->card_type = NV_50;
break;
case 0xc0:
dev_priv->card_type = NV_C0;
break;
case 0xd0:
dev_priv->card_type = NV_D0;
break;
default:
break;
}
} else
if ((reg0 & 0xff00fff0) == 0x20004000) {
if (reg0 & 0x00f00000)
dev_priv->chipset = 0x05;
else
dev_priv->chipset = 0x04;
dev_priv->card_type = NV_04;
}
iounmap(dev_priv->mmio);
}
if (!dev_priv->card_type) {
NV_ERROR(dev, "unsupported chipset 0x%08x\n", reg0);
ret = -EINVAL;
goto err_priv;
}
NV_INFO(dev, "Detected an NV%2x generation card (0x%08x)\n",
dev_priv->card_type, reg0);
/* map the mmio regs */
mmio_start_offs = pci_resource_start(dev->pdev, 0);
@ -1026,62 +1084,6 @@ int nouveau_load(struct drm_device *dev, unsigned long flags)
NV_DEBUG(dev, "regs mapped ok at 0x%llx\n",
(unsigned long long)mmio_start_offs);
#ifdef __BIG_ENDIAN
/* Put the card in BE mode if it's not */
if (nv_rd32(dev, NV03_PMC_BOOT_1) != 0x01000001)
nv_wr32(dev, NV03_PMC_BOOT_1, 0x01000001);
DRM_MEMORYBARRIER();
#endif
/* Time to determine the card architecture */
reg0 = nv_rd32(dev, NV03_PMC_BOOT_0);
/* We're dealing with >=NV10 */
if ((reg0 & 0x0f000000) > 0) {
/* Bit 27-20 contain the architecture in hex */
dev_priv->chipset = (reg0 & 0xff00000) >> 20;
/* NV04 or NV05 */
} else if ((reg0 & 0xff00fff0) == 0x20004000) {
if (reg0 & 0x00f00000)
dev_priv->chipset = 0x05;
else
dev_priv->chipset = 0x04;
} else
dev_priv->chipset = 0xff;
switch (dev_priv->chipset & 0xf0) {
case 0x00:
case 0x10:
case 0x20:
case 0x30:
dev_priv->card_type = dev_priv->chipset & 0xf0;
break;
case 0x40:
case 0x60:
dev_priv->card_type = NV_40;
break;
case 0x50:
case 0x80:
case 0x90:
case 0xa0:
dev_priv->card_type = NV_50;
break;
case 0xc0:
dev_priv->card_type = NV_C0;
break;
case 0xd0:
dev_priv->card_type = NV_D0;
break;
default:
NV_INFO(dev, "Unsupported chipset 0x%08x\n", reg0);
ret = -EINVAL;
goto err_mmio;
}
NV_INFO(dev, "Detected an NV%2x generation card (0x%08x)\n",
dev_priv->card_type, reg0);
/* determine frequency of timing crystal */
strap = nv_rd32(dev, 0x101000);
if ( dev_priv->chipset < 0x17 ||

34
drivers/gpu/drm/nouveau/nv04_fb.c
View File

@ -3,6 +3,40 @@
#include "nouveau_drv.h"
#include "nouveau_drm.h"
int
nv04_fb_vram_init(struct drm_device *dev)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
u32 boot0 = nv_rd32(dev, NV04_PFB_BOOT_0);
if (boot0 & 0x00000100) {
dev_priv->vram_size = ((boot0 >> 12) & 0xf) * 2 + 2;
dev_priv->vram_size *= 1024 * 1024;
} else {
switch (boot0 & NV04_PFB_BOOT_0_RAM_AMOUNT) {
case NV04_PFB_BOOT_0_RAM_AMOUNT_32MB:
dev_priv->vram_size = 32 * 1024 * 1024;
break;
case NV04_PFB_BOOT_0_RAM_AMOUNT_16MB:
dev_priv->vram_size = 16 * 1024 * 1024;
break;
case NV04_PFB_BOOT_0_RAM_AMOUNT_8MB:
dev_priv->vram_size = 8 * 1024 * 1024;
break;
case NV04_PFB_BOOT_0_RAM_AMOUNT_4MB:
dev_priv->vram_size = 4 * 1024 * 1024;
break;
}
}
if ((boot0 & 0x00000038) <= 0x10)
dev_priv->vram_type = NV_MEM_TYPE_SGRAM;
else
dev_priv->vram_type = NV_MEM_TYPE_SDRAM;
return 0;
}
int
nv04_fb_init(struct drm_device *dev)
{

126
drivers/gpu/drm/nouveau/nv10_fb.c
View File

@ -3,81 +3,16 @@
#include "nouveau_drv.h"
#include "nouveau_drm.h"
static struct drm_mm_node *
nv20_fb_alloc_tag(struct drm_device *dev, uint32_t size)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
struct drm_mm_node *mem;
int ret;
ret = drm_mm_pre_get(&pfb->tag_heap);
if (ret)
return NULL;
spin_lock(&dev_priv->tile.lock);
mem = drm_mm_search_free(&pfb->tag_heap, size, 0, 0);
if (mem)
mem = drm_mm_get_block_atomic(mem, size, 0);
spin_unlock(&dev_priv->tile.lock);
return mem;
}
static void
nv20_fb_free_tag(struct drm_device *dev, struct drm_mm_node *mem)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
spin_lock(&dev_priv->tile.lock);
drm_mm_put_block(mem);
spin_unlock(&dev_priv->tile.lock);
}
void
nv10_fb_init_tile_region(struct drm_device *dev, int i, uint32_t addr,
uint32_t size, uint32_t pitch, uint32_t flags)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i];
int bpp = (flags & NOUVEAU_GEM_TILE_32BPP ? 32 : 16);
tile->addr = addr;
tile->addr = 0x80000000 | addr;
tile->limit = max(1u, addr + size) - 1;
tile->pitch = pitch;
if (dev_priv->card_type == NV_20) {
if (flags & NOUVEAU_GEM_TILE_ZETA) {
/*
* Allocate some of the on-die tag memory,
* used to store Z compression meta-data (most
* likely just a bitmap determining if a given
* tile is compressed or not).
*/
tile->tag_mem = nv20_fb_alloc_tag(dev, size / 256);
if (tile->tag_mem) {
/* Enable Z compression */
if (dev_priv->chipset >= 0x25)
tile->zcomp = tile->tag_mem->start |
(bpp == 16 ?
NV25_PFB_ZCOMP_MODE_16 :
NV25_PFB_ZCOMP_MODE_32);
else
tile->zcomp = tile->tag_mem->start |
NV20_PFB_ZCOMP_EN |
(bpp == 16 ? 0 :
NV20_PFB_ZCOMP_MODE_32);
}
tile->addr |= 3;
} else {
tile->addr |= 1;
}
} else {
tile->addr |= 1 << 31;
}
}
void
@ -86,11 +21,6 @@ nv10_fb_free_tile_region(struct drm_device *dev, int i)
struct drm_nouveau_private *dev_priv = dev->dev_private;
struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i];
if (tile->tag_mem) {
nv20_fb_free_tag(dev, tile->tag_mem);
tile->tag_mem = NULL;
}
tile->addr = tile->limit = tile->pitch = tile->zcomp = 0;
}
@ -103,9 +33,48 @@ nv10_fb_set_tile_region(struct drm_device *dev, int i)
nv_wr32(dev, NV10_PFB_TLIMIT(i), tile->limit);
nv_wr32(dev, NV10_PFB_TSIZE(i), tile->pitch);
nv_wr32(dev, NV10_PFB_TILE(i), tile->addr);
}
if (dev_priv->card_type == NV_20)
nv_wr32(dev, NV20_PFB_ZCOMP(i), tile->zcomp);
int
nv1a_fb_vram_init(struct drm_device *dev)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
struct pci_dev *bridge;
uint32_t mem, mib;
bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 1));
if (!bridge) {
NV_ERROR(dev, "no bridge device\n");
return 0;
}
if (dev_priv->chipset == 0x1a) {
pci_read_config_dword(bridge, 0x7c, &mem);
mib = ((mem >> 6) & 31) + 1;
} else {
pci_read_config_dword(bridge, 0x84, &mem);
mib = ((mem >> 4) & 127) + 1;
}
dev_priv->vram_size = mib * 1024 * 1024;
return 0;
}
int
nv10_fb_vram_init(struct drm_device *dev)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
u32 fifo_data = nv_rd32(dev, NV04_PFB_FIFO_DATA);
u32 cfg0 = nv_rd32(dev, 0x100200);
dev_priv->vram_size = fifo_data & NV10_PFB_FIFO_DATA_RAM_AMOUNT_MB_MASK;
if (cfg0 & 0x00000001)
dev_priv->vram_type = NV_MEM_TYPE_DDR1;
else
dev_priv->vram_type = NV_MEM_TYPE_SDRAM;
return 0;
}
int
@ -115,14 +84,8 @@ nv10_fb_init(struct drm_device *dev)
struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
int i;
pfb->num_tiles = NV10_PFB_TILE__SIZE;
if (dev_priv->card_type == NV_20)
drm_mm_init(&pfb->tag_heap, 0,
(dev_priv->chipset >= 0x25 ?
64 * 1024 : 32 * 1024));
/* Turn all the tiling regions off. */
pfb->num_tiles = NV10_PFB_TILE__SIZE;
for (i = 0; i < pfb->num_tiles; i++)
pfb->set_tile_region(dev, i);
@ -138,7 +101,4 @@ nv10_fb_takedown(struct drm_device *dev)
for (i = 0; i < pfb->num_tiles; i++)
pfb->free_tile_region(dev, i);
if (dev_priv->card_type == NV_20)
drm_mm_takedown(&pfb->tag_heap);
}

148
drivers/gpu/drm/nouveau/nv20_fb.c Normal file
View File

@ -0,0 +1,148 @@
#include "drmP.h"
#include "drm.h"
#include "nouveau_drv.h"
#include "nouveau_drm.h"
static struct drm_mm_node *
nv20_fb_alloc_tag(struct drm_device *dev, uint32_t size)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
struct drm_mm_node *mem;
int ret;
ret = drm_mm_pre_get(&pfb->tag_heap);
if (ret)
return NULL;
spin_lock(&dev_priv->tile.lock);
mem = drm_mm_search_free(&pfb->tag_heap, size, 0, 0);
if (mem)
mem = drm_mm_get_block_atomic(mem, size, 0);
spin_unlock(&dev_priv->tile.lock);
return mem;
}
static void
nv20_fb_free_tag(struct drm_device *dev, struct drm_mm_node **pmem)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
struct drm_mm_node *mem = *pmem;
if (mem) {
spin_lock(&dev_priv->tile.lock);
drm_mm_put_block(mem);
spin_unlock(&dev_priv->tile.lock);
*pmem = NULL;
}
}
void
nv20_fb_init_tile_region(struct drm_device *dev, int i, uint32_t addr,
uint32_t size, uint32_t pitch, uint32_t flags)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i];
int bpp = (flags & NOUVEAU_GEM_TILE_32BPP ? 32 : 16);
tile->addr = 0x00000001 | addr;
tile->limit = max(1u, addr + size) - 1;
tile->pitch = pitch;
/* Allocate some of the on-die tag memory, used to store Z
* compression meta-data (most likely just a bitmap determining
* if a given tile is compressed or not).
*/
if (flags & NOUVEAU_GEM_TILE_ZETA) {
tile->tag_mem = nv20_fb_alloc_tag(dev, size / 256);
if (tile->tag_mem) {
/* Enable Z compression */
tile->zcomp = tile->tag_mem->start;
if (dev_priv->chipset >= 0x25) {
if (bpp == 16)
tile->zcomp |= NV25_PFB_ZCOMP_MODE_16;
else
tile->zcomp |= NV25_PFB_ZCOMP_MODE_32;
} else {
tile->zcomp |= NV20_PFB_ZCOMP_EN;
if (bpp != 16)
tile->zcomp |= NV20_PFB_ZCOMP_MODE_32;
}
}
tile->addr |= 2;
}
}
void
nv20_fb_free_tile_region(struct drm_device *dev, int i)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i];
tile->addr = tile->limit = tile->pitch = tile->zcomp = 0;
nv20_fb_free_tag(dev, &tile->tag_mem);
}
void
nv20_fb_set_tile_region(struct drm_device *dev, int i)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i];
nv_wr32(dev, NV10_PFB_TLIMIT(i), tile->limit);
nv_wr32(dev, NV10_PFB_TSIZE(i), tile->pitch);
nv_wr32(dev, NV10_PFB_TILE(i), tile->addr);
nv_wr32(dev, NV20_PFB_ZCOMP(i), tile->zcomp);
}
int
nv20_fb_vram_init(struct drm_device *dev)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
u32 mem_size = nv_rd32(dev, 0x10020c);
u32 pbus1218 = nv_rd32(dev, 0x001218);
dev_priv->vram_size = mem_size & 0xff000000;
switch (pbus1218 & 0x00000300) {
case 0x00000000: dev_priv->vram_type = NV_MEM_TYPE_SDRAM; break;
case 0x00000100: dev_priv->vram_type = NV_MEM_TYPE_DDR1; break;
case 0x00000200: dev_priv->vram_type = NV_MEM_TYPE_GDDR3; break;
case 0x00000300: dev_priv->vram_type = NV_MEM_TYPE_GDDR2; break;
}
return 0;
}
int
nv20_fb_init(struct drm_device *dev)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
int i;
if (dev_priv->chipset >= 0x25)
drm_mm_init(&pfb->tag_heap, 0, 64 * 1024);
else
drm_mm_init(&pfb->tag_heap, 0, 32 * 1024);
/* Turn all the tiling regions off. */
pfb->num_tiles = NV10_PFB_TILE__SIZE;
for (i = 0; i < pfb->num_tiles; i++)
pfb->set_tile_region(dev, i);
return 0;
}
void
nv20_fb_takedown(struct drm_device *dev)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
int i;
for (i = 0; i < pfb->num_tiles; i++)
pfb->free_tile_region(dev, i);
drm_mm_takedown(&pfb->tag_heap);
}

45
drivers/gpu/drm/nouveau/nv40_fb.c
View File

@ -71,6 +71,51 @@ nv44_fb_init_gart(struct drm_device *dev)
nv_wr32(dev, 0x100800, vinst | 0x00000010);
}
int
nv40_fb_vram_init(struct drm_device *dev)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
/* 0x001218 is actually present on a few other NV4X I looked at,
* and even contains sane values matching 0x100474. From looking
* at various vbios images however, this isn't the case everywhere.
* So, I chose to use the same regs I've seen NVIDIA reading around
* the memory detection, hopefully that'll get us the right numbers
*/
if (dev_priv->chipset == 0x40) {
u32 pbus1218 = nv_rd32(dev, 0x001218);
switch (pbus1218 & 0x00000300) {
case 0x00000000: dev_priv->vram_type = NV_MEM_TYPE_SDRAM; break;
case 0x00000100: dev_priv->vram_type = NV_MEM_TYPE_DDR1; break;
case 0x00000200: dev_priv->vram_type = NV_MEM_TYPE_GDDR3; break;
case 0x00000300: dev_priv->vram_type = NV_MEM_TYPE_DDR2; break;
}
} else
if (dev_priv->chipset == 0x49 || dev_priv->chipset == 0x4b) {
u32 pfb914 = nv_rd32(dev, 0x100914);
switch (pfb914 & 0x00000003) {
case 0x00000000: dev_priv->vram_type = NV_MEM_TYPE_DDR1; break;
case 0x00000001: dev_priv->vram_type = NV_MEM_TYPE_DDR2; break;
case 0x00000002: dev_priv->vram_type = NV_MEM_TYPE_GDDR3; break;
case 0x00000003: break;
}
} else
if (dev_priv->chipset != 0x4e) {
u32 pfb474 = nv_rd32(dev, 0x100474);
if (pfb474 & 0x00000004)
dev_priv->vram_type = NV_MEM_TYPE_GDDR3;
if (pfb474 & 0x00000002)
dev_priv->vram_type = NV_MEM_TYPE_DDR2;
if (pfb474 & 0x00000001)
dev_priv->vram_type = NV_MEM_TYPE_DDR1;
} else {
dev_priv->vram_type = NV_MEM_TYPE_STOLEN;
}
dev_priv->vram_size = nv_rd32(dev, 0x10020c) & 0xff000000;
return 0;
}
int
nv40_fb_init(struct drm_device *dev)
{

42
drivers/gpu/drm/nouveau/nv50_crtc.c
View File

@ -170,6 +170,41 @@ nv50_crtc_set_dither(struct nouveau_crtc *nv_crtc, bool update)
return ret;
}
static int
nv50_crtc_set_color_vibrance(struct nouveau_crtc *nv_crtc, bool update)
{
struct drm_device *dev = nv_crtc->base.dev;
struct nouveau_channel *evo = nv50_display(dev)->master;
int ret;
int adj;
u32 hue, vib;
NV_DEBUG_KMS(dev, "vibrance = %i, hue = %i\n",
nv_crtc->color_vibrance, nv_crtc->vibrant_hue);
ret = RING_SPACE(evo, 2 + (update ? 2 : 0));
if (ret) {
NV_ERROR(dev, "no space while setting color vibrance\n");
return ret;
}
adj = (nv_crtc->color_vibrance > 0) ? 50 : 0;
vib = ((nv_crtc->color_vibrance * 2047 + adj) / 100) & 0xfff;
hue = ((nv_crtc->vibrant_hue * 2047) / 100) & 0xfff;
BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, COLOR_CTRL), 1);
OUT_RING (evo, (hue << 20) | (vib << 8));
if (update) {
BEGIN_RING(evo, 0, NV50_EVO_UPDATE, 1);
OUT_RING (evo, 0);
FIRE_RING (evo);
}
return 0;
}
struct nouveau_connector *
nouveau_crtc_connector_get(struct nouveau_crtc *nv_crtc)
{
@ -577,8 +612,6 @@ nv50_crtc_do_mode_set_base(struct drm_crtc *crtc,
OUT_RING (evo, fb->base.depth == 8 ?
NV50_EVO_CRTC_CLUT_MODE_OFF : NV50_EVO_CRTC_CLUT_MODE_ON);
BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, COLOR_CTRL), 1);
OUT_RING (evo, NV50_EVO_CRTC_COLOR_CTRL_COLOR);
BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, FB_POS), 1);
OUT_RING (evo, (y << 16) | x);
@ -661,6 +694,7 @@ nv50_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *umode,
nv_crtc->set_dither(nv_crtc, false);
nv_crtc->set_scale(nv_crtc, false);
nv_crtc->set_color_vibrance(nv_crtc, false);
return nv50_crtc_do_mode_set_base(crtc, old_fb, x, y, false);
}
@ -721,6 +755,9 @@ nv50_crtc_create(struct drm_device *dev, int index)
if (!nv_crtc)
return -ENOMEM;
nv_crtc->color_vibrance = 50;
nv_crtc->vibrant_hue = 0;
/* Default CLUT parameters, will be activated on the hw upon
* first mode set.
*/
@ -751,6 +788,7 @@ nv50_crtc_create(struct drm_device *dev, int index)
/* set function pointers */
nv_crtc->set_dither = nv50_crtc_set_dither;
nv_crtc->set_scale = nv50_crtc_set_scale;
nv_crtc->set_color_vibrance = nv50_crtc_set_color_vibrance;
drm_crtc_init(dev, &nv_crtc->base, &nv50_crtc_funcs);
drm_crtc_helper_add(&nv_crtc->base, &nv50_crtc_helper_funcs);

27
drivers/gpu/drm/nouveau/nv50_display.c
View File

@ -50,6 +50,29 @@ nv50_sor_nr(struct drm_device *dev)
return 4;
}
u32
nv50_display_active_crtcs(struct drm_device *dev)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
u32 mask = 0;
int i;
if (dev_priv->chipset < 0x90 ||
dev_priv->chipset == 0x92 ||
dev_priv->chipset == 0xa0) {
for (i = 0; i < 2; i++)
mask |= nv_rd32(dev, NV50_PDISPLAY_SOR_MODE_CTRL_C(i));
} else {
for (i = 0; i < 4; i++)
mask |= nv_rd32(dev, NV90_PDISPLAY_SOR_MODE_CTRL_C(i));
}
for (i = 0; i < 3; i++)
mask |= nv_rd32(dev, NV50_PDISPLAY_DAC_MODE_CTRL_C(i));
return mask & 3;
}
static int
evo_icmd(struct drm_device *dev, int ch, u32 mthd, u32 data)
{
@ -840,9 +863,9 @@ nv50_display_unk20_handler(struct drm_device *dev)
if (type == OUTPUT_DP) {
int link = !(dcb->dpconf.sor.link & 1);
if ((mc & 0x000f0000) == 0x00020000)
nouveau_dp_tu_update(dev, or, link, pclk, 18);
nv50_sor_dp_calc_tu(dev, or, link, pclk, 18);
else
nouveau_dp_tu_update(dev, or, link, pclk, 24);
nv50_sor_dp_calc_tu(dev, or, link, pclk, 24);
}
if (dcb->type != OUTPUT_ANALOG) {

2
drivers/gpu/drm/nouveau/nv50_display.h
View File

@ -74,6 +74,8 @@ void nv50_display_destroy(struct drm_device *dev);
int nv50_crtc_blank(struct nouveau_crtc *, bool blank);
int nv50_crtc_set_clock(struct drm_device *, int head, int pclk);
u32 nv50_display_active_crtcs(struct drm_device *);
int nv50_display_sync(struct drm_device *);
int nv50_display_flip_next(struct drm_crtc *, struct drm_framebuffer *,
struct nouveau_channel *chan);

3
drivers/gpu/drm/nouveau/nv50_evo.h
View File

@ -104,7 +104,8 @@
#define NV50_EVO_CRTC_SCALE_CTRL_INACTIVE 0x00000000
#define NV50_EVO_CRTC_SCALE_CTRL_ACTIVE 0x00000009
#define NV50_EVO_CRTC_COLOR_CTRL 0x000008a8
#define NV50_EVO_CRTC_COLOR_CTRL_COLOR 0x00040000
#define NV50_EVO_CRTC_COLOR_CTRL_VIBRANCE 0x000fff00
#define NV50_EVO_CRTC_COLOR_CTRL_HUE 0xfff00000
#define NV50_EVO_CRTC_FB_POS 0x000008c0
#define NV50_EVO_CRTC_REAL_RES 0x000008c8
#define NV50_EVO_CRTC_SCALE_CENTER_OFFSET 0x000008d4

397
drivers/gpu/drm/nouveau/nv50_pm.c
View File

@ -28,6 +28,7 @@
#include "nouveau_hw.h"
#include "nouveau_pm.h"
#include "nouveau_hwsq.h"
#include "nv50_display.h"
enum clk_src {
clk_src_crystal,
@ -352,17 +353,13 @@ nv50_pm_clocks_get(struct drm_device *dev, struct nouveau_pm_level *perflvl)
}
struct nv50_pm_state {
struct nouveau_pm_level *perflvl;
struct hwsq_ucode eclk_hwsq;
struct hwsq_ucode mclk_hwsq;
u32 mscript;
u32 emast;
u32 nctrl;
u32 ncoef;
u32 sctrl;
u32 scoef;
u32 amast;
u32 pdivs;
u32 mmast;
u32 mctrl;
u32 mcoef;
};
static u32
@ -415,40 +412,153 @@ clk_same(u32 a, u32 b)
return ((a / 1000) == (b / 1000));
}
static void
mclk_precharge(struct nouveau_mem_exec_func *exec)
{
struct nv50_pm_state *info = exec->priv;
struct hwsq_ucode *hwsq = &info->mclk_hwsq;
hwsq_wr32(hwsq, 0x1002d4, 0x00000001);
}
static void
mclk_refresh(struct nouveau_mem_exec_func *exec)
{
struct nv50_pm_state *info = exec->priv;
struct hwsq_ucode *hwsq = &info->mclk_hwsq;
hwsq_wr32(hwsq, 0x1002d0, 0x00000001);
}
static void
mclk_refresh_auto(struct nouveau_mem_exec_func *exec, bool enable)
{
struct nv50_pm_state *info = exec->priv;
struct hwsq_ucode *hwsq = &info->mclk_hwsq;
hwsq_wr32(hwsq, 0x100210, enable ? 0x80000000 : 0x00000000);
}
static void
mclk_refresh_self(struct nouveau_mem_exec_func *exec, bool enable)
{
struct nv50_pm_state *info = exec->priv;
struct hwsq_ucode *hwsq = &info->mclk_hwsq;
hwsq_wr32(hwsq, 0x1002dc, enable ? 0x00000001 : 0x00000000);
}
static void
mclk_wait(struct nouveau_mem_exec_func *exec, u32 nsec)
{
struct nv50_pm_state *info = exec->priv;
struct hwsq_ucode *hwsq = &info->mclk_hwsq;
if (nsec > 1000)
hwsq_usec(hwsq, (nsec + 500) / 1000);
}
static u32
mclk_mrg(struct nouveau_mem_exec_func *exec, int mr)
{
if (mr <= 1)
return nv_rd32(exec->dev, 0x1002c0 + ((mr - 0) * 4));
if (mr <= 3)
return nv_rd32(exec->dev, 0x1002e0 + ((mr - 2) * 4));
return 0;
}
static void
mclk_mrs(struct nouveau_mem_exec_func *exec, int mr, u32 data)
{
struct drm_nouveau_private *dev_priv = exec->dev->dev_private;
struct nv50_pm_state *info = exec->priv;
struct hwsq_ucode *hwsq = &info->mclk_hwsq;
if (mr <= 1) {
if (dev_priv->vram_rank_B)
hwsq_wr32(hwsq, 0x1002c8 + ((mr - 0) * 4), data);
hwsq_wr32(hwsq, 0x1002c0 + ((mr - 0) * 4), data);
} else
if (mr <= 3) {
if (dev_priv->vram_rank_B)
hwsq_wr32(hwsq, 0x1002e8 + ((mr - 2) * 4), data);
hwsq_wr32(hwsq, 0x1002e0 + ((mr - 2) * 4), data);
}
}
static void
mclk_clock_set(struct nouveau_mem_exec_func *exec)
{
struct nv50_pm_state *info = exec->priv;
struct hwsq_ucode *hwsq = &info->mclk_hwsq;
u32 ctrl = nv_rd32(exec->dev, 0x004008);
info->mmast = nv_rd32(exec->dev, 0x00c040);
info->mmast &= ~0xc0000000; /* get MCLK_2 from HREF */
info->mmast |= 0x0000c000; /* use MCLK_2 as MPLL_BYPASS clock */
hwsq_wr32(hwsq, 0xc040, info->mmast);
hwsq_wr32(hwsq, 0x4008, ctrl | 0x00000200); /* bypass MPLL */
if (info->mctrl & 0x80000000)
hwsq_wr32(hwsq, 0x400c, info->mcoef);
hwsq_wr32(hwsq, 0x4008, info->mctrl);
}
static void
mclk_timing_set(struct nouveau_mem_exec_func *exec)
{
struct drm_device *dev = exec->dev;
struct nv50_pm_state *info = exec->priv;
struct nouveau_pm_level *perflvl = info->perflvl;
struct hwsq_ucode *hwsq = &info->mclk_hwsq;
int i;
for (i = 0; i < 9; i++) {
u32 reg = 0x100220 + (i * 4);
u32 val = nv_rd32(dev, reg);
if (val != perflvl->timing.reg[i])
hwsq_wr32(hwsq, reg, perflvl->timing.reg[i]);
}
}
static int
calc_mclk(struct drm_device *dev, u32 freq, struct hwsq_ucode *hwsq)
calc_mclk(struct drm_device *dev, struct nouveau_pm_level *perflvl,
struct nv50_pm_state *info)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
u32 crtc_mask = nv50_display_active_crtcs(dev);
struct nouveau_mem_exec_func exec = {
.dev = dev,
.precharge = mclk_precharge,
.refresh = mclk_refresh,
.refresh_auto = mclk_refresh_auto,
.refresh_self = mclk_refresh_self,
.wait = mclk_wait,
.mrg = mclk_mrg,
.mrs = mclk_mrs,
.clock_set = mclk_clock_set,
.timing_set = mclk_timing_set,
.priv = info
};
struct hwsq_ucode *hwsq = &info->mclk_hwsq;
struct pll_lims pll;
u32 mast = nv_rd32(dev, 0x00c040);
u32 ctrl = nv_rd32(dev, 0x004008);
u32 coef = nv_rd32(dev, 0x00400c);
u32 orig = ctrl;
u32 crtc_mask = 0;
int N, M, P;
int ret, i;
int ret;
/* use pcie refclock if possible, otherwise use mpll */
ctrl &= ~0x81ff0200;
if (clk_same(freq, read_clk(dev, clk_src_href))) {
ctrl |= 0x00000200 | (pll.log2p_bias << 19);
info->mctrl = nv_rd32(dev, 0x004008);
info->mctrl &= ~0x81ff0200;
if (clk_same(perflvl->memory, read_clk(dev, clk_src_href))) {
info->mctrl |= 0x00000200 | (pll.log2p_bias << 19);
} else {
ret = calc_pll(dev, 0x4008, &pll, freq, &N, &M, &P);
ret = calc_pll(dev, 0x4008, &pll, perflvl->memory, &N, &M, &P);
if (ret == 0)
return -EINVAL;
ctrl |= 0x80000000 | (P << 22) | (P << 16);
ctrl |= pll.log2p_bias << 19;
coef = (N << 8) | M;
}
mast &= ~0xc0000000; /* get MCLK_2 from HREF */
mast |= 0x0000c000; /* use MCLK_2 as MPLL_BYPASS clock */
/* determine active crtcs */
for (i = 0; i < 2; i++) {
if (nv_rd32(dev, NV50_PDISPLAY_CRTC_C(i, CLOCK)))
crtc_mask |= (1 << i);
info->mctrl |= 0x80000000 | (P << 22) | (P << 16);
info->mctrl |= pll.log2p_bias << 19;
info->mcoef = (N << 8) | M;
}
/* build the ucode which will reclock the memory for us */
@ -462,25 +572,10 @@ calc_mclk(struct drm_device *dev, u32 freq, struct hwsq_ucode *hwsq)
hwsq_setf(hwsq, 0x10, 0); /* disable bus access */
hwsq_op5f(hwsq, 0x00, 0x01); /* no idea :s */
/* prepare memory controller */
hwsq_wr32(hwsq, 0x1002d4, 0x00000001); /* precharge banks and idle */
hwsq_wr32(hwsq, 0x1002d0, 0x00000001); /* force refresh */
hwsq_wr32(hwsq, 0x100210, 0x00000000); /* stop the automatic refresh */
hwsq_wr32(hwsq, 0x1002dc, 0x00000001); /* start self refresh mode */
ret = nouveau_mem_exec(&exec, perflvl);
if (ret)
return ret;
/* reclock memory */
hwsq_wr32(hwsq, 0xc040, mast);
hwsq_wr32(hwsq, 0x4008, orig | 0x00000200); /* bypass MPLL */
hwsq_wr32(hwsq, 0x400c, coef);
hwsq_wr32(hwsq, 0x4008, ctrl);
/* restart memory controller */
hwsq_wr32(hwsq, 0x1002d4, 0x00000001); /* precharge banks and idle */
hwsq_wr32(hwsq, 0x1002dc, 0x00000000); /* stop self refresh mode */
hwsq_wr32(hwsq, 0x100210, 0x80000000); /* restart automatic refresh */
hwsq_usec(hwsq, 12); /* wait for the PLL to stabilize */
hwsq_usec(hwsq, 48); /* may be unnecessary: causes flickering */
hwsq_setf(hwsq, 0x10, 1); /* enable bus access */
hwsq_op5f(hwsq, 0x00, 0x00); /* no idea, reverse of 0x00, 0x01? */
if (dev_priv->chipset >= 0x92)
@ -494,10 +589,11 @@ nv50_pm_clocks_pre(struct drm_device *dev, struct nouveau_pm_level *perflvl)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
struct nv50_pm_state *info;
struct hwsq_ucode *hwsq;
struct pll_lims pll;
u32 out, mast, divs, ctrl;
int clk, ret = -EINVAL;
int N, M, P1, P2;
u32 out;
if (dev_priv->chipset == 0xaa ||
dev_priv->chipset == 0xac)
@ -506,54 +602,44 @@ nv50_pm_clocks_pre(struct drm_device *dev, struct nouveau_pm_level *perflvl)
info = kmalloc(sizeof(*info), GFP_KERNEL);
if (!info)
return ERR_PTR(-ENOMEM);
info->perflvl = perflvl;
/* core: for the moment at least, always use nvpll */
clk = calc_pll(dev, 0x4028, &pll, perflvl->core, &N, &M, &P1);
if (clk == 0)
goto error;
info->emast = 0x00000003;
info->nctrl = 0x80000000 | (P1 << 19) | (P1 << 16);
info->ncoef = (N << 8) | M;
/* shader: tie to nvclk if possible, otherwise use spll. have to be
* very careful that the shader clock is at least twice the core, or
* some chipsets will be very unhappy. i expect most or all of these
* cases will be handled by tying to nvclk, but it's possible there's
* corners
*/
if (P1-- && perflvl->shader == (perflvl->core << 1)) {
info->emast |= 0x00000020;
info->sctrl = 0x00000000 | (P1 << 19) | (P1 << 16);
info->scoef = nv_rd32(dev, 0x004024);
} else {
clk = calc_pll(dev, 0x4020, &pll, perflvl->shader, &N, &M, &P1);
if (clk == 0)
goto error;
info->emast |= 0x00000030;
info->sctrl = 0x80000000 | (P1 << 19) | (P1 << 16);
info->scoef = (N << 8) | M;
}
/* memory: build hwsq ucode which we'll use to reclock memory */
/* memory: build hwsq ucode which we'll use to reclock memory.
* use pcie refclock if possible, otherwise use mpll */
info->mclk_hwsq.len = 0;
if (perflvl->memory) {
clk = calc_mclk(dev, perflvl->memory, &info->mclk_hwsq);
if (clk < 0) {
ret = clk;
ret = calc_mclk(dev, perflvl, info);
if (ret)
goto error;
}
info->mscript = perflvl->memscript;
}
divs = read_div(dev);
mast = info->mmast;
/* start building HWSQ script for engine reclocking */
hwsq = &info->eclk_hwsq;
hwsq_init(hwsq);
hwsq_setf(hwsq, 0x10, 0); /* disable bus access */
hwsq_op5f(hwsq, 0x00, 0x01); /* wait for access disabled? */
/* vdec/dom6: switch to "safe" clocks temporarily */
if (perflvl->vdec) {
mast &= ~0x00000c00;
divs &= ~0x00000700;
}
if (perflvl->dom6) {
mast &= ~0x0c000000;
divs &= ~0x00000007;
}
hwsq_wr32(hwsq, 0x00c040, mast);
/* vdec: avoid modifying xpll until we know exactly how the other
* clock domains work, i suspect at least some of them can also be
* tied to xpll...
*/
info->amast = nv_rd32(dev, 0x00c040);
info->pdivs = read_div(dev);
if (perflvl->vdec) {
/* see how close we can get using nvclk as a source */
clk = calc_div(perflvl->core, perflvl->vdec, &P1);
@ -566,16 +652,14 @@ nv50_pm_clocks_pre(struct drm_device *dev, struct nouveau_pm_level *perflvl)
out = calc_div(out, perflvl->vdec, &P2);
/* select whichever gets us closest */
info->amast &= ~0x00000c00;
info->pdivs &= ~0x00000700;
if (abs((int)perflvl->vdec - clk) <=
abs((int)perflvl->vdec - out)) {
if (dev_priv->chipset != 0x98)
info->amast |= 0x00000c00;
info->pdivs |= P1 << 8;
mast |= 0x00000c00;
divs |= P1 << 8;
} else {
info->amast |= 0x00000800;
info->pdivs |= P2 << 8;
mast |= 0x00000800;
divs |= P2 << 8;
}
}
@ -583,21 +667,82 @@ nv50_pm_clocks_pre(struct drm_device *dev, struct nouveau_pm_level *perflvl)
* of the host clock frequency
*/
if (perflvl->dom6) {
info->amast &= ~0x0c000000;
if (clk_same(perflvl->dom6, read_clk(dev, clk_src_href))) {
info->amast |= 0x00000000;
mast |= 0x00000000;
} else
if (clk_same(perflvl->dom6, read_clk(dev, clk_src_hclk))) {
info->amast |= 0x08000000;
mast |= 0x08000000;
} else {
clk = read_clk(dev, clk_src_hclk) * 3;
clk = calc_div(clk, perflvl->dom6, &P1);
info->amast |= 0x0c000000;
info->pdivs = (info->pdivs & ~0x00000007) | P1;
mast |= 0x0c000000;
divs |= P1;
}
}
/* vdec/dom6: complete switch to new clocks */
switch (dev_priv->chipset) {
case 0x92:
case 0x94:
case 0x96:
hwsq_wr32(hwsq, 0x004800, divs);
break;
default:
hwsq_wr32(hwsq, 0x004700, divs);
break;
}
hwsq_wr32(hwsq, 0x00c040, mast);
/* core/shader: make sure sclk/nvclk are disconnected from their
* PLLs (nvclk to dom6, sclk to hclk)
*/
if (dev_priv->chipset < 0x92)
mast = (mast & ~0x001000b0) | 0x00100080;
else
mast = (mast & ~0x000000b3) | 0x00000081;
hwsq_wr32(hwsq, 0x00c040, mast);
/* core: for the moment at least, always use nvpll */
clk = calc_pll(dev, 0x4028, &pll, perflvl->core, &N, &M, &P1);
if (clk == 0)
goto error;
ctrl = nv_rd32(dev, 0x004028) & ~0xc03f0100;
mast &= ~0x00100000;
mast |= 3;
hwsq_wr32(hwsq, 0x004028, 0x80000000 | (P1 << 19) | (P1 << 16) | ctrl);
hwsq_wr32(hwsq, 0x00402c, (N << 8) | M);
/* shader: tie to nvclk if possible, otherwise use spll. have to be
* very careful that the shader clock is at least twice the core, or
* some chipsets will be very unhappy. i expect most or all of these
* cases will be handled by tying to nvclk, but it's possible there's
* corners
*/
ctrl = nv_rd32(dev, 0x004020) & ~0xc03f0100;
if (P1-- && perflvl->shader == (perflvl->core << 1)) {
hwsq_wr32(hwsq, 0x004020, (P1 << 19) | (P1 << 16) | ctrl);
hwsq_wr32(hwsq, 0x00c040, 0x00000020 | mast);
} else {
clk = calc_pll(dev, 0x4020, &pll, perflvl->shader, &N, &M, &P1);
if (clk == 0)
goto error;
ctrl |= 0x80000000;
hwsq_wr32(hwsq, 0x004020, (P1 << 19) | (P1 << 16) | ctrl);
hwsq_wr32(hwsq, 0x004024, (N << 8) | M);
hwsq_wr32(hwsq, 0x00c040, 0x00000030 | mast);
}
hwsq_setf(hwsq, 0x10, 1); /* enable bus access */
hwsq_op5f(hwsq, 0x00, 0x00); /* wait for access enabled? */
hwsq_fini(hwsq);
return info;
error:
kfree(info);
@ -605,23 +750,24 @@ error:
}
static int
prog_mclk(struct drm_device *dev, struct hwsq_ucode *hwsq)
prog_hwsq(struct drm_device *dev, struct hwsq_ucode *hwsq)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
u32 hwsq_data, hwsq_kick;
int i;
if (dev_priv->chipset < 0x90) {
if (dev_priv->chipset < 0x94) {
hwsq_data = 0x001400;
hwsq_kick = 0x00000003;
} else {
hwsq_data = 0x080000;
hwsq_kick = 0x00000001;
}
/* upload hwsq ucode */
nv_mask(dev, 0x001098, 0x00000008, 0x00000000);
nv_wr32(dev, 0x001304, 0x00000000);
if (dev_priv->chipset >= 0x92)
nv_wr32(dev, 0x001318, 0x00000000);
for (i = 0; i < hwsq->len / 4; i++)
nv_wr32(dev, hwsq_data + (i * 4), hwsq->ptr.u32[i]);
nv_mask(dev, 0x001098, 0x00000018, 0x00000018);
@ -645,20 +791,19 @@ prog_mclk(struct drm_device *dev, struct hwsq_ucode *hwsq)
int
nv50_pm_clocks_set(struct drm_device *dev, void *data)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
struct nv50_pm_state *info = data;
struct bit_entry M;
int ret = 0;
int ret = -EBUSY;
/* halt and idle execution engines */
nv_mask(dev, 0x002504, 0x00000001, 0x00000001);
if (!nv_wait(dev, 0x002504, 0x00000010, 0x00000010))
goto error;
goto resume;
if (!nv_wait(dev, 0x00251c, 0x0000003f, 0x0000003f))
goto resume;
/* memory: it is *very* important we change this first, the ucode
* we build in pre() now has hardcoded 0xc040 values, which can't
* change before we execute it or the engine clocks may end up
* messed up.
/* program memory clock, if necessary - must come before engine clock
* reprogramming due to how we construct the hwsq scripts in pre()
*/
if (info->mclk_hwsq.len) {
/* execute some scripts that do ??? from the vbios.. */
@ -672,42 +817,14 @@ nv50_pm_clocks_set(struct drm_device *dev, void *data)
nouveau_bios_init_exec(dev, info->mscript);
}
ret = prog_mclk(dev, &info->mclk_hwsq);
ret = prog_hwsq(dev, &info->mclk_hwsq);
if (ret)
goto resume;
}
/* reclock vdec/dom6 */
nv_mask(dev, 0x00c040, 0x00000c00, 0x00000000);
switch (dev_priv->chipset) {
case 0x92:
case 0x94:
case 0x96:
nv_mask(dev, 0x004800, 0x00000707, info->pdivs);
break;
default:
nv_mask(dev, 0x004700, 0x00000707, info->pdivs);
break;
}
nv_mask(dev, 0x00c040, 0x0c000c00, info->amast);
/* program engine clocks */
ret = prog_hwsq(dev, &info->eclk_hwsq);
/* core/shader: make sure sclk/nvclk are disconnected from their
* plls (nvclk to dom6, sclk to hclk), modify the plls, and
* reconnect sclk/nvclk to their new clock source
*/
if (dev_priv->chipset < 0x92)
nv_mask(dev, 0x00c040, 0x001000b0, 0x00100080); /* grrr! */
else
nv_mask(dev, 0x00c040, 0x000000b3, 0x00000081);
nv_mask(dev, 0x004020, 0xc03f0100, info->sctrl);
nv_wr32(dev, 0x004024, info->scoef);
nv_mask(dev, 0x004028, 0xc03f0100, info->nctrl);
nv_wr32(dev, 0x00402c, info->ncoef);
nv_mask(dev, 0x00c040, 0x00100033, info->emast);
goto resume;
error:
ret = -EBUSY;
resume:
nv_mask(dev, 0x002504, 0x00000001, 0x00000000);
kfree(info);

206
drivers/gpu/drm/nouveau/nv50_sor.c
View File

@ -36,6 +36,193 @@
#include "nouveau_crtc.h"
#include "nv50_display.h"
static u32
nv50_sor_dp_lane_map(struct drm_device *dev, struct dcb_entry *dcb, u8 lane)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
static const u8 nvaf[] = { 24, 16, 8, 0 }; /* thanks, apple.. */
static const u8 nv50[] = { 16, 8, 0, 24 };
if (dev_priv->card_type == 0xaf)
return nvaf[lane];
return nv50[lane];
}
static void
nv50_sor_dp_train_set(struct drm_device *dev, struct dcb_entry *dcb, u8 pattern)
{
u32 or = ffs(dcb->or) - 1, link = !(dcb->sorconf.link & 1);
nv_mask(dev, NV50_SOR_DP_CTRL(or, link), 0x0f000000, pattern << 24);
}
static void
nv50_sor_dp_train_adj(struct drm_device *dev, struct dcb_entry *dcb,
u8 lane, u8 swing, u8 preem)
{
u32 or = ffs(dcb->or) - 1, link = !(dcb->sorconf.link & 1);
u32 shift = nv50_sor_dp_lane_map(dev, dcb, lane);
u32 mask = 0x000000ff << shift;
u8 *table, *entry, *config;
table = nouveau_dp_bios_data(dev, dcb, &entry);
if (!table || (table[0] != 0x20 && table[0] != 0x21)) {
NV_ERROR(dev, "PDISP: unsupported DP table for chipset\n");
return;
}
config = entry + table[4];
while (config[0] != swing || config[1] != preem) {
config += table[5];
if (config >= entry + table[4] + entry[4] * table[5])
return;
}
nv_mask(dev, NV50_SOR_DP_UNK118(or, link), mask, config[2] << shift);
nv_mask(dev, NV50_SOR_DP_UNK120(or, link), mask, config[3] << shift);
nv_mask(dev, NV50_SOR_DP_UNK130(or, link), 0x0000ff00, config[4] << 8);
}
static void
nv50_sor_dp_link_set(struct drm_device *dev, struct dcb_entry *dcb, int crtc,
int link_nr, u32 link_bw, bool enhframe)
{
u32 or = ffs(dcb->or) - 1, link = !(dcb->sorconf.link & 1);
u32 dpctrl = nv_rd32(dev, NV50_SOR_DP_CTRL(or, link)) & ~0x001f4000;
u32 clksor = nv_rd32(dev, 0x614300 + (or * 0x800)) & ~0x000c0000;
u8 *table, *entry, mask;
int i;
table = nouveau_dp_bios_data(dev, dcb, &entry);
if (!table || (table[0] != 0x20 && table[0] != 0x21)) {
NV_ERROR(dev, "PDISP: unsupported DP table for chipset\n");
return;
}
entry = ROMPTR(dev, entry[10]);
if (entry) {
while (link_bw < ROM16(entry[0]) * 10)
entry += 4;
nouveau_bios_run_init_table(dev, ROM16(entry[2]), dcb, crtc);
}
dpctrl |= ((1 << link_nr) - 1) << 16;
if (enhframe)
dpctrl |= 0x00004000;
if (link_bw > 162000)
clksor |= 0x00040000;
nv_wr32(dev, 0x614300 + (or * 0x800), clksor);
nv_wr32(dev, NV50_SOR_DP_CTRL(or, link), dpctrl);
mask = 0;
for (i = 0; i < link_nr; i++)
mask |= 1 << (nv50_sor_dp_lane_map(dev, dcb, i) >> 3);
nv_mask(dev, NV50_SOR_DP_UNK130(or, link), 0x0000000f, mask);
}
static void
nv50_sor_dp_link_get(struct drm_device *dev, u32 or, u32 link, u32 *nr, u32 *bw)
{
u32 dpctrl = nv_rd32(dev, NV50_SOR_DP_CTRL(or, link)) & 0x000f0000;
u32 clksor = nv_rd32(dev, 0x614300 + (or * 0x800));
if (clksor & 0x000c0000)
*bw = 270000;
else
*bw = 162000;
if (dpctrl > 0x00030000) *nr = 4;
else if (dpctrl > 0x00010000) *nr = 2;
else *nr = 1;
}
void
nv50_sor_dp_calc_tu(struct drm_device *dev, int or, int link, u32 clk, u32 bpp)
{
const u32 symbol = 100000;
int bestTU = 0, bestVTUi = 0, bestVTUf = 0, bestVTUa = 0;
int TU, VTUi, VTUf, VTUa;
u64 link_data_rate, link_ratio, unk;
u32 best_diff = 64 * symbol;
u32 link_nr, link_bw, r;
/* calculate packed data rate for each lane */
nv50_sor_dp_link_get(dev, or, link, &link_nr, &link_bw);
link_data_rate = (clk * bpp / 8) / link_nr;
/* calculate ratio of packed data rate to link symbol rate */
link_ratio = link_data_rate * symbol;
r = do_div(link_ratio, link_bw);
for (TU = 64; TU >= 32; TU--) {
/* calculate average number of valid symbols in each TU */
u32 tu_valid = link_ratio * TU;
u32 calc, diff;
/* find a hw representation for the fraction.. */
VTUi = tu_valid / symbol;
calc = VTUi * symbol;
diff = tu_valid - calc;
if (diff) {
if (diff >= (symbol / 2)) {
VTUf = symbol / (symbol - diff);
if (symbol - (VTUf * diff))
VTUf++;
if (VTUf <= 15) {
VTUa = 1;
calc += symbol - (symbol / VTUf);
} else {
VTUa = 0;
VTUf = 1;
calc += symbol;
}
} else {
VTUa = 0;
VTUf = min((int)(symbol / diff), 15);
calc += symbol / VTUf;
}
diff = calc - tu_valid;
} else {
/* no remainder, but the hw doesn't like the fractional
* part to be zero. decrement the integer part and
* have the fraction add a whole symbol back
*/
VTUa = 0;
VTUf = 1;
VTUi--;
}
if (diff < best_diff) {
best_diff = diff;
bestTU = TU;
bestVTUa = VTUa;
bestVTUf = VTUf;
bestVTUi = VTUi;
if (diff == 0)
break;
}
}
if (!bestTU) {
NV_ERROR(dev, "DP: unable to find suitable config\n");
return;
}
/* XXX close to vbios numbers, but not right */
unk = (symbol - link_ratio) * bestTU;
unk *= link_ratio;
r = do_div(unk, symbol);
r = do_div(unk, symbol);
unk += 6;
nv_mask(dev, NV50_SOR_DP_CTRL(or, link), 0x000001fc, bestTU << 2);
nv_mask(dev, NV50_SOR_DP_SCFG(or, link), 0x010f7f3f, bestVTUa << 24 |
bestVTUf << 16 |
bestVTUi << 8 |
unk);
}
static void
nv50_sor_disconnect(struct drm_encoder *encoder)
{
@ -117,20 +304,13 @@ nv50_sor_dpms(struct drm_encoder *encoder, int mode)
}
if (nv_encoder->dcb->type == OUTPUT_DP) {
struct nouveau_i2c_chan *auxch;
struct dp_train_func func = {
.link_set = nv50_sor_dp_link_set,
.train_set = nv50_sor_dp_train_set,
.train_adj = nv50_sor_dp_train_adj
};
auxch = nouveau_i2c_find(dev, nv_encoder->dcb->i2c_index);
if (!auxch)
return;
if (mode == DRM_MODE_DPMS_ON) {
u8 status = DP_SET_POWER_D0;
nouveau_dp_auxch(auxch, 8, DP_SET_POWER, &status, 1);
nouveau_dp_link_train(encoder, nv_encoder->dp.datarate);
} else {
u8 status = DP_SET_POWER_D3;
nouveau_dp_auxch(auxch, 8, DP_SET_POWER, &status, 1);
}
nouveau_dp_dpms(encoder, mode, nv_encoder->dp.datarate, &func);
}
}

29
drivers/gpu/drm/nouveau/nv50_vm.c
View File

@ -57,27 +57,15 @@ nv50_vm_map_pgt(struct nouveau_gpuobj *pgd, u32 pde,
}
static inline u64
nv50_vm_addr(struct nouveau_vma *vma, u64 phys, u32 memtype, u32 target)
vm_addr(struct nouveau_vma *vma, u64 phys, u32 memtype, u32 target)
{
struct drm_nouveau_private *dev_priv = vma->vm->dev->dev_private;
phys |= 1; /* present */
phys |= (u64)memtype << 40;
/* IGPs don't have real VRAM, re-target to stolen system memory */
if (target == 0 && dev_priv->vram_sys_base) {
phys += dev_priv->vram_sys_base;
target = 3;
}
phys |= target << 4;
if (vma->access & NV_MEM_ACCESS_SYS)
phys |= (1 << 6);
if (!(vma->access & NV_MEM_ACCESS_WO))
phys |= (1 << 3);
return phys;
}
@ -85,11 +73,19 @@ void
nv50_vm_map(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt,
struct nouveau_mem *mem, u32 pte, u32 cnt, u64 phys, u64 delta)
{
struct drm_nouveau_private *dev_priv = vma->vm->dev->dev_private;
u32 comp = (mem->memtype & 0x180) >> 7;
u32 block;
u32 block, target;
int i;
phys = nv50_vm_addr(vma, phys, mem->memtype, 0);
/* IGPs don't have real VRAM, re-target to stolen system memory */
target = 0;
if (dev_priv->vram_sys_base) {
phys += dev_priv->vram_sys_base;
target = 3;
}
phys = vm_addr(vma, phys, mem->memtype, target);
pte <<= 3;
cnt <<= 3;
@ -125,9 +121,10 @@ void
nv50_vm_map_sg(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt,
struct nouveau_mem *mem, u32 pte, u32 cnt, dma_addr_t *list)
{
u32 target = (vma->access & NV_MEM_ACCESS_NOSNOOP) ? 3 : 2;
pte <<= 3;
while (cnt--) {
u64 phys = nv50_vm_addr(vma, (u64)*list++, mem->memtype, 2);
u64 phys = vm_addr(vma, (u64)*list++, mem->memtype, target);
nv_wo32(pgt, pte + 0, lower_32_bits(phys));
nv_wo32(pgt, pte + 4, upper_32_bits(phys));
pte += 8;

17
drivers/gpu/drm/nouveau/nv50_vram.c
View File

@ -189,8 +189,25 @@ nv50_vram_init(struct drm_device *dev)
struct nouveau_vram_engine *vram = &dev_priv->engine.vram;
const u32 rsvd_head = ( 256 * 1024) >> 12; /* vga memory */
const u32 rsvd_tail = (1024 * 1024) >> 12; /* vbios etc */
u32 pfb714 = nv_rd32(dev, 0x100714);
u32 rblock, length;
switch (pfb714 & 0x00000007) {
case 0: dev_priv->vram_type = NV_MEM_TYPE_DDR1; break;
case 1:
if (nouveau_mem_vbios_type(dev) == NV_MEM_TYPE_DDR3)
dev_priv->vram_type = NV_MEM_TYPE_DDR3;
else
dev_priv->vram_type = NV_MEM_TYPE_DDR2;
break;
case 2: dev_priv->vram_type = NV_MEM_TYPE_GDDR3; break;
case 3: dev_priv->vram_type = NV_MEM_TYPE_GDDR4; break;
case 4: dev_priv->vram_type = NV_MEM_TYPE_GDDR5; break;
default:
break;
}
dev_priv->vram_rank_B = !!(nv_rd32(dev, 0x100200) & 0x4);
dev_priv->vram_size = nv_rd32(dev, 0x10020c);
dev_priv->vram_size |= (dev_priv->vram_size & 0xff) << 32;
dev_priv->vram_size &= 0xffffffff00ULL;

2
drivers/gpu/drm/nouveau/nvc0_pm.c
View File

@ -269,7 +269,7 @@ calc_clk(struct drm_device *dev, int clk, struct nvc0_pm_clock *info, u32 freq)
clk0 = calc_div(dev, clk, clk0, freq, &div1D);
/* see if we can get any closer using PLLs */
if (clk0 != freq) {
if (clk0 != freq && (0x00004387 & (1 << clk))) {
if (clk < 7)
clk1 = calc_pll(dev, clk, freq, &info->coef);
else

4
drivers/gpu/drm/nouveau/nvc0_vm.c
View File

@ -77,9 +77,11 @@ void
nvc0_vm_map_sg(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt,
struct nouveau_mem *mem, u32 pte, u32 cnt, dma_addr_t *list)
{
u32 target = (vma->access & NV_MEM_ACCESS_NOSNOOP) ? 7 : 5;
pte <<= 3;
while (cnt--) {
u64 phys = nvc0_vm_addr(vma, *list++, mem->memtype, 5);
u64 phys = nvc0_vm_addr(vma, *list++, mem->memtype, target);
nv_wo32(pgt, pte + 0, lower_32_bits(phys));
nv_wo32(pgt, pte + 4, upper_32_bits(phys));
pte += 8;

31
drivers/gpu/drm/nouveau/nvc0_vram.c
View File

@ -106,31 +106,32 @@ nvc0_vram_init(struct drm_device *dev)
struct nouveau_vram_engine *vram = &dev_priv->engine.vram;
const u32 rsvd_head = ( 256 * 1024) >> 12; /* vga memory */
const u32 rsvd_tail = (1024 * 1024) >> 12; /* vbios etc */
u32 parts = nv_rd32(dev, 0x121c74);
u32 parts = nv_rd32(dev, 0x022438);
u32 pmask = nv_rd32(dev, 0x022554);
u32 bsize = nv_rd32(dev, 0x10f20c);
u32 offset, length;
bool uniform = true;
int ret, part;
NV_DEBUG(dev, "0x100800: 0x%08x\n", nv_rd32(dev, 0x100800));
NV_DEBUG(dev, "parts 0x%08x bcast_mem_amount 0x%08x\n", parts, bsize);
NV_DEBUG(dev, "parts 0x%08x mask 0x%08x\n", parts, pmask);
dev_priv->vram_type = nouveau_mem_vbios_type(dev);
dev_priv->vram_rank_B = !!(nv_rd32(dev, 0x10f200) & 0x00000004);
/* read amount of vram attached to each memory controller */
part = 0;
while (parts) {
u32 psize = nv_rd32(dev, 0x11020c + (part++ * 0x1000));
if (psize == 0)
continue;
parts--;
for (part = 0; part < parts; part++) {
if (!(pmask & (1 << part))) {
u32 psize = nv_rd32(dev, 0x11020c + (part * 0x1000));
if (psize != bsize) {
if (psize < bsize)
bsize = psize;
uniform = false;
}
if (psize != bsize) {
if (psize < bsize)
bsize = psize;
uniform = false;
NV_DEBUG(dev, "%d: mem_amount 0x%08x\n", part, psize);
dev_priv->vram_size += (u64)psize << 20;
}
NV_DEBUG(dev, "%d: mem_amount 0x%08x\n", part, psize);
dev_priv->vram_size += (u64)psize << 20;
}
/* if all controllers have the same amount attached, there's no holes */

336
drivers/gpu/drm/nouveau/nvd0_display.c
View File

@ -284,6 +284,8 @@ nvd0_display_flip_next(struct drm_crtc *crtc, struct drm_framebuffer *fb,
u32 *push;
int ret;
evo_sync(crtc->dev, EVO_MASTER);
swap_interval <<= 4;
if (swap_interval == 0)
swap_interval |= 0x100;
@ -593,7 +595,7 @@ nvd0_crtc_commit(struct drm_crtc *crtc)
evo_kick(push, crtc->dev, EVO_MASTER);
}
nvd0_crtc_cursor_show(nv_crtc, nv_crtc->cursor.visible, false);
nvd0_crtc_cursor_show(nv_crtc, nv_crtc->cursor.visible, true);
nvd0_display_flip_next(crtc, crtc->fb, NULL, 1);
}
@ -634,8 +636,7 @@ nvd0_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *umode,
u32 hactive, hsynce, hbackp, hfrontp, hblanke, hblanks;
u32 vactive, vsynce, vbackp, vfrontp, vblanke, vblanks;
u32 vblan2e = 0, vblan2s = 1;
u32 magic = 0x31ec6000;
u32 syncs, *push;
u32 *push;
int ret;
hactive = mode->htotal;
@ -655,15 +656,8 @@ nvd0_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *umode,
vblan2e = vactive + vsynce + vbackp;
vblan2s = vblan2e + (mode->vdisplay * vscan / ilace);
vactive = (vactive * 2) + 1;
magic |= 0x00000001;
}
syncs = 0x00000001;
if (mode->flags & DRM_MODE_FLAG_NHSYNC)
syncs |= 0x00000008;
if (mode->flags & DRM_MODE_FLAG_NVSYNC)
syncs |= 0x00000010;
ret = nvd0_crtc_swap_fbs(crtc, old_fb);
if (ret)
return ret;
@ -683,9 +677,6 @@ nvd0_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *umode,
evo_data(push, mode->clock * 1000);
evo_data(push, 0x00200000); /* ??? */
evo_data(push, mode->clock * 1000);
evo_mthd(push, 0x0404 + (nv_crtc->index * 0x300), 2);
evo_data(push, syncs);
evo_data(push, magic);
evo_mthd(push, 0x04d0 + (nv_crtc->index * 0x300), 2);
evo_data(push, 0x00000311);
evo_data(push, 0x00000100);
@ -958,11 +949,6 @@ nvd0_dac_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
return true;
}
static void
nvd0_dac_prepare(struct drm_encoder *encoder)
{
}
static void
nvd0_dac_commit(struct drm_encoder *encoder)
{
@ -974,13 +960,26 @@ nvd0_dac_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
{
struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
u32 *push;
u32 syncs, magic, *push;
syncs = 0x00000001;
if (mode->flags & DRM_MODE_FLAG_NHSYNC)
syncs |= 0x00000008;
if (mode->flags & DRM_MODE_FLAG_NVSYNC)
syncs |= 0x00000010;
magic = 0x31ec6000 | (nv_crtc->index << 25);
if (mode->flags & DRM_MODE_FLAG_INTERLACE)
magic |= 0x00000001;
nvd0_dac_dpms(encoder, DRM_MODE_DPMS_ON);
push = evo_wait(encoder->dev, EVO_MASTER, 4);
push = evo_wait(encoder->dev, EVO_MASTER, 8);
if (push) {
evo_mthd(push, 0x0180 + (nv_encoder->or * 0x20), 2);
evo_mthd(push, 0x0404 + (nv_crtc->index * 0x300), 2);
evo_data(push, syncs);
evo_data(push, magic);
evo_mthd(push, 0x0180 + (nv_encoder->or * 0x020), 2);
evo_data(push, 1 << nv_crtc->index);
evo_data(push, 0x00ff);
evo_kick(push, encoder->dev, EVO_MASTER);
@ -1043,7 +1042,7 @@ nvd0_dac_destroy(struct drm_encoder *encoder)
static const struct drm_encoder_helper_funcs nvd0_dac_hfunc = {
.dpms = nvd0_dac_dpms,
.mode_fixup = nvd0_dac_mode_fixup,
.prepare = nvd0_dac_prepare,
.prepare = nvd0_dac_disconnect,
.commit = nvd0_dac_commit,
.mode_set = nvd0_dac_mode_set,
.disable = nvd0_dac_disconnect,
@ -1183,6 +1182,143 @@ nvd0_hdmi_disconnect(struct drm_encoder *encoder)
/******************************************************************************
* SOR
*****************************************************************************/
static inline u32
nvd0_sor_dp_lane_map(struct drm_device *dev, struct dcb_entry *dcb, u8 lane)
{
static const u8 nvd0[] = { 16, 8, 0, 24 };
return nvd0[lane];
}
static void
nvd0_sor_dp_train_set(struct drm_device *dev, struct dcb_entry *dcb, u8 pattern)
{
const u32 or = ffs(dcb->or) - 1, link = !(dcb->sorconf.link & 1);
const u32 loff = (or * 0x800) + (link * 0x80);
nv_mask(dev, 0x61c110 + loff, 0x0f0f0f0f, 0x01010101 * pattern);
}
static void
nvd0_sor_dp_train_adj(struct drm_device *dev, struct dcb_entry *dcb,
u8 lane, u8 swing, u8 preem)
{
const u32 or = ffs(dcb->or) - 1, link = !(dcb->sorconf.link & 1);
const u32 loff = (or * 0x800) + (link * 0x80);
u32 shift = nvd0_sor_dp_lane_map(dev, dcb, lane);
u32 mask = 0x000000ff << shift;
u8 *table, *entry, *config = NULL;
switch (swing) {
case 0: preem += 0; break;
case 1: preem += 4; break;
case 2: preem += 7; break;
case 3: preem += 9; break;
}
table = nouveau_dp_bios_data(dev, dcb, &entry);
if (table) {
if (table[0] == 0x30) {
config = entry + table[4];
config += table[5] * preem;
}
}
if (!config) {
NV_ERROR(dev, "PDISP: unsupported DP table for chipset\n");
return;
}
nv_mask(dev, 0x61c118 + loff, mask, config[1] << shift);
nv_mask(dev, 0x61c120 + loff, mask, config[2] << shift);
nv_mask(dev, 0x61c130 + loff, 0x0000ff00, config[3] << 8);
nv_mask(dev, 0x61c13c + loff, 0x00000000, 0x00000000);
}
static void
nvd0_sor_dp_link_set(struct drm_device *dev, struct dcb_entry *dcb, int crtc,
int link_nr, u32 link_bw, bool enhframe)
{
const u32 or = ffs(dcb->or) - 1, link = !(dcb->sorconf.link & 1);
const u32 loff = (or * 0x800) + (link * 0x80);
const u32 soff = (or * 0x800);
u32 dpctrl = nv_rd32(dev, 0x61c10c + loff) & ~0x001f4000;
u32 clksor = nv_rd32(dev, 0x612300 + soff) & ~0x007c0000;
u32 script = 0x0000, lane_mask = 0;
u8 *table, *entry;
int i;
link_bw /= 27000;
table = nouveau_dp_bios_data(dev, dcb, &entry);
if (table) {
if (table[0] == 0x30) entry = ROMPTR(dev, entry[10]);
else entry = NULL;
while (entry) {
if (entry[0] >= link_bw)
break;
entry += 3;
}
nouveau_bios_run_init_table(dev, script, dcb, crtc);
}
clksor |= link_bw << 18;
dpctrl |= ((1 << link_nr) - 1) << 16;
if (enhframe)
dpctrl |= 0x00004000;
for (i = 0; i < link_nr; i++)
lane_mask |= 1 << (nvd0_sor_dp_lane_map(dev, dcb, i) >> 3);
nv_wr32(dev, 0x612300 + soff, clksor);
nv_wr32(dev, 0x61c10c + loff, dpctrl);
nv_mask(dev, 0x61c130 + loff, 0x0000000f, lane_mask);
}
static void
nvd0_sor_dp_link_get(struct drm_device *dev, struct dcb_entry *dcb,
u32 *link_nr, u32 *link_bw)
{
const u32 or = ffs(dcb->or) - 1, link = !(dcb->sorconf.link & 1);
const u32 loff = (or * 0x800) + (link * 0x80);
const u32 soff = (or * 0x800);
u32 dpctrl = nv_rd32(dev, 0x61c10c + loff) & 0x000f0000;
u32 clksor = nv_rd32(dev, 0x612300 + soff);
if (dpctrl > 0x00030000) *link_nr = 4;
else if (dpctrl > 0x00010000) *link_nr = 2;
else *link_nr = 1;
*link_bw = (clksor & 0x007c0000) >> 18;
*link_bw *= 27000;
}
static void
nvd0_sor_dp_calc_tu(struct drm_device *dev, struct dcb_entry *dcb,
u32 crtc, u32 datarate)
{
const u32 symbol = 100000;
const u32 TU = 64;
u32 link_nr, link_bw;
u64 ratio, value;
nvd0_sor_dp_link_get(dev, dcb, &link_nr, &link_bw);
ratio = datarate;
ratio *= symbol;
do_div(ratio, link_nr * link_bw);
value = (symbol - ratio) * TU;
value *= ratio;
do_div(value, symbol);
do_div(value, symbol);
value += 5;
value |= 0x08000000;
nv_wr32(dev, 0x616610 + (crtc * 0x800), value);
}
static void
nvd0_sor_dpms(struct drm_encoder *encoder, int mode)
{
@ -1215,6 +1351,16 @@ nvd0_sor_dpms(struct drm_encoder *encoder, int mode)
nv_mask(dev, 0x61c004 + (or * 0x0800), 0x80000001, dpms_ctrl);
nv_wait(dev, 0x61c004 + (or * 0x0800), 0x80000000, 0x00000000);
nv_wait(dev, 0x61c030 + (or * 0x0800), 0x10000000, 0x00000000);
if (nv_encoder->dcb->type == OUTPUT_DP) {
struct dp_train_func func = {
.link_set = nvd0_sor_dp_link_set,
.train_set = nvd0_sor_dp_train_set,
.train_adj = nvd0_sor_dp_train_adj
};
nouveau_dp_dpms(encoder, mode, nv_encoder->dp.datarate, &func);
}
}
static bool
@ -1236,9 +1382,38 @@ nvd0_sor_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
return true;
}
static void
nvd0_sor_disconnect(struct drm_encoder *encoder)
{
struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
struct drm_device *dev = encoder->dev;
u32 *push;
if (nv_encoder->crtc) {
nvd0_crtc_prepare(nv_encoder->crtc);
push = evo_wait(dev, EVO_MASTER, 4);
if (push) {
evo_mthd(push, 0x0200 + (nv_encoder->or * 0x20), 1);
evo_data(push, 0x00000000);
evo_mthd(push, 0x0080, 1);
evo_data(push, 0x00000000);
evo_kick(push, dev, EVO_MASTER);
}
nvd0_hdmi_disconnect(encoder);
nv_encoder->crtc = NULL;
nv_encoder->last_dpms = DRM_MODE_DPMS_OFF;
}
}
static void
nvd0_sor_prepare(struct drm_encoder *encoder)
{
nvd0_sor_disconnect(encoder);
if (nouveau_encoder(encoder)->dcb->type == OUTPUT_DP)
evo_sync(encoder->dev, EVO_MASTER);
}
static void
@ -1257,7 +1432,18 @@ nvd0_sor_mode_set(struct drm_encoder *encoder, struct drm_display_mode *umode,
struct nouveau_connector *nv_connector;
struct nvbios *bios = &dev_priv->vbios;
u32 mode_ctrl = (1 << nv_crtc->index);
u32 *push, or_config;
u32 syncs, magic, *push;
u32 or_config;
syncs = 0x00000001;
if (mode->flags & DRM_MODE_FLAG_NHSYNC)
syncs |= 0x00000008;
if (mode->flags & DRM_MODE_FLAG_NVSYNC)
syncs |= 0x00000010;
magic = 0x31ec6000 | (nv_crtc->index << 25);
if (mode->flags & DRM_MODE_FLAG_INTERLACE)
magic |= 0x00000001;
nv_connector = nouveau_encoder_connector_get(nv_encoder);
switch (nv_encoder->dcb->type) {
@ -1306,6 +1492,22 @@ nvd0_sor_mode_set(struct drm_encoder *encoder, struct drm_display_mode *umode,
}
break;
case OUTPUT_DP:
if (nv_connector->base.display_info.bpc == 6) {
nv_encoder->dp.datarate = mode->clock * 18 / 8;
syncs |= 0x00000140;
} else {
nv_encoder->dp.datarate = mode->clock * 24 / 8;
syncs |= 0x00000180;
}
if (nv_encoder->dcb->sorconf.link & 1)
mode_ctrl |= 0x00000800;
else
mode_ctrl |= 0x00000900;
or_config = (mode_ctrl & 0x00000f00) >> 8;
break;
default:
BUG_ON(1);
break;
@ -1313,9 +1515,17 @@ nvd0_sor_mode_set(struct drm_encoder *encoder, struct drm_display_mode *umode,
nvd0_sor_dpms(encoder, DRM_MODE_DPMS_ON);
push = evo_wait(dev, EVO_MASTER, 4);
if (nv_encoder->dcb->type == OUTPUT_DP) {
nvd0_sor_dp_calc_tu(dev, nv_encoder->dcb, nv_crtc->index,
nv_encoder->dp.datarate);
}
push = evo_wait(dev, EVO_MASTER, 8);
if (push) {
evo_mthd(push, 0x0200 + (nv_encoder->or * 0x20), 2);
evo_mthd(push, 0x0404 + (nv_crtc->index * 0x300), 2);
evo_data(push, syncs);
evo_data(push, magic);
evo_mthd(push, 0x0200 + (nv_encoder->or * 0x020), 2);
evo_data(push, mode_ctrl);
evo_data(push, or_config);
evo_kick(push, dev, EVO_MASTER);
@ -1324,32 +1534,6 @@ nvd0_sor_mode_set(struct drm_encoder *encoder, struct drm_display_mode *umode,
nv_encoder->crtc = encoder->crtc;
}
static void
nvd0_sor_disconnect(struct drm_encoder *encoder)
{
struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
struct drm_device *dev = encoder->dev;
u32 *push;
if (nv_encoder->crtc) {
nvd0_crtc_prepare(nv_encoder->crtc);
push = evo_wait(dev, EVO_MASTER, 4);
if (push) {
evo_mthd(push, 0x0200 + (nv_encoder->or * 0x20), 1);
evo_data(push, 0x00000000);
evo_mthd(push, 0x0080, 1);
evo_data(push, 0x00000000);
evo_kick(push, dev, EVO_MASTER);
}
nvd0_hdmi_disconnect(encoder);
nv_encoder->crtc = NULL;
nv_encoder->last_dpms = DRM_MODE_DPMS_OFF;
}
}
static void
nvd0_sor_destroy(struct drm_encoder *encoder)
{
@ -1402,17 +1586,19 @@ static struct dcb_entry *
lookup_dcb(struct drm_device *dev, int id, u32 mc)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
int type, or, i;
int type, or, i, link = -1;
if (id < 4) {
type = OUTPUT_ANALOG;
or = id;
} else {
switch (mc & 0x00000f00) {
case 0x00000000: type = OUTPUT_LVDS; break;
case 0x00000100: type = OUTPUT_TMDS; break;
case 0x00000200: type = OUTPUT_TMDS; break;
case 0x00000500: type = OUTPUT_TMDS; break;
case 0x00000000: link = 0; type = OUTPUT_LVDS; break;
case 0x00000100: link = 0; type = OUTPUT_TMDS; break;
case 0x00000200: link = 1; type = OUTPUT_TMDS; break;
case 0x00000500: link = 0; type = OUTPUT_TMDS; break;
case 0x00000800: link = 0; type = OUTPUT_DP; break;
case 0x00000900: link = 1; type = OUTPUT_DP; break;
default:
NV_ERROR(dev, "PDISP: unknown SOR mc 0x%08x\n", mc);
return NULL;
@ -1423,7 +1609,8 @@ lookup_dcb(struct drm_device *dev, int id, u32 mc)
for (i = 0; i < dev_priv->vbios.dcb.entries; i++) {
struct dcb_entry *dcb = &dev_priv->vbios.dcb.entry[i];
if (dcb->type == type && (dcb->or & (1 << or)))
if (dcb->type == type && (dcb->or & (1 << or)) &&
(link < 0 || link == !(dcb->sorconf.link & 1)))
return dcb;
}
@ -1498,6 +1685,7 @@ nvd0_display_unk2_handler(struct drm_device *dev, u32 crtc, u32 mask)
break;
case OUTPUT_TMDS:
case OUTPUT_LVDS:
case OUTPUT_DP:
if (cfg & 0x00000100)
tmp = 0x00000101;
else
@ -1548,7 +1736,7 @@ nvd0_display_bh(unsigned long data)
{
struct drm_device *dev = (struct drm_device *)data;
struct nvd0_display *disp = nvd0_display(dev);
u32 mask, crtc;
u32 mask = 0, crtc = ~0;
int i;
if (drm_debug & (DRM_UT_DRIVER | DRM_UT_KMS)) {
@ -1564,12 +1752,8 @@ nvd0_display_bh(unsigned long data)
}
}
mask = nv_rd32(dev, 0x6101d4);
crtc = 0;
if (!mask) {
mask = nv_rd32(dev, 0x6109d4);
crtc = 1;
}
while (!mask && ++crtc < dev->mode_config.num_crtc)
mask = nv_rd32(dev, 0x6101d4 + (crtc * 0x800));
if (disp->modeset & 0x00000001)
nvd0_display_unk1_handler(dev, crtc, mask);
@ -1584,6 +1768,7 @@ nvd0_display_intr(struct drm_device *dev)
{
struct nvd0_display *disp = nvd0_display(dev);
u32 intr = nv_rd32(dev, 0x610088);
int i;
if (intr & 0x00000001) {
u32 stat = nv_rd32(dev, 0x61008c);
@ -1628,16 +1813,13 @@ nvd0_display_intr(struct drm_device *dev)
intr &= ~0x00100000;
}
if (intr & 0x01000000) {
u32 stat = nv_rd32(dev, 0x6100bc);
nv_wr32(dev, 0x6100bc, stat);
intr &= ~0x01000000;
}
if (intr & 0x02000000) {
u32 stat = nv_rd32(dev, 0x6108bc);
nv_wr32(dev, 0x6108bc, stat);
intr &= ~0x02000000;
for (i = 0; i < dev->mode_config.num_crtc; i++) {
u32 mask = 0x01000000 << i;
if (intr & mask) {
u32 stat = nv_rd32(dev, 0x6100bc + (i * 0x800));
nv_wr32(dev, 0x6100bc + (i * 0x800), stat);
intr &= ~mask;
}
}
if (intr)
@ -1774,7 +1956,7 @@ nvd0_display_create(struct drm_device *dev)
struct pci_dev *pdev = dev->pdev;
struct nvd0_display *disp;
struct dcb_entry *dcbe;
int ret, i;
int crtcs, ret, i;
disp = kzalloc(sizeof(*disp), GFP_KERNEL);
if (!disp)
@ -1782,7 +1964,8 @@ nvd0_display_create(struct drm_device *dev)
dev_priv->engine.display.priv = disp;
/* create crtc objects to represent the hw heads */
for (i = 0; i < 2; i++) {
crtcs = nv_rd32(dev, 0x022448);
for (i = 0; i < crtcs; i++) {
ret = nvd0_crtc_create(dev, i);
if (ret)
goto out;
@ -1803,6 +1986,7 @@ nvd0_display_create(struct drm_device *dev)
switch (dcbe->type) {
case OUTPUT_TMDS:
case OUTPUT_LVDS:
case OUTPUT_DP:
nvd0_sor_create(connector, dcbe);
break;
case OUTPUT_ANALOG: