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arm64: dts: hip05: Append all gicv3 ITS entries

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There are four subsystems in hip05 soc, peri/m3/pcie/dsa,
each subsystem has one its, append them under gicv3 node.

They will be used by hisilicon mbigen.

Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
This commit is contained in:
Kefeng Wang 2016-01-29 16:39:03 +08:00 committed by Wei Xu
parent 6897db62bb
commit abf9c25d55
1 changed files with 19 additions and 1 deletions
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20
arch/arm64/boot/dts/hisilicon/hip05.dtsi
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@ -246,11 +246,29 @@
<0x0 0xfe020000 0 0x10000>; /* GICV */ <0x0 0xfe020000 0 0x10000>; /* GICV */
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
its_totems: interrupt-controller@8c000000 { its_peri: interrupt-controller@8c000000 {
compatible = "arm,gic-v3-its"; compatible = "arm,gic-v3-its";
msi-controller; msi-controller;
reg = <0x0 0x8c000000 0x0 0x40000>; reg = <0x0 0x8c000000 0x0 0x40000>;
}; };
its_m3: interrupt-controller@a3000000 {
compatible = "arm,gic-v3-its";
msi-controller;
reg = <0x0 0xa3000000 0x0 0x40000>;
};
its_pcie: interrupt-controller@b7000000 {
compatible = "arm,gic-v3-its";
msi-controller;
reg = <0x0 0xb7000000 0x0 0x40000>;
};
its_dsa: interrupt-controller@c6000000 {
compatible = "arm,gic-v3-its";
msi-controller;
reg = <0x0 0xc6000000 0x0 0x40000>;
};
}; };
timer { timer {