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net: phy: nxp-c45-tja11xx: use phylib master/slave implementation

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Remove the custom implementation of master/save setup and read status
and use genphy_c45_config_aneg and genphy_c45_read_status since phylib
has support for master/slave setup and master/slave status.

Signed-off-by: Radu Pirea (NXP OSS) <radu-nicolae.pirea@oss.nxp.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Link: https://lore.kernel.org/r/20230731091619.77961-2-radu-nicolae.pirea@oss.nxp.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Radu Pirea (NXP OSS) 2023-07-31 12:16:09 +03:00 committed by Jakub Kicinski
parent b9e643f0ad
commit ac0687e821
1 changed files with 2 additions and 75 deletions
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77
drivers/net/phy/nxp-c45-tja11xx.c
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@ -19,13 +19,6 @@
#define PHY_ID_TJA_1103 0x001BB010 #define PHY_ID_TJA_1103 0x001BB010
#define PMAPMD_B100T1_PMAPMD_CTL 0x0834
#define B100T1_PMAPMD_CONFIG_EN BIT(15)
#define B100T1_PMAPMD_MASTER BIT(14)
#define MASTER_MODE (B100T1_PMAPMD_CONFIG_EN | \
B100T1_PMAPMD_MASTER)
#define SLAVE_MODE (B100T1_PMAPMD_CONFIG_EN)
#define VEND1_DEVICE_CONTROL 0x0040 #define VEND1_DEVICE_CONTROL 0x0040
#define DEVICE_CONTROL_RESET BIT(15) #define DEVICE_CONTROL_RESET BIT(15)
#define DEVICE_CONTROL_CONFIG_GLOBAL_EN BIT(14) #define DEVICE_CONTROL_CONFIG_GLOBAL_EN BIT(14)
@ -988,72 +981,6 @@ static int nxp_c45_cable_test_get_status(struct phy_device *phydev,
return nxp_c45_start_op(phydev); return nxp_c45_start_op(phydev);
} }
static int nxp_c45_setup_master_slave(struct phy_device *phydev)
{
switch (phydev->master_slave_set) {
case MASTER_SLAVE_CFG_MASTER_FORCE:
case MASTER_SLAVE_CFG_MASTER_PREFERRED:
phy_write_mmd(phydev, MDIO_MMD_PMAPMD, PMAPMD_B100T1_PMAPMD_CTL,
MASTER_MODE);
break;
case MASTER_SLAVE_CFG_SLAVE_PREFERRED:
case MASTER_SLAVE_CFG_SLAVE_FORCE:
phy_write_mmd(phydev, MDIO_MMD_PMAPMD, PMAPMD_B100T1_PMAPMD_CTL,
SLAVE_MODE);
break;
case MASTER_SLAVE_CFG_UNKNOWN:
case MASTER_SLAVE_CFG_UNSUPPORTED:
return 0;
default:
phydev_warn(phydev, "Unsupported Master/Slave mode\n");
return -EOPNOTSUPP;
}
return 0;
}
static int nxp_c45_read_master_slave(struct phy_device *phydev)
{
int reg;
phydev->master_slave_get = MASTER_SLAVE_CFG_UNKNOWN;
phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN;
reg = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, PMAPMD_B100T1_PMAPMD_CTL);
if (reg < 0)
return reg;
if (reg & B100T1_PMAPMD_MASTER) {
phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_FORCE;
phydev->master_slave_state = MASTER_SLAVE_STATE_MASTER;
} else {
phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_FORCE;
phydev->master_slave_state = MASTER_SLAVE_STATE_SLAVE;
}
return 0;
}
static int nxp_c45_config_aneg(struct phy_device *phydev)
{
return nxp_c45_setup_master_slave(phydev);
}
static int nxp_c45_read_status(struct phy_device *phydev)
{
int ret;
ret = genphy_c45_read_status(phydev);
if (ret)
return ret;
ret = nxp_c45_read_master_slave(phydev);
if (ret)
return ret;
return 0;
}
static int nxp_c45_get_sqi(struct phy_device *phydev) static int nxp_c45_get_sqi(struct phy_device *phydev)
{ {
int reg; int reg;
@ -1355,11 +1282,11 @@ static struct phy_driver nxp_c45_driver[] = {
.features = PHY_BASIC_T1_FEATURES, .features = PHY_BASIC_T1_FEATURES,
.probe = nxp_c45_probe, .probe = nxp_c45_probe,
.soft_reset = nxp_c45_soft_reset, .soft_reset = nxp_c45_soft_reset,
.config_aneg = nxp_c45_config_aneg, .config_aneg = genphy_c45_config_aneg,
.config_init = nxp_c45_config_init, .config_init = nxp_c45_config_init,
.config_intr = nxp_c45_config_intr, .config_intr = nxp_c45_config_intr,
.handle_interrupt = nxp_c45_handle_interrupt, .handle_interrupt = nxp_c45_handle_interrupt,
.read_status = nxp_c45_read_status, .read_status = genphy_c45_read_status,
.suspend = genphy_c45_pma_suspend, .suspend = genphy_c45_pma_suspend,
.resume = genphy_c45_pma_resume, .resume = genphy_c45_pma_resume,
.get_sset_count = nxp_c45_get_sset_count, .get_sset_count = nxp_c45_get_sset_count,