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perf: imx_perf: fix counter start and config sequence

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In current driver, the counter will start firstly and then be configured.
This sequence is not correct for AXI filter events since the correct
AXI_MASK and AXI_ID are not set yet. Then the results may be inaccurate.

Reviewed-by: Frank Li <Frank.Li@nxp.com>
Fixes: 55691f99d4 ("drivers/perf: imx_ddr: Add support for NXP i.MX9 SoC DDRC PMU driver")
cc: stable@vger.kernel.org
Signed-off-by: Xu Yang <xu.yang_2@nxp.com>
Link: https://lore.kernel.org/r/20240529080358.703784-5-xu.yang_2@nxp.com
Signed-off-by: Will Deacon <will@kernel.org>
This commit is contained in:
Xu Yang 2024-05-29 16:03:55 +08:00 committed by Will Deacon
parent fab5e5a866
commit ac9aa295f7
1 changed files with 3 additions and 3 deletions
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6
drivers/perf/fsl_imx9_ddr_perf.c
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@ -541,12 +541,12 @@ static int ddr_perf_event_add(struct perf_event *event, int flags)
hwc->idx = counter;
hwc->state |= PERF_HES_STOPPED;
if (flags & PERF_EF_START)
ddr_perf_event_start(event, flags);
/* read trans, write trans, read beat */
imx93_ddr_perf_monitor_config(pmu, event_id, counter, cfg1, cfg2);
if (flags & PERF_EF_START)
ddr_perf_event_start(event, flags);
return 0;
}