iommu/arm-smmu: Report IOMMU_CAP_CACHE_COHERENCY even betterer
Although it's vanishingly unlikely that anyone would integrate an SMMU
within a coherent interconnect without also making the pagetable walk
interface coherent, the same effect happens if a coherent SMMU fails to
advertise CTTW correctly. This turns out to be the case on some popular
NXP SoCs, where VFIO started failing the IOMMU_CAP_CACHE_COHERENCY test,
even though IOMMU_CACHE *was* previously achieving the desired effect
anyway thanks to the underlying integration.
While those SoCs stand to gain some more general benefits from a
firmware update to override CTTW correctly in DT/ACPI, it's also easy
to work around this in Linux as well, to avoid imposing too much on
affected users - since the upstream client devices *are* correctly
marked as coherent, we can trivially infer their coherent paths through
the SMMU as well.
Reported-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Fixes: df198b37e7
("iommu/arm-smmu: Report IOMMU_CAP_CACHE_COHERENCY better")
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Tested-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Link: https://lore.kernel.org/r/d6dc41952961e5c7b21acac08a8bf1eb0f69e124.1671123115.git.robin.murphy@arm.com
Signed-off-by: Will Deacon <will@kernel.org>
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@ -1316,8 +1316,14 @@ static bool arm_smmu_capable(struct device *dev, enum iommu_cap cap)
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switch (cap) {
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case IOMMU_CAP_CACHE_COHERENCY:
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/* Assume that a coherent TCU implies coherent TBUs */
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return cfg->smmu->features & ARM_SMMU_FEAT_COHERENT_WALK;
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/*
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* It's overwhelmingly the case in practice that when the pagetable
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* walk interface is connected to a coherent interconnect, all the
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* translation interfaces are too. Furthermore if the device is
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* natively coherent, then its translation interface must also be.
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*/
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return cfg->smmu->features & ARM_SMMU_FEAT_COHERENT_WALK ||
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device_get_dma_attr(dev) == DEV_DMA_COHERENT;
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case IOMMU_CAP_NOEXEC:
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return true;
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default:
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