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Renesas driver updates for v5.8

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- Add System Controller (SYSC) and Reset (RST) support for the new
     RZ/G1H (R8A7742) SoC.
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Merge tag 'renesas-drivers-for-v5.8-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/drivers

Renesas driver updates for v5.8

  - Add System Controller (SYSC) and Reset (RST) support for the new
    RZ/G1H (R8A7742) SoC.

* tag 'renesas-drivers-for-v5.8-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
  soc: renesas: rcar-rst: Add support for RZ/G1H
  soc: renesas: rcar-sysc: Add R8A7742 support
  clk: renesas: Add r8a7742 CPG Core Clock Definitions
  dt-bindings: power: rcar-sysc: Add r8a7742 power domain index macros

Link: https://lore.kernel.org/r/20200430084849.1457-5-geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2020-05-25 16:25:11 +02:00
commit acb09eca32
8 changed files with 123 additions and 0 deletions
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4
drivers/soc/renesas/Kconfig
View File

@ -261,6 +261,10 @@ config ARCH_R8A77995
endif # ARM64
# SoC
config SYSC_R8A7742
bool "RZ/G1H System Controller support" if COMPILE_TEST
select SYSC_RCAR
config SYSC_R8A7743
bool "RZ/G1M System Controller support" if COMPILE_TEST
select SYSC_RCAR

1
drivers/soc/renesas/Makefile
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@ -3,6 +3,7 @@
obj-$(CONFIG_SOC_RENESAS) += renesas-soc.o
# SoC
obj-$(CONFIG_SYSC_R8A7742) += r8a7742-sysc.o
obj-$(CONFIG_SYSC_R8A7743) += r8a7743-sysc.o
obj-$(CONFIG_SYSC_R8A7745) += r8a7745-sysc.o
obj-$(CONFIG_SYSC_R8A77470) += r8a77470-sysc.o

42
drivers/soc/renesas/r8a7742-sysc.c Normal file
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@ -0,0 +1,42 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Renesas RZ/G1H System Controller
*
* Copyright (C) 2020 Renesas Electronics Corp.
*/
#include <linux/kernel.h>
#include <dt-bindings/power/r8a7742-sysc.h>
#include "rcar-sysc.h"
static const struct rcar_sysc_area r8a7742_areas[] __initconst = {
{ "always-on", 0, 0, R8A7742_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
{ "ca15-scu", 0x180, 0, R8A7742_PD_CA15_SCU, R8A7742_PD_ALWAYS_ON,
PD_SCU },
{ "ca15-cpu0", 0x40, 0, R8A7742_PD_CA15_CPU0, R8A7742_PD_CA15_SCU,
PD_CPU_NOCR },
{ "ca15-cpu1", 0x40, 1, R8A7742_PD_CA15_CPU1, R8A7742_PD_CA15_SCU,
PD_CPU_NOCR },
{ "ca15-cpu2", 0x40, 2, R8A7742_PD_CA15_CPU2, R8A7742_PD_CA15_SCU,
PD_CPU_NOCR },
{ "ca15-cpu3", 0x40, 3, R8A7742_PD_CA15_CPU3, R8A7742_PD_CA15_SCU,
PD_CPU_NOCR },
{ "ca7-scu", 0x100, 0, R8A7742_PD_CA7_SCU, R8A7742_PD_ALWAYS_ON,
PD_SCU },
{ "ca7-cpu0", 0x1c0, 0, R8A7742_PD_CA7_CPU0, R8A7742_PD_CA7_SCU,
PD_CPU_NOCR },
{ "ca7-cpu1", 0x1c0, 1, R8A7742_PD_CA7_CPU1, R8A7742_PD_CA7_SCU,
PD_CPU_NOCR },
{ "ca7-cpu2", 0x1c0, 2, R8A7742_PD_CA7_CPU2, R8A7742_PD_CA7_SCU,
PD_CPU_NOCR },
{ "ca7-cpu3", 0x1c0, 3, R8A7742_PD_CA7_CPU3, R8A7742_PD_CA7_SCU,
PD_CPU_NOCR },
{ "rgx", 0xc0, 0, R8A7742_PD_RGX, R8A7742_PD_ALWAYS_ON },
};
const struct rcar_sysc_info r8a7742_sysc_info __initconst = {
.areas = r8a7742_areas,
.num_areas = ARRAY_SIZE(r8a7742_areas),
};

1
drivers/soc/renesas/rcar-rst.c
View File

@ -39,6 +39,7 @@ static const struct rst_config rcar_rst_gen3 __initconst = {
static const struct of_device_id rcar_rst_matches[] __initconst = {
/* RZ/G1 is handled like R-Car Gen2 */
{ .compatible = "renesas,r8a7742-rst", .data = &rcar_rst_gen2 },
{ .compatible = "renesas,r8a7743-rst", .data = &rcar_rst_gen2 },
{ .compatible = "renesas,r8a7744-rst", .data = &rcar_rst_gen2 },
{ .compatible = "renesas,r8a7745-rst", .data = &rcar_rst_gen2 },

3
drivers/soc/renesas/rcar-sysc.c
View File

@ -273,6 +273,9 @@ finalize:
}
static const struct of_device_id rcar_sysc_matches[] __initconst = {
#ifdef CONFIG_SYSC_R8A7742
{ .compatible = "renesas,r8a7742-sysc", .data = &r8a7742_sysc_info },
#endif
#ifdef CONFIG_SYSC_R8A7743
{ .compatible = "renesas,r8a7743-sysc", .data = &r8a7743_sysc_info },
/* RZ/G1N is identical to RZ/G2M w.r.t. power domains. */

1
drivers/soc/renesas/rcar-sysc.h
View File

@ -49,6 +49,7 @@ struct rcar_sysc_info {
u32 extmask_val; /* SYSCEXTMASK register mask value */
};
extern const struct rcar_sysc_info r8a7742_sysc_info;
extern const struct rcar_sysc_info r8a7743_sysc_info;
extern const struct rcar_sysc_info r8a7745_sysc_info;
extern const struct rcar_sysc_info r8a77470_sysc_info;

42
include/dt-bindings/clock/r8a7742-cpg-mssr.h Normal file
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@ -0,0 +1,42 @@
/* SPDX-License-Identifier: GPL-2.0+
*
* Copyright (C) 2020 Renesas Electronics Corp.
*/
#ifndef __DT_BINDINGS_CLOCK_R8A7742_CPG_MSSR_H__
#define __DT_BINDINGS_CLOCK_R8A7742_CPG_MSSR_H__
#include <dt-bindings/clock/renesas-cpg-mssr.h>
/* r8a7742 CPG Core Clocks */
#define R8A7742_CLK_Z 0
#define R8A7742_CLK_Z2 1
#define R8A7742_CLK_ZG 2
#define R8A7742_CLK_ZTR 3
#define R8A7742_CLK_ZTRD2 4
#define R8A7742_CLK_ZT 5
#define R8A7742_CLK_ZX 6
#define R8A7742_CLK_ZS 7
#define R8A7742_CLK_HP 8
#define R8A7742_CLK_B 9
#define R8A7742_CLK_LB 10
#define R8A7742_CLK_P 11
#define R8A7742_CLK_CL 12
#define R8A7742_CLK_M2 13
#define R8A7742_CLK_ZB3 14
#define R8A7742_CLK_ZB3D2 15
#define R8A7742_CLK_DDR 16
#define R8A7742_CLK_SDH 17
#define R8A7742_CLK_SD0 18
#define R8A7742_CLK_SD1 19
#define R8A7742_CLK_SD2 20
#define R8A7742_CLK_SD3 21
#define R8A7742_CLK_MMC0 22
#define R8A7742_CLK_MMC1 23
#define R8A7742_CLK_MP 24
#define R8A7742_CLK_QSPI 25
#define R8A7742_CLK_CP 26
#define R8A7742_CLK_RCAN 27
#define R8A7742_CLK_R 28
#define R8A7742_CLK_OSC 29
#endif /* __DT_BINDINGS_CLOCK_R8A7742_CPG_MSSR_H__ */

29
include/dt-bindings/power/r8a7742-sysc.h Normal file
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@ -0,0 +1,29 @@
/* SPDX-License-Identifier: GPL-2.0
*
* Copyright (C) 2020 Renesas Electronics Corp.
*/
#ifndef __DT_BINDINGS_POWER_R8A7742_SYSC_H__
#define __DT_BINDINGS_POWER_R8A7742_SYSC_H__
/*
* These power domain indices match the numbers of the interrupt bits
* representing the power areas in the various Interrupt Registers
* (e.g. SYSCISR, Interrupt Status Register)
*/
#define R8A7742_PD_CA15_CPU0 0
#define R8A7742_PD_CA15_CPU1 1
#define R8A7742_PD_CA15_CPU2 2
#define R8A7742_PD_CA15_CPU3 3
#define R8A7742_PD_CA7_CPU0 5
#define R8A7742_PD_CA7_CPU1 6
#define R8A7742_PD_CA7_CPU2 7
#define R8A7742_PD_CA7_CPU3 8
#define R8A7742_PD_CA15_SCU 12
#define R8A7742_PD_RGX 20
#define R8A7742_PD_CA7_SCU 21
/* Always-on power area */
#define R8A7742_PD_ALWAYS_ON 32
#endif /* __DT_BINDINGS_POWER_R8A7742_SYSC_H__ */