drm/i915: Reset the breadcrumbs IRQ more carefully
Along with the interrupt, we want to restore the fake-irq and
wait-timeout detection. If we use the breadcrumbs interface to setup the
interrupt as it wants, the auxiliary timers will also be restored.
v2: Cancel both timers as well, sanitize the IMR.
Fixes: 821ed7df6e
("drm/i915: Update reset path to fix incomplete requests")
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20161007065327.24515-3-chris@chris-wilson.co.uk
This commit is contained in:
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@ -578,6 +578,36 @@ int intel_engine_init_breadcrumbs(struct intel_engine_cs *engine)
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return 0;
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}
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static void cancel_fake_irq(struct intel_engine_cs *engine)
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{
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struct intel_breadcrumbs *b = &engine->breadcrumbs;
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del_timer_sync(&b->hangcheck);
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del_timer_sync(&b->fake_irq);
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clear_bit(engine->id, &engine->i915->gpu_error.missed_irq_rings);
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}
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void intel_engine_reset_breadcrumbs(struct intel_engine_cs *engine)
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{
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struct intel_breadcrumbs *b = &engine->breadcrumbs;
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cancel_fake_irq(engine);
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spin_lock(&b->lock);
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__intel_breadcrumbs_disable_irq(b);
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if (intel_engine_has_waiter(engine)) {
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b->timeout = wait_timeout();
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__intel_breadcrumbs_enable_irq(b);
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if (READ_ONCE(b->irq_posted))
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wake_up_process(b->first_wait->tsk);
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} else {
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/* sanitize the IMR and unmask any auxiliary interrupts */
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irq_disable(engine);
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}
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spin_unlock(&b->lock);
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}
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void intel_engine_fini_breadcrumbs(struct intel_engine_cs *engine)
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{
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struct intel_breadcrumbs *b = &engine->breadcrumbs;
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@ -585,8 +615,7 @@ void intel_engine_fini_breadcrumbs(struct intel_engine_cs *engine)
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if (!IS_ERR_OR_NULL(b->signaler))
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kthread_stop(b->signaler);
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del_timer_sync(&b->hangcheck);
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del_timer_sync(&b->fake_irq);
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cancel_fake_irq(engine);
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}
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unsigned int intel_kick_waiters(struct drm_i915_private *i915)
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@ -210,9 +210,6 @@ void intel_engine_init_seqno(struct intel_engine_cs *engine, u32 seqno)
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void intel_engine_init_hangcheck(struct intel_engine_cs *engine)
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{
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memset(&engine->hangcheck, 0, sizeof(engine->hangcheck));
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clear_bit(engine->id, &engine->i915->gpu_error.missed_irq_rings);
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if (intel_engine_has_waiter(engine))
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i915_queue_hangcheck(engine->i915);
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}
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static void intel_engine_init_requests(struct intel_engine_cs *engine)
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@ -307,18 +304,6 @@ int intel_engine_init_common(struct intel_engine_cs *engine)
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return 0;
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}
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void intel_engine_reset_irq(struct intel_engine_cs *engine)
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{
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struct drm_i915_private *dev_priv = engine->i915;
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spin_lock_irq(&dev_priv->irq_lock);
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if (intel_engine_has_waiter(engine))
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engine->irq_enable(engine);
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else
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engine->irq_disable(engine);
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spin_unlock_irq(&dev_priv->irq_lock);
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}
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/**
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* intel_engines_cleanup_common - cleans up the engine state created by
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* the common initiailizers.
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@ -1230,7 +1230,7 @@ static int gen8_init_common_ring(struct intel_engine_cs *engine)
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lrc_init_hws(engine);
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intel_engine_reset_irq(engine);
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intel_engine_reset_breadcrumbs(engine);
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I915_WRITE(RING_HWSTAM(engine->mmio_base), 0xffffffff);
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@ -548,7 +548,7 @@ static int init_ring_common(struct intel_engine_cs *engine)
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else
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intel_ring_setup_status_page(engine);
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intel_engine_reset_irq(engine);
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intel_engine_reset_breadcrumbs(engine);
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/* Enforce ordering by reading HEAD register back */
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I915_READ_HEAD(engine);
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@ -520,7 +520,6 @@ int __intel_ring_space(int head, int tail, int size);
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void intel_ring_update_space(struct intel_ring *ring);
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void intel_engine_init_seqno(struct intel_engine_cs *engine, u32 seqno);
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void intel_engine_reset_irq(struct intel_engine_cs *engine);
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void intel_engine_setup_common(struct intel_engine_cs *engine);
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int intel_engine_init_common(struct intel_engine_cs *engine);
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@ -614,6 +613,7 @@ static inline bool intel_engine_wakeup(const struct intel_engine_cs *engine)
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return wakeup;
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}
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void intel_engine_reset_breadcrumbs(struct intel_engine_cs *engine);
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void intel_engine_fini_breadcrumbs(struct intel_engine_cs *engine);
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unsigned int intel_kick_waiters(struct drm_i915_private *i915);
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unsigned int intel_kick_signalers(struct drm_i915_private *i915);
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