powerpc: drop MPC8272-ADS and PowerQUICC II FADS shared code.
With the two platforms depending on this shared code, and no others, we can remove the orphaned code and Kconfigs Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://msgid.link/20230224204959.17425-4-paul.gortmaker@windriver.com
This commit is contained in:
Paul Gortmaker
Michael Ellerman
parent
859b21a008
commit
ad46ad2d85
@ -13,10 +13,6 @@
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#ifdef CONFIG_8260
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#if defined(CONFIG_PQ2ADS) || defined (CONFIG_PQ2FADS)
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#include <platforms/82xx/pq2ads.h>
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#endif
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#ifdef CONFIG_PCI_8260
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#include <platforms/82xx/m82xx_pci.h>
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#endif
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@ -28,9 +28,6 @@ config MGCOGE
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endif
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config PQ2ADS
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bool
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config 8260
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bool
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depends on PPC_BOOK3S_32
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@ -46,6 +43,3 @@ config 8272
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help
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The MPC8272 CPM has a different internal dpram setup than other CPM2
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devices
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config PQ2_ADS_PCI_PIC
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bool
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@ -3,6 +3,5 @@
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# Makefile for the PowerPC 82xx linux kernel.
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#
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obj-$(CONFIG_CPM2) += pq2.o
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obj-$(CONFIG_PQ2_ADS_PCI_PIC) += pq2ads-pci-pic.o
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obj-$(CONFIG_EP8248E) += ep8248e.o
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obj-$(CONFIG_MGCOGE) += km82xx.o
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@ -1,172 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* PQ2 ADS-style PCI interrupt controller
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*
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* Copyright 2007 Freescale Semiconductor, Inc.
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* Author: Scott Wood <scottwood@freescale.com>
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*
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* Loosely based on mpc82xx ADS support by Vitaly Bordug <vbordug@ru.mvista.com>
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* Copyright (c) 2006 MontaVista Software, Inc.
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*/
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#include <linux/init.h>
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#include <linux/spinlock.h>
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#include <linux/irq.h>
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#include <linux/types.h>
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#include <linux/slab.h>
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#include <linux/of_irq.h>
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#include <asm/io.h>
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#include <asm/cpm2.h>
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#include "pq2.h"
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static DEFINE_RAW_SPINLOCK(pci_pic_lock);
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struct pq2ads_pci_pic {
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struct device_node *node;
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struct irq_domain *host;
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struct {
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u32 stat;
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u32 mask;
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} __iomem *regs;
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};
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#define NUM_IRQS 32
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static void pq2ads_pci_mask_irq(struct irq_data *d)
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{
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struct pq2ads_pci_pic *priv = irq_data_get_irq_chip_data(d);
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int irq = NUM_IRQS - irqd_to_hwirq(d) - 1;
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if (irq != -1) {
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unsigned long flags;
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raw_spin_lock_irqsave(&pci_pic_lock, flags);
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setbits32(&priv->regs->mask, 1 << irq);
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mb();
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raw_spin_unlock_irqrestore(&pci_pic_lock, flags);
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}
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}
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static void pq2ads_pci_unmask_irq(struct irq_data *d)
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{
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struct pq2ads_pci_pic *priv = irq_data_get_irq_chip_data(d);
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int irq = NUM_IRQS - irqd_to_hwirq(d) - 1;
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if (irq != -1) {
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unsigned long flags;
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raw_spin_lock_irqsave(&pci_pic_lock, flags);
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clrbits32(&priv->regs->mask, 1 << irq);
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raw_spin_unlock_irqrestore(&pci_pic_lock, flags);
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}
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}
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static struct irq_chip pq2ads_pci_ic = {
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.name = "PQ2 ADS PCI",
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.irq_mask = pq2ads_pci_mask_irq,
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.irq_mask_ack = pq2ads_pci_mask_irq,
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.irq_ack = pq2ads_pci_mask_irq,
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.irq_unmask = pq2ads_pci_unmask_irq,
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.irq_enable = pq2ads_pci_unmask_irq,
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.irq_disable = pq2ads_pci_mask_irq
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};
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static void pq2ads_pci_irq_demux(struct irq_desc *desc)
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{
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struct pq2ads_pci_pic *priv = irq_desc_get_handler_data(desc);
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u32 stat, mask, pend;
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int bit;
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for (;;) {
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stat = in_be32(&priv->regs->stat);
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mask = in_be32(&priv->regs->mask);
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pend = stat & ~mask;
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if (!pend)
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break;
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for (bit = 0; pend != 0; ++bit, pend <<= 1) {
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if (pend & 0x80000000)
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generic_handle_domain_irq(priv->host, bit);
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}
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}
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}
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static int pci_pic_host_map(struct irq_domain *h, unsigned int virq,
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irq_hw_number_t hw)
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{
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irq_set_status_flags(virq, IRQ_LEVEL);
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irq_set_chip_data(virq, h->host_data);
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irq_set_chip_and_handler(virq, &pq2ads_pci_ic, handle_level_irq);
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return 0;
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}
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static const struct irq_domain_ops pci_pic_host_ops = {
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.map = pci_pic_host_map,
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};
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int __init pq2ads_pci_init_irq(void)
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{
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struct pq2ads_pci_pic *priv;
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struct irq_domain *host;
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struct device_node *np;
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int ret = -ENODEV;
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int irq;
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np = of_find_compatible_node(NULL, NULL, "fsl,pq2ads-pci-pic");
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if (!np) {
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printk(KERN_ERR "No pci pic node in device tree.\n");
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goto out;
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}
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irq = irq_of_parse_and_map(np, 0);
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if (!irq) {
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printk(KERN_ERR "No interrupt in pci pic node.\n");
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goto out_put_node;
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}
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priv = kzalloc(sizeof(*priv), GFP_KERNEL);
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if (!priv) {
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ret = -ENOMEM;
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goto out_unmap_irq;
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}
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/* PCI interrupt controller registers: status and mask */
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priv->regs = of_iomap(np, 0);
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if (!priv->regs) {
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printk(KERN_ERR "Cannot map PCI PIC registers.\n");
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goto out_free_kmalloc;
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}
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/* mask all PCI interrupts */
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out_be32(&priv->regs->mask, ~0);
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mb();
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host = irq_domain_add_linear(np, NUM_IRQS, &pci_pic_host_ops, priv);
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if (!host) {
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ret = -ENOMEM;
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goto out_unmap_regs;
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}
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priv->host = host;
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irq_set_handler_data(irq, priv);
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irq_set_chained_handler(irq, pq2ads_pci_irq_demux);
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ret = 0;
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goto out_put_node;
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out_unmap_regs:
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iounmap(priv->regs);
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out_free_kmalloc:
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kfree(priv);
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out_unmap_irq:
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irq_dispose_mapping(irq);
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out_put_node:
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of_node_put(np);
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out:
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return ret;
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}
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@ -1,40 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* PQ2/mpc8260 board-specific stuff
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*
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* A collection of structures, addresses, and values associated with
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* the Freescale MPC8260ADS/MPC8266ADS-PCI boards.
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* Copied from the RPX-Classic and SBS8260 stuff.
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*
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* Author: Vitaly Bordug <vbordug@ru.mvista.com>
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*
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* Originally written by Dan Malek for Motorola MPC8260 family
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*
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* Copyright (c) 2001 Dan Malek <dan@embeddedalley.com>
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* Copyright (c) 2006 MontaVista Software, Inc.
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*/
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#ifdef __KERNEL__
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#ifndef __MACH_ADS8260_DEFS
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#define __MACH_ADS8260_DEFS
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#include <linux/seq_file.h>
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/* The ADS8260 has 16, 32-bit wide control/status registers, accessed
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* only on word boundaries.
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* Not all are used (yet), or are interesting to us (yet).
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*/
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/* Things of interest in the CSR.
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*/
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#define BCSR0_LED0 ((uint)0x02000000) /* 0 == on */
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#define BCSR0_LED1 ((uint)0x01000000) /* 0 == on */
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#define BCSR1_FETHIEN ((uint)0x08000000) /* 0 == enable*/
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#define BCSR1_FETH_RST ((uint)0x04000000) /* 0 == reset */
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#define BCSR1_RS232_EN1 ((uint)0x02000000) /* 0 ==enable */
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#define BCSR1_RS232_EN2 ((uint)0x01000000) /* 0 ==enable */
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#define BCSR3_FETHIEN2 ((uint)0x10000000) /* 0 == enable*/
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#define BCSR3_FETH2_RST ((uint)0x80000000) /* 0 == reset */
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#endif /* __MACH_ADS8260_DEFS */
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#endif /* __KERNEL__ */
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