riscv: cpu: Add 64bit hartid support on RV64
The hartid can be a 64bit value on RV64 platforms. Add support for 64bit hartid in riscv_of_processor_hartid() and update its callers. Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Reviewed-by: Atish Patra <atishp@rivosinc.com> Link: https://lore.kernel.org/r/20220527051743.2829940-5-sunilvl@ventanamicro.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
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@ -79,8 +79,8 @@ static inline void wait_for_interrupt(void)
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}
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struct device_node;
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int riscv_of_processor_hartid(struct device_node *node);
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int riscv_of_parent_hartid(struct device_node *node);
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int riscv_of_processor_hartid(struct device_node *node, unsigned long *hartid);
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int riscv_of_parent_hartid(struct device_node *node, unsigned long *hartid);
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extern void riscv_fill_hwcap(void);
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extern int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src);
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@ -14,37 +14,36 @@
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* Returns the hart ID of the given device tree node, or -ENODEV if the node
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* isn't an enabled and valid RISC-V hart node.
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*/
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int riscv_of_processor_hartid(struct device_node *node)
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int riscv_of_processor_hartid(struct device_node *node, unsigned long *hart)
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{
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const char *isa;
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u32 hart;
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if (!of_device_is_compatible(node, "riscv")) {
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pr_warn("Found incompatible CPU\n");
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return -ENODEV;
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}
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hart = of_get_cpu_hwid(node, 0);
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if (hart == ~0U) {
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*hart = (unsigned long) of_get_cpu_hwid(node, 0);
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if (*hart == ~0UL) {
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pr_warn("Found CPU without hart ID\n");
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return -ENODEV;
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}
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if (!of_device_is_available(node)) {
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pr_info("CPU with hartid=%d is not available\n", hart);
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pr_info("CPU with hartid=%lu is not available\n", *hart);
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return -ENODEV;
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}
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if (of_property_read_string(node, "riscv,isa", &isa)) {
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pr_warn("CPU with hartid=%d has no \"riscv,isa\" property\n", hart);
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pr_warn("CPU with hartid=%lu has no \"riscv,isa\" property\n", *hart);
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return -ENODEV;
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}
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if (isa[0] != 'r' || isa[1] != 'v') {
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pr_warn("CPU with hartid=%d has an invalid ISA of \"%s\"\n", hart, isa);
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pr_warn("CPU with hartid=%lu has an invalid ISA of \"%s\"\n", *hart, isa);
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return -ENODEV;
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}
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return hart;
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return 0;
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}
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/*
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@ -53,11 +52,16 @@ int riscv_of_processor_hartid(struct device_node *node)
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* To achieve this, we walk up the DT tree until we find an active
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* RISC-V core (HART) node and extract the cpuid from it.
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*/
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int riscv_of_parent_hartid(struct device_node *node)
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int riscv_of_parent_hartid(struct device_node *node, unsigned long *hartid)
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{
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int rc;
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for (; node; node = node->parent) {
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if (of_device_is_compatible(node, "riscv"))
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return riscv_of_processor_hartid(node);
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if (of_device_is_compatible(node, "riscv")) {
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rc = riscv_of_processor_hartid(node, hartid);
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if (!rc)
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return 0;
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}
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}
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return -1;
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@ -73,8 +73,9 @@ void __init riscv_fill_hwcap(void)
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struct device_node *node;
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const char *isa;
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char print_str[NUM_ALPHA_EXTS + 1];
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int i, j;
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int i, j, rc;
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static unsigned long isa2hwcap[256] = {0};
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unsigned long hartid;
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isa2hwcap['i'] = isa2hwcap['I'] = COMPAT_HWCAP_ISA_I;
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isa2hwcap['m'] = isa2hwcap['M'] = COMPAT_HWCAP_ISA_M;
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@ -92,7 +93,8 @@ void __init riscv_fill_hwcap(void)
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DECLARE_BITMAP(this_isa, RISCV_ISA_EXT_MAX);
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const char *temp;
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if (riscv_of_processor_hartid(node) < 0)
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rc = riscv_of_processor_hartid(node, &hartid);
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if (rc < 0)
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continue;
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if (of_property_read_string(node, "riscv,isa", &isa)) {
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@ -72,15 +72,16 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
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void __init setup_smp(void)
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{
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struct device_node *dn;
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int hart;
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unsigned long hart;
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bool found_boot_cpu = false;
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int cpuid = 1;
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int rc;
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cpu_set_ops(0);
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for_each_of_cpu_node(dn) {
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hart = riscv_of_processor_hartid(dn);
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if (hart < 0)
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rc = riscv_of_processor_hartid(dn, &hart);
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if (rc < 0)
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continue;
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if (hart == cpuid_to_hartid_map(0)) {
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@ -90,7 +91,7 @@ void __init setup_smp(void)
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continue;
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}
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if (cpuid >= NR_CPUS) {
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pr_warn("Invalid cpuid [%d] for hartid [%d]\n",
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pr_warn("Invalid cpuid [%d] for hartid [%lu]\n",
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cpuid, hart);
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continue;
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}
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@ -101,20 +101,21 @@ static irqreturn_t riscv_timer_interrupt(int irq, void *dev_id)
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static int __init riscv_timer_init_dt(struct device_node *n)
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{
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int cpuid, hartid, error;
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int cpuid, error;
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unsigned long hartid;
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struct device_node *child;
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struct irq_domain *domain;
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hartid = riscv_of_processor_hartid(n);
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if (hartid < 0) {
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pr_warn("Not valid hartid for node [%pOF] error = [%d]\n",
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error = riscv_of_processor_hartid(n, &hartid);
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if (error < 0) {
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pr_warn("Not valid hartid for node [%pOF] error = [%lu]\n",
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n, hartid);
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return hartid;
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return error;
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}
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cpuid = riscv_hartid_to_cpuid(hartid);
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if (cpuid < 0) {
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pr_warn("Invalid cpuid for hartid [%d]\n", hartid);
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pr_warn("Invalid cpuid for hartid [%lu]\n", hartid);
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return cpuid;
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}
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@ -140,7 +141,7 @@ static int __init riscv_timer_init_dt(struct device_node *n)
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return -ENODEV;
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}
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pr_info("%s: Registering clocksource cpuid [%d] hartid [%d]\n",
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pr_info("%s: Registering clocksource cpuid [%d] hartid [%lu]\n",
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__func__, cpuid, hartid);
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error = clocksource_register_hz(&riscv_clocksource, riscv_timebase);
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if (error) {
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@ -95,10 +95,11 @@ static const struct irq_domain_ops riscv_intc_domain_ops = {
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static int __init riscv_intc_init(struct device_node *node,
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struct device_node *parent)
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{
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int rc, hartid;
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int rc;
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unsigned long hartid;
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hartid = riscv_of_parent_hartid(node);
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if (hartid < 0) {
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rc = riscv_of_parent_hartid(node, &hartid);
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if (rc < 0) {
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pr_warn("unable to find hart id for %pOF\n", node);
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return 0;
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}
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@ -317,7 +317,8 @@ static int __init plic_init(struct device_node *node,
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for (i = 0; i < nr_contexts; i++) {
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struct of_phandle_args parent;
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irq_hw_number_t hwirq;
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int cpu, hartid;
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int cpu;
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unsigned long hartid;
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if (of_irq_parse_one(node, i, &parent)) {
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pr_err("failed to parse parent for context %d.\n", i);
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@ -341,8 +342,8 @@ static int __init plic_init(struct device_node *node,
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continue;
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}
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hartid = riscv_of_parent_hartid(parent.np);
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if (hartid < 0) {
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error = riscv_of_parent_hartid(parent.np, &hartid);
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if (error < 0) {
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pr_warn("failed to parse hart ID for context %d.\n", i);
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continue;
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}
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