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drm/amdgpu: fix the hang caused by PCIe link width switch

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SMU had set all the necessary fields for a link width switch
but the width switch wasn't occurring because the link was idle
in the L1 state. Setting LC_L1_RECONFIG_EN=0x1 will allow width
switches to also be initiated while in L1 instead of waiting until
the link is back in L0.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
This commit is contained in:
Evan Quan 2021-05-25 14:36:29 +08:00 committed by Alex Deucher
parent 5a5da8ae95
commit adcf949e66
3 changed files with 17 additions and 0 deletions
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1
drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h
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@ -94,6 +94,7 @@ struct amdgpu_nbio_funcs {
bool enable); bool enable);
void (*program_aspm)(struct amdgpu_device *adev); void (*program_aspm)(struct amdgpu_device *adev);
void (*apply_lc_spc_mode_wa)(struct amdgpu_device *adev); void (*apply_lc_spc_mode_wa)(struct amdgpu_device *adev);
void (*apply_l1_link_width_reconfig_wa)(struct amdgpu_device *adev);
}; };
struct amdgpu_nbio { struct amdgpu_nbio {

13
drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
View File

@ -490,6 +490,18 @@ static void nbio_v2_3_apply_lc_spc_mode_wa(struct amdgpu_device *adev)
} }
} }
static void nbio_v2_3_apply_l1_link_width_reconfig_wa(struct amdgpu_device *adev)
{
uint32_t reg_data = 0;
if (adev->asic_type != CHIP_NAVI10)
return;
reg_data = RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL);
reg_data |= PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK;
WREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL, reg_data);
}
const struct amdgpu_nbio_funcs nbio_v2_3_funcs = { const struct amdgpu_nbio_funcs nbio_v2_3_funcs = {
.get_hdp_flush_req_offset = nbio_v2_3_get_hdp_flush_req_offset, .get_hdp_flush_req_offset = nbio_v2_3_get_hdp_flush_req_offset,
.get_hdp_flush_done_offset = nbio_v2_3_get_hdp_flush_done_offset, .get_hdp_flush_done_offset = nbio_v2_3_get_hdp_flush_done_offset,
@ -512,4 +524,5 @@ const struct amdgpu_nbio_funcs nbio_v2_3_funcs = {
.enable_aspm = nbio_v2_3_enable_aspm, .enable_aspm = nbio_v2_3_enable_aspm,
.program_aspm = nbio_v2_3_program_aspm, .program_aspm = nbio_v2_3_program_aspm,
.apply_lc_spc_mode_wa = nbio_v2_3_apply_lc_spc_mode_wa, .apply_lc_spc_mode_wa = nbio_v2_3_apply_lc_spc_mode_wa,
.apply_l1_link_width_reconfig_wa = nbio_v2_3_apply_l1_link_width_reconfig_wa,
}; };

3
drivers/gpu/drm/amd/amdgpu/nv.c
View File

@ -1414,6 +1414,9 @@ static int nv_common_hw_init(void *handle)
if (adev->nbio.funcs->apply_lc_spc_mode_wa) if (adev->nbio.funcs->apply_lc_spc_mode_wa)
adev->nbio.funcs->apply_lc_spc_mode_wa(adev); adev->nbio.funcs->apply_lc_spc_mode_wa(adev);
if (adev->nbio.funcs->apply_l1_link_width_reconfig_wa)
adev->nbio.funcs->apply_l1_link_width_reconfig_wa(adev);
/* enable pcie gen2/3 link */ /* enable pcie gen2/3 link */
nv_pcie_gen3_enable(adev); nv_pcie_gen3_enable(adev);
/* enable aspm */ /* enable aspm */